1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE
23 select ARCH_HAS_KEEPINITRD
24 select ARCH_HAS_MEMBARRIER_SYNC_CORE
25 select ARCH_HAS_PTE_DEVMAP
26 select ARCH_HAS_PTE_SPECIAL
27 select ARCH_HAS_SETUP_DMA_OPS
28 select ARCH_HAS_SET_DIRECT_MAP
29 select ARCH_HAS_SET_MEMORY
30 select ARCH_HAS_STRICT_KERNEL_RWX
31 select ARCH_HAS_STRICT_MODULE_RWX
32 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
33 select ARCH_HAS_SYNC_DMA_FOR_CPU
34 select ARCH_HAS_SYSCALL_WRAPPER
35 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
36 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
37 select ARCH_HAVE_NMI_SAFE_CMPXCHG
38 select ARCH_INLINE_READ_LOCK if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
55 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
64 select ARCH_KEEP_MEMBLOCK
65 select ARCH_USE_CMPXCHG_LOCKREF
66 select ARCH_USE_QUEUED_RWLOCKS
67 select ARCH_USE_QUEUED_SPINLOCKS
68 select ARCH_SUPPORTS_MEMORY_FAILURE
69 select ARCH_SUPPORTS_ATOMIC_RMW
70 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
71 select ARCH_SUPPORTS_NUMA_BALANCING
72 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
73 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
74 select ARCH_WANT_FRAME_POINTERS
75 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
76 select ARCH_HAS_UBSAN_SANITIZE_ALL
80 select AUDIT_ARCH_COMPAT_GENERIC
81 select ARM_GIC_V2M if PCI
83 select ARM_GIC_V3_ITS if PCI
85 select BUILDTIME_EXTABLE_SORT
86 select CLONE_BACKWARDS
88 select CPU_PM if (SUSPEND || CPU_IDLE)
90 select DCACHE_WORD_ACCESS
91 select DMA_DIRECT_REMAP
94 select GENERIC_ALLOCATOR
95 select GENERIC_ARCH_TOPOLOGY
96 select GENERIC_CLOCKEVENTS
97 select GENERIC_CLOCKEVENTS_BROADCAST
98 select GENERIC_CPU_AUTOPROBE
99 select GENERIC_CPU_VULNERABILITIES
100 select GENERIC_EARLY_IOREMAP
101 select GENERIC_IDLE_POLL_SETUP
102 select GENERIC_IRQ_MULTI_HANDLER
103 select GENERIC_IRQ_PROBE
104 select GENERIC_IRQ_SHOW
105 select GENERIC_IRQ_SHOW_LEVEL
106 select GENERIC_PCI_IOMAP
107 select GENERIC_SCHED_CLOCK
108 select GENERIC_SMP_IDLE_THREAD
109 select GENERIC_STRNCPY_FROM_USER
110 select GENERIC_STRNLEN_USER
111 select GENERIC_TIME_VSYSCALL
112 select GENERIC_GETTIMEOFDAY
113 select HANDLE_DOMAIN_IRQ
114 select HARDIRQS_SW_RESEND
116 select HAVE_ACPI_APEI if (ACPI && EFI)
117 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
118 select HAVE_ARCH_AUDITSYSCALL
119 select HAVE_ARCH_BITREVERSE
120 select HAVE_ARCH_HUGE_VMAP
121 select HAVE_ARCH_JUMP_LABEL
122 select HAVE_ARCH_JUMP_LABEL_RELATIVE
123 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
124 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
125 select HAVE_ARCH_KGDB
126 select HAVE_ARCH_MMAP_RND_BITS
127 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
128 select HAVE_ARCH_PREL32_RELOCATIONS
129 select HAVE_ARCH_SECCOMP_FILTER
130 select HAVE_ARCH_STACKLEAK
131 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
132 select HAVE_ARCH_TRACEHOOK
133 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
134 select HAVE_ARCH_VMAP_STACK
135 select HAVE_ARM_SMCCC
136 select HAVE_ASM_MODVERSIONS
138 select HAVE_C_RECORDMCOUNT
139 select HAVE_CMPXCHG_DOUBLE
140 select HAVE_CMPXCHG_LOCAL
141 select HAVE_CONTEXT_TRACKING
142 select HAVE_DEBUG_BUGVERBOSE
143 select HAVE_DEBUG_KMEMLEAK
144 select HAVE_DMA_CONTIGUOUS
145 select HAVE_DYNAMIC_FTRACE
146 select HAVE_EFFICIENT_UNALIGNED_ACCESS
148 select HAVE_FTRACE_MCOUNT_RECORD
149 select HAVE_FUNCTION_TRACER
150 select HAVE_FUNCTION_ERROR_INJECTION
151 select HAVE_FUNCTION_GRAPH_TRACER
152 select HAVE_GCC_PLUGINS
153 select HAVE_HW_BREAKPOINT if PERF_EVENTS
154 select HAVE_IRQ_TIME_ACCOUNTING
155 select HAVE_MEMBLOCK_NODE_MAP if NUMA
157 select HAVE_PATA_PLATFORM
158 select HAVE_PERF_EVENTS
159 select HAVE_PERF_REGS
160 select HAVE_PERF_USER_STACK_DUMP
161 select HAVE_REGS_AND_STACK_ACCESS_API
162 select HAVE_FUNCTION_ARG_ACCESS_API
163 select HAVE_RCU_TABLE_FREE
165 select HAVE_STACKPROTECTOR
166 select HAVE_SYSCALL_TRACEPOINTS
168 select HAVE_KRETPROBES
169 select HAVE_GENERIC_VDSO
170 select IOMMU_DMA if IOMMU_SUPPORT
172 select IRQ_FORCED_THREADING
173 select MODULES_USE_ELF_RELA
174 select NEED_DMA_MAP_STATE
175 select NEED_SG_DMA_LENGTH
177 select OF_EARLY_FLATTREE
178 select PCI_DOMAINS_GENERIC if PCI
179 select PCI_ECAM if (ACPI && PCI)
180 select PCI_SYSCALL if PCI
186 select SYSCTL_EXCEPTION_TRACE
187 select THREAD_INFO_IN_TASK
189 ARM 64-bit (AArch64) Linux support.
197 config ARM64_PAGE_SHIFT
199 default 16 if ARM64_64K_PAGES
200 default 14 if ARM64_16K_PAGES
203 config ARM64_CONT_SHIFT
205 default 5 if ARM64_64K_PAGES
206 default 7 if ARM64_16K_PAGES
209 config ARCH_MMAP_RND_BITS_MIN
210 default 14 if ARM64_64K_PAGES
211 default 16 if ARM64_16K_PAGES
214 # max bits determined by the following formula:
215 # VA_BITS - PAGE_SHIFT - 3
216 config ARCH_MMAP_RND_BITS_MAX
217 default 19 if ARM64_VA_BITS=36
218 default 24 if ARM64_VA_BITS=39
219 default 27 if ARM64_VA_BITS=42
220 default 30 if ARM64_VA_BITS=47
221 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
222 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
223 default 33 if ARM64_VA_BITS=48
224 default 14 if ARM64_64K_PAGES
225 default 16 if ARM64_16K_PAGES
228 config ARCH_MMAP_RND_COMPAT_BITS_MIN
229 default 7 if ARM64_64K_PAGES
230 default 9 if ARM64_16K_PAGES
233 config ARCH_MMAP_RND_COMPAT_BITS_MAX
239 config STACKTRACE_SUPPORT
242 config ILLEGAL_POINTER_VALUE
244 default 0xdead000000000000
246 config LOCKDEP_SUPPORT
249 config TRACE_IRQFLAGS_SUPPORT
256 config GENERIC_BUG_RELATIVE_POINTERS
258 depends on GENERIC_BUG
260 config GENERIC_HWEIGHT
266 config GENERIC_CALIBRATE_DELAY
270 bool "Support DMA32 zone" if EXPERT
273 config ARCH_ENABLE_MEMORY_HOTPLUG
279 config KERNEL_MODE_NEON
282 config FIX_EARLYCON_MEM
285 config PGTABLE_LEVELS
287 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
288 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
289 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
290 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
291 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
292 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
294 config ARCH_SUPPORTS_UPROBES
297 config ARCH_PROC_KCORE_TEXT
300 config KASAN_SHADOW_OFFSET
303 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
304 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
305 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
306 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
307 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
308 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
309 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
310 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
311 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
312 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
313 default 0xffffffffffffffff
315 source "arch/arm64/Kconfig.platforms"
317 menu "Kernel Features"
319 menu "ARM errata workarounds via the alternatives framework"
321 config ARM64_WORKAROUND_CLEAN_CACHE
324 config ARM64_ERRATUM_826319
325 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
327 select ARM64_WORKAROUND_CLEAN_CACHE
329 This option adds an alternative code sequence to work around ARM
330 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
331 AXI master interface and an L2 cache.
333 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
334 and is unable to accept a certain write via this interface, it will
335 not progress on read data presented on the read data channel and the
338 The workaround promotes data cache clean instructions to
339 data cache clean-and-invalidate.
340 Please note that this does not necessarily enable the workaround,
341 as it depends on the alternative framework, which will only patch
342 the kernel if an affected CPU is detected.
346 config ARM64_ERRATUM_827319
347 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
349 select ARM64_WORKAROUND_CLEAN_CACHE
351 This option adds an alternative code sequence to work around ARM
352 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
353 master interface and an L2 cache.
355 Under certain conditions this erratum can cause a clean line eviction
356 to occur at the same time as another transaction to the same address
357 on the AMBA 5 CHI interface, which can cause data corruption if the
358 interconnect reorders the two transactions.
360 The workaround promotes data cache clean instructions to
361 data cache clean-and-invalidate.
362 Please note that this does not necessarily enable the workaround,
363 as it depends on the alternative framework, which will only patch
364 the kernel if an affected CPU is detected.
368 config ARM64_ERRATUM_824069
369 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
371 select ARM64_WORKAROUND_CLEAN_CACHE
373 This option adds an alternative code sequence to work around ARM
374 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
375 to a coherent interconnect.
377 If a Cortex-A53 processor is executing a store or prefetch for
378 write instruction at the same time as a processor in another
379 cluster is executing a cache maintenance operation to the same
380 address, then this erratum might cause a clean cache line to be
381 incorrectly marked as dirty.
383 The workaround promotes data cache clean instructions to
384 data cache clean-and-invalidate.
385 Please note that this option does not necessarily enable the
386 workaround, as it depends on the alternative framework, which will
387 only patch the kernel if an affected CPU is detected.
391 config ARM64_ERRATUM_819472
392 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
394 select ARM64_WORKAROUND_CLEAN_CACHE
396 This option adds an alternative code sequence to work around ARM
397 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
398 present when it is connected to a coherent interconnect.
400 If the processor is executing a load and store exclusive sequence at
401 the same time as a processor in another cluster is executing a cache
402 maintenance operation to the same address, then this erratum might
403 cause data corruption.
405 The workaround promotes data cache clean instructions to
406 data cache clean-and-invalidate.
407 Please note that this does not necessarily enable the workaround,
408 as it depends on the alternative framework, which will only patch
409 the kernel if an affected CPU is detected.
413 config ARM64_ERRATUM_832075
414 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
417 This option adds an alternative code sequence to work around ARM
418 erratum 832075 on Cortex-A57 parts up to r1p2.
420 Affected Cortex-A57 parts might deadlock when exclusive load/store
421 instructions to Write-Back memory are mixed with Device loads.
423 The workaround is to promote device loads to use Load-Acquire
425 Please note that this does not necessarily enable the workaround,
426 as it depends on the alternative framework, which will only patch
427 the kernel if an affected CPU is detected.
431 config ARM64_ERRATUM_834220
432 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
436 This option adds an alternative code sequence to work around ARM
437 erratum 834220 on Cortex-A57 parts up to r1p2.
439 Affected Cortex-A57 parts might report a Stage 2 translation
440 fault as the result of a Stage 1 fault for load crossing a
441 page boundary when there is a permission or device memory
442 alignment fault at Stage 1 and a translation fault at Stage 2.
444 The workaround is to verify that the Stage 1 translation
445 doesn't generate a fault before handling the Stage 2 fault.
446 Please note that this does not necessarily enable the workaround,
447 as it depends on the alternative framework, which will only patch
448 the kernel if an affected CPU is detected.
452 config ARM64_ERRATUM_845719
453 bool "Cortex-A53: 845719: a load might read incorrect data"
457 This option adds an alternative code sequence to work around ARM
458 erratum 845719 on Cortex-A53 parts up to r0p4.
460 When running a compat (AArch32) userspace on an affected Cortex-A53
461 part, a load at EL0 from a virtual address that matches the bottom 32
462 bits of the virtual address used by a recent load at (AArch64) EL1
463 might return incorrect data.
465 The workaround is to write the contextidr_el1 register on exception
466 return to a 32-bit task.
467 Please note that this does not necessarily enable the workaround,
468 as it depends on the alternative framework, which will only patch
469 the kernel if an affected CPU is detected.
473 config ARM64_ERRATUM_843419
474 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
476 select ARM64_MODULE_PLTS if MODULES
478 This option links the kernel with '--fix-cortex-a53-843419' and
479 enables PLT support to replace certain ADRP instructions, which can
480 cause subsequent memory accesses to use an incorrect address on
481 Cortex-A53 parts up to r0p4.
485 config ARM64_ERRATUM_1024718
486 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
489 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
491 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
492 update of the hardware dirty bit when the DBM/AP bits are updated
493 without a break-before-make. The workaround is to disable the usage
494 of hardware DBM locally on the affected cores. CPUs not affected by
495 this erratum will continue to use the feature.
499 config ARM64_ERRATUM_1418040
500 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
504 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
505 errata 1188873 and 1418040.
507 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
508 cause register corruption when accessing the timer registers
509 from AArch32 userspace.
513 config ARM64_ERRATUM_1165522
514 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
517 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
519 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
520 corrupted TLBs by speculating an AT instruction during a guest
525 config ARM64_ERRATUM_1286807
526 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
528 select ARM64_WORKAROUND_REPEAT_TLBI
530 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
532 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
533 address for a cacheable mapping of a location is being
534 accessed by a core while another core is remapping the virtual
535 address to a new physical page using the recommended
536 break-before-make sequence, then under very rare circumstances
537 TLBI+DSB completes before a read using the translation being
538 invalidated has been observed by other observers. The
539 workaround repeats the TLBI+DSB operation.
543 config ARM64_ERRATUM_1463225
544 bool "Cortex-A76: Software Step might prevent interrupt recognition"
547 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
549 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
550 of a system call instruction (SVC) can prevent recognition of
551 subsequent interrupts when software stepping is disabled in the
552 exception handler of the system call and either kernel debugging
553 is enabled or VHE is in use.
555 Work around the erratum by triggering a dummy step exception
556 when handling a system call from a task that is being stepped
557 in a VHE configuration of the kernel.
561 config CAVIUM_ERRATUM_22375
562 bool "Cavium erratum 22375, 24313"
565 Enable workaround for errata 22375 and 24313.
567 This implements two gicv3-its errata workarounds for ThunderX. Both
568 with a small impact affecting only ITS table allocation.
570 erratum 22375: only alloc 8MB table size
571 erratum 24313: ignore memory access type
573 The fixes are in ITS initialization and basically ignore memory access
574 type and table size provided by the TYPER and BASER registers.
578 config CAVIUM_ERRATUM_23144
579 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
583 ITS SYNC command hang for cross node io and collections/cpu mapping.
587 config CAVIUM_ERRATUM_23154
588 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
591 The gicv3 of ThunderX requires a modified version for
592 reading the IAR status to ensure data synchronization
593 (access to icc_iar1_el1 is not sync'ed before and after).
597 config CAVIUM_ERRATUM_27456
598 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
601 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
602 instructions may cause the icache to become corrupted if it
603 contains data for a non-current ASID. The fix is to
604 invalidate the icache when changing the mm context.
608 config CAVIUM_ERRATUM_30115
609 bool "Cavium erratum 30115: Guest may disable interrupts in host"
612 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
613 1.2, and T83 Pass 1.0, KVM guest execution may disable
614 interrupts in host. Trapping both GICv3 group-0 and group-1
615 accesses sidesteps the issue.
619 config QCOM_FALKOR_ERRATUM_1003
620 bool "Falkor E1003: Incorrect translation due to ASID change"
623 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
624 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
625 in TTBR1_EL1, this situation only occurs in the entry trampoline and
626 then only for entries in the walk cache, since the leaf translation
627 is unchanged. Work around the erratum by invalidating the walk cache
628 entries for the trampoline before entering the kernel proper.
630 config ARM64_WORKAROUND_REPEAT_TLBI
633 config QCOM_FALKOR_ERRATUM_1009
634 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
636 select ARM64_WORKAROUND_REPEAT_TLBI
638 On Falkor v1, the CPU may prematurely complete a DSB following a
639 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
640 one more time to fix the issue.
644 config QCOM_QDF2400_ERRATUM_0065
645 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
648 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
649 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
650 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
654 config SOCIONEXT_SYNQUACER_PREITS
655 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
658 Socionext Synquacer SoCs implement a separate h/w block to generate
659 MSI doorbell writes with non-zero values for the device ID.
663 config HISILICON_ERRATUM_161600802
664 bool "Hip07 161600802: Erroneous redistributor VLPI base"
667 The HiSilicon Hip07 SoC uses the wrong redistributor base
668 when issued ITS commands such as VMOVP and VMAPP, and requires
669 a 128kB offset to be applied to the target address in this commands.
673 config QCOM_FALKOR_ERRATUM_E1041
674 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
677 Falkor CPU may speculatively fetch instructions from an improper
678 memory location when MMU translation is changed from SCTLR_ELn[M]=1
679 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
683 config FUJITSU_ERRATUM_010001
684 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
687 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
688 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
689 accesses may cause undefined fault (Data abort, DFSC=0b111111).
690 This fault occurs under a specific hardware condition when a
691 load/store instruction performs an address translation using:
692 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
693 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
694 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
695 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
697 The workaround is to ensure these bits are clear in TCR_ELx.
698 The workaround only affects the Fujitsu-A64FX.
707 default ARM64_4K_PAGES
709 Page size (translation granule) configuration.
711 config ARM64_4K_PAGES
714 This feature enables 4KB pages support.
716 config ARM64_16K_PAGES
719 The system will use 16KB pages support. AArch32 emulation
720 requires applications compiled with 16K (or a multiple of 16K)
723 config ARM64_64K_PAGES
726 This feature enables 64KB pages support (4KB by default)
727 allowing only two levels of page tables and faster TLB
728 look-up. AArch32 emulation requires applications compiled
729 with 64K aligned segments.
734 prompt "Virtual address space size"
735 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
736 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
737 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
739 Allows choosing one of multiple possible virtual address
740 space sizes. The level of translation table is determined by
741 a combination of page size and virtual address space size.
743 config ARM64_VA_BITS_36
744 bool "36-bit" if EXPERT
745 depends on ARM64_16K_PAGES
747 config ARM64_VA_BITS_39
749 depends on ARM64_4K_PAGES
751 config ARM64_VA_BITS_42
753 depends on ARM64_64K_PAGES
755 config ARM64_VA_BITS_47
757 depends on ARM64_16K_PAGES
759 config ARM64_VA_BITS_48
762 config ARM64_VA_BITS_52
764 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
766 Enable 52-bit virtual addressing for userspace when explicitly
767 requested via a hint to mmap(). The kernel will also use 52-bit
768 virtual addresses for its own mappings (provided HW support for
769 this feature is available, otherwise it reverts to 48-bit).
771 NOTE: Enabling 52-bit virtual addressing in conjunction with
772 ARMv8.3 Pointer Authentication will result in the PAC being
773 reduced from 7 bits to 3 bits, which may have a significant
774 impact on its susceptibility to brute-force attacks.
776 If unsure, select 48-bit virtual addressing instead.
780 config ARM64_FORCE_52BIT
781 bool "Force 52-bit virtual addresses for userspace"
782 depends on ARM64_VA_BITS_52 && EXPERT
784 For systems with 52-bit userspace VAs enabled, the kernel will attempt
785 to maintain compatibility with older software by providing 48-bit VAs
786 unless a hint is supplied to mmap.
788 This configuration option disables the 48-bit compatibility logic, and
789 forces all userspace addresses to be 52-bit on HW that supports it. One
790 should only enable this configuration option for stress testing userspace
791 memory management code. If unsure say N here.
795 default 36 if ARM64_VA_BITS_36
796 default 39 if ARM64_VA_BITS_39
797 default 42 if ARM64_VA_BITS_42
798 default 47 if ARM64_VA_BITS_47
799 default 48 if ARM64_VA_BITS_48
800 default 52 if ARM64_VA_BITS_52
803 prompt "Physical address space size"
804 default ARM64_PA_BITS_48
806 Choose the maximum physical address range that the kernel will
809 config ARM64_PA_BITS_48
812 config ARM64_PA_BITS_52
813 bool "52-bit (ARMv8.2)"
814 depends on ARM64_64K_PAGES
815 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
817 Enable support for a 52-bit physical address space, introduced as
818 part of the ARMv8.2-LPA extension.
820 With this enabled, the kernel will also continue to work on CPUs that
821 do not support ARMv8.2-LPA, but with some added memory overhead (and
822 minor performance overhead).
828 default 48 if ARM64_PA_BITS_48
829 default 52 if ARM64_PA_BITS_52
831 config CPU_BIG_ENDIAN
832 bool "Build big-endian kernel"
834 Say Y if you plan on running a kernel in big-endian mode.
837 bool "Multi-core scheduler support"
839 Multi-core scheduler support improves the CPU scheduler's decision
840 making when dealing with multi-core CPU chips at a cost of slightly
841 increased overhead in some places. If unsure say N here.
844 bool "SMT scheduler support"
846 Improves the CPU scheduler's decision making when dealing with
847 MultiThreading at a cost of slightly increased overhead in some
848 places. If unsure say N here.
851 int "Maximum number of CPUs (2-4096)"
856 bool "Support for hot-pluggable CPUs"
857 select GENERIC_IRQ_MIGRATION
859 Say Y here to experiment with turning CPUs off and on. CPUs
860 can be controlled through /sys/devices/system/cpu.
862 # Common NUMA Features
864 bool "Numa Memory Allocation and Scheduler Support"
865 select ACPI_NUMA if ACPI
868 Enable NUMA (Non Uniform Memory Access) support.
870 The kernel will try to allocate memory used by a CPU on the
871 local memory of the CPU and add some more
872 NUMA awareness to the kernel.
875 int "Maximum NUMA Nodes (as a power of 2)"
878 depends on NEED_MULTIPLE_NODES
880 Specify the maximum number of NUMA Nodes available on the target
881 system. Increases memory reserved to accommodate various tables.
883 config USE_PERCPU_NUMA_NODE_ID
887 config HAVE_SETUP_PER_CPU_AREA
891 config NEED_PER_CPU_EMBED_FIRST_CHUNK
898 source "kernel/Kconfig.hz"
900 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
903 config ARCH_SPARSEMEM_ENABLE
905 select SPARSEMEM_VMEMMAP_ENABLE
907 config ARCH_SPARSEMEM_DEFAULT
908 def_bool ARCH_SPARSEMEM_ENABLE
910 config ARCH_SELECT_MEMORY_MODEL
911 def_bool ARCH_SPARSEMEM_ENABLE
913 config ARCH_FLATMEM_ENABLE
916 config HAVE_ARCH_PFN_VALID
919 config HW_PERF_EVENTS
923 config SYS_SUPPORTS_HUGETLBFS
926 config ARCH_WANT_HUGE_PMD_SHARE
928 config ARCH_HAS_CACHE_LINE_SIZE
931 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
932 def_bool y if PGTABLE_LEVELS > 2
935 bool "Enable seccomp to safely compute untrusted bytecode"
937 This kernel feature is useful for number crunching applications
938 that may need to compute untrusted bytecode during their
939 execution. By using pipes or other transports made available to
940 the process as file descriptors supporting the read/write
941 syscalls, it's possible to isolate those applications in
942 their own address space using seccomp. Once seccomp is
943 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
944 and the task is only allowed to execute a few safe syscalls
945 defined by each seccomp mode.
948 bool "Enable paravirtualization code"
950 This changes the kernel so it can modify itself when it is run
951 under a hypervisor, potentially improving performance significantly
952 over full virtualization.
954 config PARAVIRT_TIME_ACCOUNTING
955 bool "Paravirtual steal time accounting"
958 Select this option to enable fine granularity task steal time
959 accounting. Time spent executing other tasks in parallel with
960 the current vCPU is discounted from the vCPU power. To account for
961 that, there can be a small performance impact.
963 If in doubt, say N here.
966 depends on PM_SLEEP_SMP
968 bool "kexec system call"
970 kexec is a system call that implements the ability to shutdown your
971 current kernel, and to start another kernel. It is like a reboot
972 but it is independent of the system firmware. And like a reboot
973 you can start any kernel with it, not just Linux.
976 bool "kexec file based system call"
979 This is new version of kexec system call. This system call is
980 file based and takes file descriptors as system call argument
981 for kernel and initramfs as opposed to list of segments as
982 accepted by previous system call.
985 bool "Verify kernel signature during kexec_file_load() syscall"
986 depends on KEXEC_FILE
988 Select this option to verify a signature with loaded kernel
989 image. If configured, any attempt of loading a image without
990 valid signature will fail.
992 In addition to that option, you need to enable signature
993 verification for the corresponding kernel image type being
994 loaded in order for this to work.
996 config KEXEC_IMAGE_VERIFY_SIG
997 bool "Enable Image signature verification support"
1000 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1002 Enable Image signature verification support.
1004 comment "Support for PE file signature verification disabled"
1005 depends on KEXEC_SIG
1006 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1009 bool "Build kdump crash kernel"
1011 Generate crash dump after being started by kexec. This should
1012 be normally only set in special crash dump kernels which are
1013 loaded in the main kernel with kexec-tools into a specially
1014 reserved region and then later executed after a crash by
1017 For more details see Documentation/admin-guide/kdump/kdump.rst
1024 bool "Xen guest support on ARM64"
1025 depends on ARM64 && OF
1029 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1031 config FORCE_MAX_ZONEORDER
1033 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1034 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1037 The kernel memory allocator divides physically contiguous memory
1038 blocks into "zones", where each zone is a power of two number of
1039 pages. This option selects the largest power of two that the kernel
1040 keeps in the memory allocator. If you need to allocate very large
1041 blocks of physically contiguous memory, then you may need to
1042 increase this value.
1044 This config option is actually maximum order plus one. For example,
1045 a value of 11 means that the largest free memory block is 2^10 pages.
1047 We make sure that we can allocate upto a HugePage size for each configuration.
1049 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1051 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1052 4M allocations matching the default size used by generic code.
1054 config UNMAP_KERNEL_AT_EL0
1055 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1058 Speculation attacks against some high-performance processors can
1059 be used to bypass MMU permission checks and leak kernel data to
1060 userspace. This can be defended against by unmapping the kernel
1061 when running in userspace, mapping it back in on exception entry
1062 via a trampoline page in the vector table.
1066 config HARDEN_BRANCH_PREDICTOR
1067 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1070 Speculation attacks against some high-performance processors rely on
1071 being able to manipulate the branch predictor for a victim context by
1072 executing aliasing branches in the attacker context. Such attacks
1073 can be partially mitigated against by clearing internal branch
1074 predictor state and limiting the prediction logic in some situations.
1076 This config option will take CPU-specific actions to harden the
1077 branch predictor against aliasing attacks and may rely on specific
1078 instruction sequences or control bits being set by the system
1083 config HARDEN_EL2_VECTORS
1084 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1087 Speculation attacks against some high-performance processors can
1088 be used to leak privileged information such as the vector base
1089 register, resulting in a potential defeat of the EL2 layout
1092 This config option will map the vectors to a fixed location,
1093 independent of the EL2 code mapping, so that revealing VBAR_EL2
1094 to an attacker does not give away any extra information. This
1095 only gets enabled on affected CPUs.
1100 bool "Speculative Store Bypass Disable" if EXPERT
1103 This enables mitigation of the bypassing of previous stores
1104 by speculative loads.
1108 config RODATA_FULL_DEFAULT_ENABLED
1109 bool "Apply r/o permissions of VM areas also to their linear aliases"
1112 Apply read-only attributes of VM areas to the linear alias of
1113 the backing pages as well. This prevents code or read-only data
1114 from being modified (inadvertently or intentionally) via another
1115 mapping of the same memory page. This additional enhancement can
1116 be turned off at runtime by passing rodata=[off|on] (and turned on
1117 with rodata=full if this option is set to 'n')
1119 This requires the linear region to be mapped down to pages,
1120 which may adversely affect performance in some cases.
1122 config ARM64_SW_TTBR0_PAN
1123 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1125 Enabling this option prevents the kernel from accessing
1126 user-space memory directly by pointing TTBR0_EL1 to a reserved
1127 zeroed area and reserved ASID. The user access routines
1128 restore the valid TTBR0_EL1 temporarily.
1130 config ARM64_TAGGED_ADDR_ABI
1131 bool "Enable the tagged user addresses syscall ABI"
1134 When this option is enabled, user applications can opt in to a
1135 relaxed ABI via prctl() allowing tagged addresses to be passed
1136 to system calls as pointer arguments. For details, see
1137 Documentation/arm64/tagged-address-abi.rst.
1140 bool "Kernel support for 32-bit EL0"
1141 depends on ARM64_4K_PAGES || EXPERT
1142 select COMPAT_BINFMT_ELF if BINFMT_ELF
1144 select OLD_SIGSUSPEND3
1145 select COMPAT_OLD_SIGACTION
1147 This option enables support for a 32-bit EL0 running under a 64-bit
1148 kernel at EL1. AArch32-specific components such as system calls,
1149 the user helper functions, VFP support and the ptrace interface are
1150 handled appropriately by the kernel.
1152 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1153 that you will only be able to execute AArch32 binaries that were compiled
1154 with page size aligned segments.
1156 If you want to execute 32-bit userspace applications, say Y.
1160 config KUSER_HELPERS
1161 bool "Enable kuser helpers page for 32-bit applications"
1164 Warning: disabling this option may break 32-bit user programs.
1166 Provide kuser helpers to compat tasks. The kernel provides
1167 helper code to userspace in read only form at a fixed location
1168 to allow userspace to be independent of the CPU type fitted to
1169 the system. This permits binaries to be run on ARMv4 through
1170 to ARMv8 without modification.
1172 See Documentation/arm/kernel_user_helpers.rst for details.
1174 However, the fixed address nature of these helpers can be used
1175 by ROP (return orientated programming) authors when creating
1178 If all of the binaries and libraries which run on your platform
1179 are built specifically for your platform, and make no use of
1180 these helpers, then you can turn this option off to hinder
1181 such exploits. However, in that case, if a binary or library
1182 relying on those helpers is run, it will not function correctly.
1184 Say N here only if you are absolutely certain that you do not
1185 need these helpers; otherwise, the safe option is to say Y.
1188 bool "Enable vDSO for 32-bit applications"
1189 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1190 select GENERIC_COMPAT_VDSO
1193 Place in the process address space of 32-bit applications an
1194 ELF shared object providing fast implementations of gettimeofday
1197 You must have a 32-bit build of glibc 2.22 or later for programs
1198 to seamlessly take advantage of this.
1200 menuconfig ARMV8_DEPRECATED
1201 bool "Emulate deprecated/obsolete ARMv8 instructions"
1204 Legacy software support may require certain instructions
1205 that have been deprecated or obsoleted in the architecture.
1207 Enable this config to enable selective emulation of these
1214 config SWP_EMULATION
1215 bool "Emulate SWP/SWPB instructions"
1217 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1218 they are always undefined. Say Y here to enable software
1219 emulation of these instructions for userspace using LDXR/STXR.
1221 In some older versions of glibc [<=2.8] SWP is used during futex
1222 trylock() operations with the assumption that the code will not
1223 be preempted. This invalid assumption may be more likely to fail
1224 with SWP emulation enabled, leading to deadlock of the user
1227 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1228 on an external transaction monitoring block called a global
1229 monitor to maintain update atomicity. If your system does not
1230 implement a global monitor, this option can cause programs that
1231 perform SWP operations to uncached memory to deadlock.
1235 config CP15_BARRIER_EMULATION
1236 bool "Emulate CP15 Barrier instructions"
1238 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1239 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1240 strongly recommended to use the ISB, DSB, and DMB
1241 instructions instead.
1243 Say Y here to enable software emulation of these
1244 instructions for AArch32 userspace code. When this option is
1245 enabled, CP15 barrier usage is traced which can help
1246 identify software that needs updating.
1250 config SETEND_EMULATION
1251 bool "Emulate SETEND instruction"
1253 The SETEND instruction alters the data-endianness of the
1254 AArch32 EL0, and is deprecated in ARMv8.
1256 Say Y here to enable software emulation of the instruction
1257 for AArch32 userspace code.
1259 Note: All the cpus on the system must have mixed endian support at EL0
1260 for this feature to be enabled. If a new CPU - which doesn't support mixed
1261 endian - is hotplugged in after this feature has been enabled, there could
1262 be unexpected results in the applications.
1269 menu "ARMv8.1 architectural features"
1271 config ARM64_HW_AFDBM
1272 bool "Support for hardware updates of the Access and Dirty page flags"
1275 The ARMv8.1 architecture extensions introduce support for
1276 hardware updates of the access and dirty information in page
1277 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1278 capable processors, accesses to pages with PTE_AF cleared will
1279 set this bit instead of raising an access flag fault.
1280 Similarly, writes to read-only pages with the DBM bit set will
1281 clear the read-only bit (AP[2]) instead of raising a
1284 Kernels built with this configuration option enabled continue
1285 to work on pre-ARMv8.1 hardware and the performance impact is
1286 minimal. If unsure, say Y.
1289 bool "Enable support for Privileged Access Never (PAN)"
1292 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1293 prevents the kernel or hypervisor from accessing user-space (EL0)
1296 Choosing this option will cause any unprotected (not using
1297 copy_to_user et al) memory access to fail with a permission fault.
1299 The feature is detected at runtime, and will remain as a 'nop'
1300 instruction if the cpu does not implement the feature.
1302 config ARM64_LSE_ATOMICS
1303 bool "Atomic instructions"
1304 depends on JUMP_LABEL
1307 As part of the Large System Extensions, ARMv8.1 introduces new
1308 atomic instructions that are designed specifically to scale in
1311 Say Y here to make use of these instructions for the in-kernel
1312 atomic routines. This incurs a small overhead on CPUs that do
1313 not support these instructions and requires the kernel to be
1314 built with binutils >= 2.25 in order for the new instructions
1318 bool "Enable support for Virtualization Host Extensions (VHE)"
1321 Virtualization Host Extensions (VHE) allow the kernel to run
1322 directly at EL2 (instead of EL1) on processors that support
1323 it. This leads to better performance for KVM, as they reduce
1324 the cost of the world switch.
1326 Selecting this option allows the VHE feature to be detected
1327 at runtime, and does not affect processors that do not
1328 implement this feature.
1332 menu "ARMv8.2 architectural features"
1335 bool "Enable support for User Access Override (UAO)"
1338 User Access Override (UAO; part of the ARMv8.2 Extensions)
1339 causes the 'unprivileged' variant of the load/store instructions to
1340 be overridden to be privileged.
1342 This option changes get_user() and friends to use the 'unprivileged'
1343 variant of the load/store instructions. This ensures that user-space
1344 really did have access to the supplied memory. When addr_limit is
1345 set to kernel memory the UAO bit will be set, allowing privileged
1346 access to kernel memory.
1348 Choosing this option will cause copy_to_user() et al to use user-space
1351 The feature is detected at runtime, the kernel will use the
1352 regular load/store instructions if the cpu does not implement the
1356 bool "Enable support for persistent memory"
1357 select ARCH_HAS_PMEM_API
1358 select ARCH_HAS_UACCESS_FLUSHCACHE
1360 Say Y to enable support for the persistent memory API based on the
1361 ARMv8.2 DCPoP feature.
1363 The feature is detected at runtime, and the kernel will use DC CVAC
1364 operations if DC CVAP is not supported (following the behaviour of
1365 DC CVAP itself if the system does not define a point of persistence).
1367 config ARM64_RAS_EXTN
1368 bool "Enable support for RAS CPU Extensions"
1371 CPUs that support the Reliability, Availability and Serviceability
1372 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1373 errors, classify them and report them to software.
1375 On CPUs with these extensions system software can use additional
1376 barriers to determine if faults are pending and read the
1377 classification from a new set of registers.
1379 Selecting this feature will allow the kernel to use these barriers
1380 and access the new registers if the system supports the extension.
1381 Platform RAS features may additionally depend on firmware support.
1384 bool "Enable support for Common Not Private (CNP) translations"
1386 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1388 Common Not Private (CNP) allows translation table entries to
1389 be shared between different PEs in the same inner shareable
1390 domain, so the hardware can use this fact to optimise the
1391 caching of such entries in the TLB.
1393 Selecting this option allows the CNP feature to be detected
1394 at runtime, and does not affect PEs that do not implement
1399 menu "ARMv8.3 architectural features"
1401 config ARM64_PTR_AUTH
1402 bool "Enable support for pointer authentication"
1404 depends on !KVM || ARM64_VHE
1406 Pointer authentication (part of the ARMv8.3 Extensions) provides
1407 instructions for signing and authenticating pointers against secret
1408 keys, which can be used to mitigate Return Oriented Programming (ROP)
1411 This option enables these instructions at EL0 (i.e. for userspace).
1413 Choosing this option will cause the kernel to initialise secret keys
1414 for each process at exec() time, with these keys being
1415 context-switched along with the process.
1417 The feature is detected at runtime. If the feature is not present in
1418 hardware it will not be advertised to userspace/KVM guest nor will it
1419 be enabled. However, KVM guest also require VHE mode and hence
1420 CONFIG_ARM64_VHE=y option to use this feature.
1425 bool "ARM Scalable Vector Extension support"
1427 depends on !KVM || ARM64_VHE
1429 The Scalable Vector Extension (SVE) is an extension to the AArch64
1430 execution state which complements and extends the SIMD functionality
1431 of the base architecture to support much larger vectors and to enable
1432 additional vectorisation opportunities.
1434 To enable use of this extension on CPUs that implement it, say Y.
1436 On CPUs that support the SVE2 extensions, this option will enable
1439 Note that for architectural reasons, firmware _must_ implement SVE
1440 support when running on SVE capable hardware. The required support
1443 * version 1.5 and later of the ARM Trusted Firmware
1444 * the AArch64 boot wrapper since commit 5e1261e08abf
1445 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1447 For other firmware implementations, consult the firmware documentation
1450 If you need the kernel to boot on SVE-capable hardware with broken
1451 firmware, you may need to say N here until you get your firmware
1452 fixed. Otherwise, you may experience firmware panics or lockups when
1453 booting the kernel. If unsure and you are not observing these
1454 symptoms, you should assume that it is safe to say Y.
1456 CPUs that support SVE are architecturally required to support the
1457 Virtualization Host Extensions (VHE), so the kernel makes no
1458 provision for supporting SVE alongside KVM without VHE enabled.
1459 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1460 KVM in the same kernel image.
1462 config ARM64_MODULE_PLTS
1463 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1465 select HAVE_MOD_ARCH_SPECIFIC
1467 Allocate PLTs when loading modules so that jumps and calls whose
1468 targets are too far away for their relative offsets to be encoded
1469 in the instructions themselves can be bounced via veneers in the
1470 module's PLT. This allows modules to be allocated in the generic
1471 vmalloc area after the dedicated module memory area has been
1474 When running with address space randomization (KASLR), the module
1475 region itself may be too far away for ordinary relative jumps and
1476 calls, and so in that case, module PLTs are required and cannot be
1479 Specific errata workaround(s) might also force module PLTs to be
1480 enabled (ARM64_ERRATUM_843419).
1482 config ARM64_PSEUDO_NMI
1483 bool "Support for NMI-like interrupts"
1484 select CONFIG_ARM_GIC_V3
1486 Adds support for mimicking Non-Maskable Interrupts through the use of
1487 GIC interrupt priority. This support requires version 3 or later of
1490 This high priority configuration for interrupts needs to be
1491 explicitly enabled by setting the kernel parameter
1492 "irqchip.gicv3_pseudo_nmi" to 1.
1497 config ARM64_DEBUG_PRIORITY_MASKING
1498 bool "Debug interrupt priority masking"
1500 This adds runtime checks to functions enabling/disabling
1501 interrupts when using priority masking. The additional checks verify
1502 the validity of ICC_PMR_EL1 when calling concerned functions.
1509 select ARCH_HAS_RELR
1511 This builds the kernel as a Position Independent Executable (PIE),
1512 which retains all relocation metadata required to relocate the
1513 kernel binary at runtime to a different virtual address than the
1514 address it was linked at.
1515 Since AArch64 uses the RELA relocation format, this requires a
1516 relocation pass at runtime even if the kernel is loaded at the
1517 same address it was linked at.
1519 config RANDOMIZE_BASE
1520 bool "Randomize the address of the kernel image"
1521 select ARM64_MODULE_PLTS if MODULES
1524 Randomizes the virtual address at which the kernel image is
1525 loaded, as a security feature that deters exploit attempts
1526 relying on knowledge of the location of kernel internals.
1528 It is the bootloader's job to provide entropy, by passing a
1529 random u64 value in /chosen/kaslr-seed at kernel entry.
1531 When booting via the UEFI stub, it will invoke the firmware's
1532 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1533 to the kernel proper. In addition, it will randomise the physical
1534 location of the kernel Image as well.
1538 config RANDOMIZE_MODULE_REGION_FULL
1539 bool "Randomize the module region over a 4 GB range"
1540 depends on RANDOMIZE_BASE
1543 Randomizes the location of the module region inside a 4 GB window
1544 covering the core kernel. This way, it is less likely for modules
1545 to leak information about the location of core kernel data structures
1546 but it does imply that function calls between modules and the core
1547 kernel will need to be resolved via veneers in the module PLT.
1549 When this option is not set, the module region will be randomized over
1550 a limited range that contains the [_stext, _etext] interval of the
1551 core kernel, so branch relocations are always in range.
1553 config CC_HAVE_STACKPROTECTOR_SYSREG
1554 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1556 config STACKPROTECTOR_PER_TASK
1558 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1564 config ARM64_ACPI_PARKING_PROTOCOL
1565 bool "Enable support for the ARM64 ACPI parking protocol"
1568 Enable support for the ARM64 ACPI parking protocol. If disabled
1569 the kernel will not allow booting through the ARM64 ACPI parking
1570 protocol even if the corresponding data is present in the ACPI
1574 string "Default kernel command string"
1577 Provide a set of default command-line options at build time by
1578 entering them here. As a minimum, you should specify the the
1579 root device (e.g. root=/dev/nfs).
1581 config CMDLINE_FORCE
1582 bool "Always use the default kernel command string"
1584 Always use the default kernel command string, even if the boot
1585 loader passes other arguments to the kernel.
1586 This is useful if you cannot or don't want to change the
1587 command-line options your boot loader passes to the kernel.
1593 bool "UEFI runtime support"
1594 depends on OF && !CPU_BIG_ENDIAN
1595 depends on KERNEL_MODE_NEON
1596 select ARCH_SUPPORTS_ACPI
1599 select EFI_PARAMS_FROM_FDT
1600 select EFI_RUNTIME_WRAPPERS
1605 This option provides support for runtime services provided
1606 by UEFI firmware (such as non-volatile variables, realtime
1607 clock, and platform reset). A UEFI stub is also provided to
1608 allow the kernel to be booted as an EFI application. This
1609 is only useful on systems that have UEFI firmware.
1612 bool "Enable support for SMBIOS (DMI) tables"
1616 This enables SMBIOS/DMI feature for systems.
1618 This option is only useful on systems that have UEFI firmware.
1619 However, even with this option, the resultant kernel should
1620 continue to boot on existing non-UEFI platforms.
1624 config SYSVIPC_COMPAT
1626 depends on COMPAT && SYSVIPC
1628 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1630 depends on HUGETLB_PAGE && MIGRATION
1632 menu "Power management options"
1634 source "kernel/power/Kconfig"
1636 config ARCH_HIBERNATION_POSSIBLE
1640 config ARCH_HIBERNATION_HEADER
1642 depends on HIBERNATION
1644 config ARCH_SUSPEND_POSSIBLE
1649 menu "CPU Power Management"
1651 source "drivers/cpuidle/Kconfig"
1653 source "drivers/cpufreq/Kconfig"
1657 source "drivers/firmware/Kconfig"
1659 source "drivers/acpi/Kconfig"
1661 source "arch/arm64/kvm/Kconfig"
1664 source "arch/arm64/crypto/Kconfig"