3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ACPI_MCFG if ACPI
7 select ACPI_SPCR_TABLE if ACPI
8 select ARCH_CLOCKSOURCE_DATA
9 select ARCH_HAS_DEBUG_VIRTUAL
10 select ARCH_HAS_DEVMEM_IS_ALLOWED
11 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
12 select ARCH_HAS_ELF_RANDOMIZE
13 select ARCH_HAS_GCOV_PROFILE_ALL
14 select ARCH_HAS_GIGANTIC_PAGE
16 select ARCH_HAS_SET_MEMORY
17 select ARCH_HAS_SG_CHAIN
18 select ARCH_HAS_STRICT_KERNEL_RWX
19 select ARCH_HAS_STRICT_MODULE_RWX
20 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
21 select ARCH_USE_CMPXCHG_LOCKREF
22 select ARCH_SUPPORTS_ATOMIC_RMW
23 select ARCH_SUPPORTS_NUMA_BALANCING
24 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
25 select ARCH_WANT_FRAME_POINTERS
26 select ARCH_HAS_UBSAN_SANITIZE_ALL
30 select AUDIT_ARCH_COMPAT_GENERIC
31 select ARM_GIC_V2M if PCI
33 select ARM_GIC_V3_ITS if PCI
35 select BUILDTIME_EXTABLE_SORT
36 select CLONE_BACKWARDS
38 select CPU_PM if (SUSPEND || CPU_IDLE)
39 select DCACHE_WORD_ACCESS
42 select GENERIC_ALLOCATOR
43 select GENERIC_CLOCKEVENTS
44 select GENERIC_CLOCKEVENTS_BROADCAST
45 select GENERIC_CPU_AUTOPROBE
46 select GENERIC_EARLY_IOREMAP
47 select GENERIC_IDLE_POLL_SETUP
48 select GENERIC_IRQ_PROBE
49 select GENERIC_IRQ_SHOW
50 select GENERIC_IRQ_SHOW_LEVEL
51 select GENERIC_PCI_IOMAP
52 select GENERIC_SCHED_CLOCK
53 select GENERIC_SMP_IDLE_THREAD
54 select GENERIC_STRNCPY_FROM_USER
55 select GENERIC_STRNLEN_USER
56 select GENERIC_TIME_VSYSCALL
57 select HANDLE_DOMAIN_IRQ
58 select HARDIRQS_SW_RESEND
59 select HAVE_ACPI_APEI if (ACPI && EFI)
60 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
61 select HAVE_ARCH_AUDITSYSCALL
62 select HAVE_ARCH_BITREVERSE
63 select HAVE_ARCH_HARDENED_USERCOPY
64 select HAVE_ARCH_HUGE_VMAP
65 select HAVE_ARCH_JUMP_LABEL
66 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
68 select HAVE_ARCH_MMAP_RND_BITS
69 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
70 select HAVE_ARCH_SECCOMP_FILTER
71 select HAVE_ARCH_TRACEHOOK
72 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
75 select HAVE_C_RECORDMCOUNT
76 select HAVE_CC_STACKPROTECTOR
77 select HAVE_CMPXCHG_DOUBLE
78 select HAVE_CMPXCHG_LOCAL
79 select HAVE_CONTEXT_TRACKING
80 select HAVE_DEBUG_BUGVERBOSE
81 select HAVE_DEBUG_KMEMLEAK
82 select HAVE_DMA_API_DEBUG
83 select HAVE_DMA_CONTIGUOUS
84 select HAVE_DYNAMIC_FTRACE
85 select HAVE_EFFICIENT_UNALIGNED_ACCESS
86 select HAVE_FTRACE_MCOUNT_RECORD
87 select HAVE_FUNCTION_TRACER
88 select HAVE_FUNCTION_GRAPH_TRACER
89 select HAVE_GCC_PLUGINS
90 select HAVE_GENERIC_DMA_COHERENT
91 select HAVE_HW_BREAKPOINT if PERF_EVENTS
92 select HAVE_IRQ_TIME_ACCOUNTING
94 select HAVE_MEMBLOCK_NODE_MAP if NUMA
95 select HAVE_PATA_PLATFORM
96 select HAVE_PERF_EVENTS
98 select HAVE_PERF_USER_STACK_DUMP
99 select HAVE_REGS_AND_STACK_ACCESS_API
100 select HAVE_RCU_TABLE_FREE
101 select HAVE_SYSCALL_TRACEPOINTS
103 select HAVE_KRETPROBES
104 select IOMMU_DMA if IOMMU_SUPPORT
106 select IRQ_FORCED_THREADING
107 select MODULES_USE_ELF_RELA
110 select OF_EARLY_FLATTREE
111 select OF_RESERVED_MEM
112 select PCI_ECAM if ACPI
116 select SYSCTL_EXCEPTION_TRACE
117 select THREAD_INFO_IN_TASK
119 ARM 64-bit (AArch64) Linux support.
124 config ARCH_PHYS_ADDR_T_64BIT
130 config ARM64_PAGE_SHIFT
132 default 16 if ARM64_64K_PAGES
133 default 14 if ARM64_16K_PAGES
136 config ARM64_CONT_SHIFT
138 default 5 if ARM64_64K_PAGES
139 default 7 if ARM64_16K_PAGES
142 config ARCH_MMAP_RND_BITS_MIN
143 default 14 if ARM64_64K_PAGES
144 default 16 if ARM64_16K_PAGES
147 # max bits determined by the following formula:
148 # VA_BITS - PAGE_SHIFT - 3
149 config ARCH_MMAP_RND_BITS_MAX
150 default 19 if ARM64_VA_BITS=36
151 default 24 if ARM64_VA_BITS=39
152 default 27 if ARM64_VA_BITS=42
153 default 30 if ARM64_VA_BITS=47
154 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
155 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
156 default 33 if ARM64_VA_BITS=48
157 default 14 if ARM64_64K_PAGES
158 default 16 if ARM64_16K_PAGES
161 config ARCH_MMAP_RND_COMPAT_BITS_MIN
162 default 7 if ARM64_64K_PAGES
163 default 9 if ARM64_16K_PAGES
166 config ARCH_MMAP_RND_COMPAT_BITS_MAX
172 config STACKTRACE_SUPPORT
175 config ILLEGAL_POINTER_VALUE
177 default 0xdead000000000000
179 config LOCKDEP_SUPPORT
182 config TRACE_IRQFLAGS_SUPPORT
185 config RWSEM_XCHGADD_ALGORITHM
192 config GENERIC_BUG_RELATIVE_POINTERS
194 depends on GENERIC_BUG
196 config GENERIC_HWEIGHT
202 config GENERIC_CALIBRATE_DELAY
208 config HAVE_GENERIC_RCU_GUP
211 config ARCH_DMA_ADDR_T_64BIT
214 config NEED_DMA_MAP_STATE
217 config NEED_SG_DMA_LENGTH
229 config KERNEL_MODE_NEON
232 config FIX_EARLYCON_MEM
235 config PGTABLE_LEVELS
237 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
238 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
239 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
240 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
241 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
242 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
244 config ARCH_SUPPORTS_UPROBES
247 source "init/Kconfig"
249 source "kernel/Kconfig.freezer"
251 source "arch/arm64/Kconfig.platforms"
258 This feature enables support for PCI bus system. If you say Y
259 here, the kernel will include drivers and infrastructure code
260 to support PCI bus devices.
265 config PCI_DOMAINS_GENERIC
271 source "drivers/pci/Kconfig"
275 menu "Kernel Features"
277 menu "ARM errata workarounds via the alternatives framework"
279 config ARM64_ERRATUM_826319
280 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
283 This option adds an alternative code sequence to work around ARM
284 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
285 AXI master interface and an L2 cache.
287 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
288 and is unable to accept a certain write via this interface, it will
289 not progress on read data presented on the read data channel and the
292 The workaround promotes data cache clean instructions to
293 data cache clean-and-invalidate.
294 Please note that this does not necessarily enable the workaround,
295 as it depends on the alternative framework, which will only patch
296 the kernel if an affected CPU is detected.
300 config ARM64_ERRATUM_827319
301 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
304 This option adds an alternative code sequence to work around ARM
305 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
306 master interface and an L2 cache.
308 Under certain conditions this erratum can cause a clean line eviction
309 to occur at the same time as another transaction to the same address
310 on the AMBA 5 CHI interface, which can cause data corruption if the
311 interconnect reorders the two transactions.
313 The workaround promotes data cache clean instructions to
314 data cache clean-and-invalidate.
315 Please note that this does not necessarily enable the workaround,
316 as it depends on the alternative framework, which will only patch
317 the kernel if an affected CPU is detected.
321 config ARM64_ERRATUM_824069
322 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
325 This option adds an alternative code sequence to work around ARM
326 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
327 to a coherent interconnect.
329 If a Cortex-A53 processor is executing a store or prefetch for
330 write instruction at the same time as a processor in another
331 cluster is executing a cache maintenance operation to the same
332 address, then this erratum might cause a clean cache line to be
333 incorrectly marked as dirty.
335 The workaround promotes data cache clean instructions to
336 data cache clean-and-invalidate.
337 Please note that this option does not necessarily enable the
338 workaround, as it depends on the alternative framework, which will
339 only patch the kernel if an affected CPU is detected.
343 config ARM64_ERRATUM_819472
344 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
347 This option adds an alternative code sequence to work around ARM
348 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
349 present when it is connected to a coherent interconnect.
351 If the processor is executing a load and store exclusive sequence at
352 the same time as a processor in another cluster is executing a cache
353 maintenance operation to the same address, then this erratum might
354 cause data corruption.
356 The workaround promotes data cache clean instructions to
357 data cache clean-and-invalidate.
358 Please note that this does not necessarily enable the workaround,
359 as it depends on the alternative framework, which will only patch
360 the kernel if an affected CPU is detected.
364 config ARM64_ERRATUM_832075
365 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
368 This option adds an alternative code sequence to work around ARM
369 erratum 832075 on Cortex-A57 parts up to r1p2.
371 Affected Cortex-A57 parts might deadlock when exclusive load/store
372 instructions to Write-Back memory are mixed with Device loads.
374 The workaround is to promote device loads to use Load-Acquire
376 Please note that this does not necessarily enable the workaround,
377 as it depends on the alternative framework, which will only patch
378 the kernel if an affected CPU is detected.
382 config ARM64_ERRATUM_834220
383 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
387 This option adds an alternative code sequence to work around ARM
388 erratum 834220 on Cortex-A57 parts up to r1p2.
390 Affected Cortex-A57 parts might report a Stage 2 translation
391 fault as the result of a Stage 1 fault for load crossing a
392 page boundary when there is a permission or device memory
393 alignment fault at Stage 1 and a translation fault at Stage 2.
395 The workaround is to verify that the Stage 1 translation
396 doesn't generate a fault before handling the Stage 2 fault.
397 Please note that this does not necessarily enable the workaround,
398 as it depends on the alternative framework, which will only patch
399 the kernel if an affected CPU is detected.
403 config ARM64_ERRATUM_845719
404 bool "Cortex-A53: 845719: a load might read incorrect data"
408 This option adds an alternative code sequence to work around ARM
409 erratum 845719 on Cortex-A53 parts up to r0p4.
411 When running a compat (AArch32) userspace on an affected Cortex-A53
412 part, a load at EL0 from a virtual address that matches the bottom 32
413 bits of the virtual address used by a recent load at (AArch64) EL1
414 might return incorrect data.
416 The workaround is to write the contextidr_el1 register on exception
417 return to a 32-bit task.
418 Please note that this does not necessarily enable the workaround,
419 as it depends on the alternative framework, which will only patch
420 the kernel if an affected CPU is detected.
424 config ARM64_ERRATUM_843419
425 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
427 select ARM64_MODULE_CMODEL_LARGE if MODULES
429 This option links the kernel with '--fix-cortex-a53-843419' and
430 builds modules using the large memory model in order to avoid the use
431 of the ADRP instruction, which can cause a subsequent memory access
432 to use an incorrect address on Cortex-A53 parts up to r0p4.
436 config CAVIUM_ERRATUM_22375
437 bool "Cavium erratum 22375, 24313"
440 Enable workaround for erratum 22375, 24313.
442 This implements two gicv3-its errata workarounds for ThunderX. Both
443 with small impact affecting only ITS table allocation.
445 erratum 22375: only alloc 8MB table size
446 erratum 24313: ignore memory access type
448 The fixes are in ITS initialization and basically ignore memory access
449 type and table size provided by the TYPER and BASER registers.
453 config CAVIUM_ERRATUM_23144
454 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
458 ITS SYNC command hang for cross node io and collections/cpu mapping.
462 config CAVIUM_ERRATUM_23154
463 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
466 The gicv3 of ThunderX requires a modified version for
467 reading the IAR status to ensure data synchronization
468 (access to icc_iar1_el1 is not sync'ed before and after).
472 config CAVIUM_ERRATUM_27456
473 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
476 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
477 instructions may cause the icache to become corrupted if it
478 contains data for a non-current ASID. The fix is to
479 invalidate the icache when changing the mm context.
483 config QCOM_FALKOR_ERRATUM_1003
484 bool "Falkor E1003: Incorrect translation due to ASID change"
486 select ARM64_PAN if ARM64_SW_TTBR0_PAN
488 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
489 and BADDR are changed together in TTBRx_EL1. The workaround for this
490 issue is to use a reserved ASID in cpu_do_switch_mm() before
491 switching to the new ASID. Saying Y here selects ARM64_PAN if
492 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
493 maintaining the E1003 workaround in the software PAN emulation code
494 would be an unnecessary complication. The affected Falkor v1 CPU
495 implements ARMv8.1 hardware PAN support and using hardware PAN
496 support versus software PAN emulation is mutually exclusive at
501 config QCOM_FALKOR_ERRATUM_1009
502 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
505 On Falkor v1, the CPU may prematurely complete a DSB following a
506 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
507 one more time to fix the issue.
516 default ARM64_4K_PAGES
518 Page size (translation granule) configuration.
520 config ARM64_4K_PAGES
523 This feature enables 4KB pages support.
525 config ARM64_16K_PAGES
528 The system will use 16KB pages support. AArch32 emulation
529 requires applications compiled with 16K (or a multiple of 16K)
532 config ARM64_64K_PAGES
535 This feature enables 64KB pages support (4KB by default)
536 allowing only two levels of page tables and faster TLB
537 look-up. AArch32 emulation requires applications compiled
538 with 64K aligned segments.
543 prompt "Virtual address space size"
544 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
545 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
546 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
548 Allows choosing one of multiple possible virtual address
549 space sizes. The level of translation table is determined by
550 a combination of page size and virtual address space size.
552 config ARM64_VA_BITS_36
553 bool "36-bit" if EXPERT
554 depends on ARM64_16K_PAGES
556 config ARM64_VA_BITS_39
558 depends on ARM64_4K_PAGES
560 config ARM64_VA_BITS_42
562 depends on ARM64_64K_PAGES
564 config ARM64_VA_BITS_47
566 depends on ARM64_16K_PAGES
568 config ARM64_VA_BITS_48
575 default 36 if ARM64_VA_BITS_36
576 default 39 if ARM64_VA_BITS_39
577 default 42 if ARM64_VA_BITS_42
578 default 47 if ARM64_VA_BITS_47
579 default 48 if ARM64_VA_BITS_48
581 config CPU_BIG_ENDIAN
582 bool "Build big-endian kernel"
584 Say Y if you plan on running a kernel in big-endian mode.
587 bool "Multi-core scheduler support"
589 Multi-core scheduler support improves the CPU scheduler's decision
590 making when dealing with multi-core CPU chips at a cost of slightly
591 increased overhead in some places. If unsure say N here.
594 bool "SMT scheduler support"
596 Improves the CPU scheduler's decision making when dealing with
597 MultiThreading at a cost of slightly increased overhead in some
598 places. If unsure say N here.
601 int "Maximum number of CPUs (2-4096)"
603 # These have to remain sorted largest to smallest
607 bool "Support for hot-pluggable CPUs"
608 select GENERIC_IRQ_MIGRATION
610 Say Y here to experiment with turning CPUs off and on. CPUs
611 can be controlled through /sys/devices/system/cpu.
613 # Common NUMA Features
615 bool "Numa Memory Allocation and Scheduler Support"
616 select ACPI_NUMA if ACPI
619 Enable NUMA (Non Uniform Memory Access) support.
621 The kernel will try to allocate memory used by a CPU on the
622 local memory of the CPU and add some more
623 NUMA awareness to the kernel.
626 int "Maximum NUMA Nodes (as a power of 2)"
629 depends on NEED_MULTIPLE_NODES
631 Specify the maximum number of NUMA Nodes available on the target
632 system. Increases memory reserved to accommodate various tables.
634 config USE_PERCPU_NUMA_NODE_ID
638 config HAVE_SETUP_PER_CPU_AREA
642 config NEED_PER_CPU_EMBED_FIRST_CHUNK
650 source kernel/Kconfig.preempt
651 source kernel/Kconfig.hz
653 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
656 config ARCH_HAS_HOLES_MEMORYMODEL
657 def_bool y if SPARSEMEM
659 config ARCH_SPARSEMEM_ENABLE
661 select SPARSEMEM_VMEMMAP_ENABLE
663 config ARCH_SPARSEMEM_DEFAULT
664 def_bool ARCH_SPARSEMEM_ENABLE
666 config ARCH_SELECT_MEMORY_MODEL
667 def_bool ARCH_SPARSEMEM_ENABLE
669 config HAVE_ARCH_PFN_VALID
670 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
672 config HW_PERF_EVENTS
676 config SYS_SUPPORTS_HUGETLBFS
679 config ARCH_WANT_HUGE_PMD_SHARE
680 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
682 config ARCH_HAS_CACHE_LINE_SIZE
688 bool "Enable seccomp to safely compute untrusted bytecode"
690 This kernel feature is useful for number crunching applications
691 that may need to compute untrusted bytecode during their
692 execution. By using pipes or other transports made available to
693 the process as file descriptors supporting the read/write
694 syscalls, it's possible to isolate those applications in
695 their own address space using seccomp. Once seccomp is
696 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
697 and the task is only allowed to execute a few safe syscalls
698 defined by each seccomp mode.
701 bool "Enable paravirtualization code"
703 This changes the kernel so it can modify itself when it is run
704 under a hypervisor, potentially improving performance significantly
705 over full virtualization.
707 config PARAVIRT_TIME_ACCOUNTING
708 bool "Paravirtual steal time accounting"
712 Select this option to enable fine granularity task steal time
713 accounting. Time spent executing other tasks in parallel with
714 the current vCPU is discounted from the vCPU power. To account for
715 that, there can be a small performance impact.
717 If in doubt, say N here.
720 depends on PM_SLEEP_SMP
722 bool "kexec system call"
724 kexec is a system call that implements the ability to shutdown your
725 current kernel, and to start another kernel. It is like a reboot
726 but it is independent of the system firmware. And like a reboot
727 you can start any kernel with it, not just Linux.
734 bool "Xen guest support on ARM64"
735 depends on ARM64 && OF
739 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
741 config FORCE_MAX_ZONEORDER
743 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
744 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
747 The kernel memory allocator divides physically contiguous memory
748 blocks into "zones", where each zone is a power of two number of
749 pages. This option selects the largest power of two that the kernel
750 keeps in the memory allocator. If you need to allocate very large
751 blocks of physically contiguous memory, then you may need to
754 This config option is actually maximum order plus one. For example,
755 a value of 11 means that the largest free memory block is 2^10 pages.
757 We make sure that we can allocate upto a HugePage size for each configuration.
759 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
761 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
762 4M allocations matching the default size used by generic code.
764 menuconfig ARMV8_DEPRECATED
765 bool "Emulate deprecated/obsolete ARMv8 instructions"
768 Legacy software support may require certain instructions
769 that have been deprecated or obsoleted in the architecture.
771 Enable this config to enable selective emulation of these
779 bool "Emulate SWP/SWPB instructions"
781 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
782 they are always undefined. Say Y here to enable software
783 emulation of these instructions for userspace using LDXR/STXR.
785 In some older versions of glibc [<=2.8] SWP is used during futex
786 trylock() operations with the assumption that the code will not
787 be preempted. This invalid assumption may be more likely to fail
788 with SWP emulation enabled, leading to deadlock of the user
791 NOTE: when accessing uncached shared regions, LDXR/STXR rely
792 on an external transaction monitoring block called a global
793 monitor to maintain update atomicity. If your system does not
794 implement a global monitor, this option can cause programs that
795 perform SWP operations to uncached memory to deadlock.
799 config CP15_BARRIER_EMULATION
800 bool "Emulate CP15 Barrier instructions"
802 The CP15 barrier instructions - CP15ISB, CP15DSB, and
803 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
804 strongly recommended to use the ISB, DSB, and DMB
805 instructions instead.
807 Say Y here to enable software emulation of these
808 instructions for AArch32 userspace code. When this option is
809 enabled, CP15 barrier usage is traced which can help
810 identify software that needs updating.
814 config SETEND_EMULATION
815 bool "Emulate SETEND instruction"
817 The SETEND instruction alters the data-endianness of the
818 AArch32 EL0, and is deprecated in ARMv8.
820 Say Y here to enable software emulation of the instruction
821 for AArch32 userspace code.
823 Note: All the cpus on the system must have mixed endian support at EL0
824 for this feature to be enabled. If a new CPU - which doesn't support mixed
825 endian - is hotplugged in after this feature has been enabled, there could
826 be unexpected results in the applications.
831 config ARM64_SW_TTBR0_PAN
832 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
834 Enabling this option prevents the kernel from accessing
835 user-space memory directly by pointing TTBR0_EL1 to a reserved
836 zeroed area and reserved ASID. The user access routines
837 restore the valid TTBR0_EL1 temporarily.
839 menu "ARMv8.1 architectural features"
841 config ARM64_HW_AFDBM
842 bool "Support for hardware updates of the Access and Dirty page flags"
845 The ARMv8.1 architecture extensions introduce support for
846 hardware updates of the access and dirty information in page
847 table entries. When enabled in TCR_EL1 (HA and HD bits) on
848 capable processors, accesses to pages with PTE_AF cleared will
849 set this bit instead of raising an access flag fault.
850 Similarly, writes to read-only pages with the DBM bit set will
851 clear the read-only bit (AP[2]) instead of raising a
854 Kernels built with this configuration option enabled continue
855 to work on pre-ARMv8.1 hardware and the performance impact is
856 minimal. If unsure, say Y.
859 bool "Enable support for Privileged Access Never (PAN)"
862 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
863 prevents the kernel or hypervisor from accessing user-space (EL0)
866 Choosing this option will cause any unprotected (not using
867 copy_to_user et al) memory access to fail with a permission fault.
869 The feature is detected at runtime, and will remain as a 'nop'
870 instruction if the cpu does not implement the feature.
872 config ARM64_LSE_ATOMICS
873 bool "Atomic instructions"
875 As part of the Large System Extensions, ARMv8.1 introduces new
876 atomic instructions that are designed specifically to scale in
879 Say Y here to make use of these instructions for the in-kernel
880 atomic routines. This incurs a small overhead on CPUs that do
881 not support these instructions and requires the kernel to be
882 built with binutils >= 2.25.
885 bool "Enable support for Virtualization Host Extensions (VHE)"
888 Virtualization Host Extensions (VHE) allow the kernel to run
889 directly at EL2 (instead of EL1) on processors that support
890 it. This leads to better performance for KVM, as they reduce
891 the cost of the world switch.
893 Selecting this option allows the VHE feature to be detected
894 at runtime, and does not affect processors that do not
895 implement this feature.
899 menu "ARMv8.2 architectural features"
902 bool "Enable support for User Access Override (UAO)"
905 User Access Override (UAO; part of the ARMv8.2 Extensions)
906 causes the 'unprivileged' variant of the load/store instructions to
907 be overriden to be privileged.
909 This option changes get_user() and friends to use the 'unprivileged'
910 variant of the load/store instructions. This ensures that user-space
911 really did have access to the supplied memory. When addr_limit is
912 set to kernel memory the UAO bit will be set, allowing privileged
913 access to kernel memory.
915 Choosing this option will cause copy_to_user() et al to use user-space
918 The feature is detected at runtime, the kernel will use the
919 regular load/store instructions if the cpu does not implement the
924 config ARM64_MODULE_CMODEL_LARGE
927 config ARM64_MODULE_PLTS
929 select ARM64_MODULE_CMODEL_LARGE
930 select HAVE_MOD_ARCH_SPECIFIC
935 This builds the kernel as a Position Independent Executable (PIE),
936 which retains all relocation metadata required to relocate the
937 kernel binary at runtime to a different virtual address than the
938 address it was linked at.
939 Since AArch64 uses the RELA relocation format, this requires a
940 relocation pass at runtime even if the kernel is loaded at the
941 same address it was linked at.
943 config RANDOMIZE_BASE
944 bool "Randomize the address of the kernel image"
945 select ARM64_MODULE_PLTS if MODULES
948 Randomizes the virtual address at which the kernel image is
949 loaded, as a security feature that deters exploit attempts
950 relying on knowledge of the location of kernel internals.
952 It is the bootloader's job to provide entropy, by passing a
953 random u64 value in /chosen/kaslr-seed at kernel entry.
955 When booting via the UEFI stub, it will invoke the firmware's
956 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
957 to the kernel proper. In addition, it will randomise the physical
958 location of the kernel Image as well.
962 config RANDOMIZE_MODULE_REGION_FULL
963 bool "Randomize the module region independently from the core kernel"
964 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
967 Randomizes the location of the module region without considering the
968 location of the core kernel. This way, it is impossible for modules
969 to leak information about the location of core kernel data structures
970 but it does imply that function calls between modules and the core
971 kernel will need to be resolved via veneers in the module PLT.
973 When this option is not set, the module region will be randomized over
974 a limited range that contains the [_stext, _etext] interval of the
975 core kernel, so branch relocations are always in range.
981 config ARM64_ACPI_PARKING_PROTOCOL
982 bool "Enable support for the ARM64 ACPI parking protocol"
985 Enable support for the ARM64 ACPI parking protocol. If disabled
986 the kernel will not allow booting through the ARM64 ACPI parking
987 protocol even if the corresponding data is present in the ACPI
991 string "Default kernel command string"
994 Provide a set of default command-line options at build time by
995 entering them here. As a minimum, you should specify the the
996 root device (e.g. root=/dev/nfs).
999 bool "Always use the default kernel command string"
1001 Always use the default kernel command string, even if the boot
1002 loader passes other arguments to the kernel.
1003 This is useful if you cannot or don't want to change the
1004 command-line options your boot loader passes to the kernel.
1010 bool "UEFI runtime support"
1011 depends on OF && !CPU_BIG_ENDIAN
1014 select EFI_PARAMS_FROM_FDT
1015 select EFI_RUNTIME_WRAPPERS
1020 This option provides support for runtime services provided
1021 by UEFI firmware (such as non-volatile variables, realtime
1022 clock, and platform reset). A UEFI stub is also provided to
1023 allow the kernel to be booted as an EFI application. This
1024 is only useful on systems that have UEFI firmware.
1027 bool "Enable support for SMBIOS (DMI) tables"
1031 This enables SMBIOS/DMI feature for systems.
1033 This option is only useful on systems that have UEFI firmware.
1034 However, even with this option, the resultant kernel should
1035 continue to boot on existing non-UEFI platforms.
1039 menu "Userspace binary formats"
1041 source "fs/Kconfig.binfmt"
1044 bool "Kernel support for 32-bit EL0"
1045 depends on ARM64_4K_PAGES || EXPERT
1046 select COMPAT_BINFMT_ELF if BINFMT_ELF
1048 select OLD_SIGSUSPEND3
1049 select COMPAT_OLD_SIGACTION
1051 This option enables support for a 32-bit EL0 running under a 64-bit
1052 kernel at EL1. AArch32-specific components such as system calls,
1053 the user helper functions, VFP support and the ptrace interface are
1054 handled appropriately by the kernel.
1056 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1057 that you will only be able to execute AArch32 binaries that were compiled
1058 with page size aligned segments.
1060 If you want to execute 32-bit userspace applications, say Y.
1062 config SYSVIPC_COMPAT
1064 depends on COMPAT && SYSVIPC
1068 menu "Power management options"
1070 source "kernel/power/Kconfig"
1072 config ARCH_HIBERNATION_POSSIBLE
1076 config ARCH_HIBERNATION_HEADER
1078 depends on HIBERNATION
1080 config ARCH_SUSPEND_POSSIBLE
1085 menu "CPU Power Management"
1087 source "drivers/cpuidle/Kconfig"
1089 source "drivers/cpufreq/Kconfig"
1093 source "net/Kconfig"
1095 source "drivers/Kconfig"
1097 source "drivers/firmware/Kconfig"
1099 source "drivers/acpi/Kconfig"
1103 source "arch/arm64/kvm/Kconfig"
1105 source "arch/arm64/Kconfig.debug"
1107 source "security/Kconfig"
1109 source "crypto/Kconfig"
1111 source "arch/arm64/crypto/Kconfig"
1114 source "lib/Kconfig"