3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
15 select ARCH_HAS_ELF_RANDOMIZE
16 select ARCH_HAS_FAST_MULTIPLIER
17 select ARCH_HAS_FORTIFY_SOURCE
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
21 select ARCH_HAS_MEMBARRIER_SYNC_CORE
22 select ARCH_HAS_PTE_SPECIAL
23 select ARCH_HAS_SET_MEMORY
24 select ARCH_HAS_SG_CHAIN
25 select ARCH_HAS_STRICT_KERNEL_RWX
26 select ARCH_HAS_STRICT_MODULE_RWX
27 select ARCH_HAS_SYSCALL_WRAPPER
28 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
29 select ARCH_HAVE_NMI_SAFE_CMPXCHG
30 select ARCH_INLINE_READ_LOCK if !PREEMPT
31 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
32 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
33 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
34 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
35 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
36 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
37 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
38 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
39 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
40 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
42 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
43 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
44 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
46 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
47 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
48 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
49 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
50 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
51 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
52 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
53 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
54 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
56 select ARCH_USE_CMPXCHG_LOCKREF
57 select ARCH_USE_QUEUED_RWLOCKS
58 select ARCH_USE_QUEUED_SPINLOCKS
59 select ARCH_SUPPORTS_MEMORY_FAILURE
60 select ARCH_SUPPORTS_ATOMIC_RMW
61 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
62 select ARCH_SUPPORTS_NUMA_BALANCING
63 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
64 select ARCH_WANT_FRAME_POINTERS
65 select ARCH_HAS_UBSAN_SANITIZE_ALL
69 select AUDIT_ARCH_COMPAT_GENERIC
70 select ARM_GIC_V2M if PCI
72 select ARM_GIC_V3_ITS if PCI
74 select BUILDTIME_EXTABLE_SORT
75 select CLONE_BACKWARDS
77 select CPU_PM if (SUSPEND || CPU_IDLE)
79 select DCACHE_WORD_ACCESS
83 select GENERIC_ALLOCATOR
84 select GENERIC_ARCH_TOPOLOGY
85 select GENERIC_CLOCKEVENTS
86 select GENERIC_CLOCKEVENTS_BROADCAST
87 select GENERIC_CPU_AUTOPROBE
88 select GENERIC_EARLY_IOREMAP
89 select GENERIC_IDLE_POLL_SETUP
90 select GENERIC_IRQ_MULTI_HANDLER
91 select GENERIC_IRQ_PROBE
92 select GENERIC_IRQ_SHOW
93 select GENERIC_IRQ_SHOW_LEVEL
94 select GENERIC_PCI_IOMAP
95 select GENERIC_SCHED_CLOCK
96 select GENERIC_SMP_IDLE_THREAD
97 select GENERIC_STRNCPY_FROM_USER
98 select GENERIC_STRNLEN_USER
99 select GENERIC_TIME_VSYSCALL
100 select HANDLE_DOMAIN_IRQ
101 select HARDIRQS_SW_RESEND
102 select HAVE_ACPI_APEI if (ACPI && EFI)
103 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
104 select HAVE_ARCH_AUDITSYSCALL
105 select HAVE_ARCH_BITREVERSE
106 select HAVE_ARCH_HUGE_VMAP
107 select HAVE_ARCH_JUMP_LABEL
108 select HAVE_ARCH_JUMP_LABEL_RELATIVE
109 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
110 select HAVE_ARCH_KGDB
111 select HAVE_ARCH_MMAP_RND_BITS
112 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
113 select HAVE_ARCH_PREL32_RELOCATIONS
114 select HAVE_ARCH_SECCOMP_FILTER
115 select HAVE_ARCH_STACKLEAK
116 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
117 select HAVE_ARCH_TRACEHOOK
118 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
119 select HAVE_ARCH_VMAP_STACK
120 select HAVE_ARM_SMCCC
122 select HAVE_C_RECORDMCOUNT
123 select HAVE_CMPXCHG_DOUBLE
124 select HAVE_CMPXCHG_LOCAL
125 select HAVE_CONTEXT_TRACKING
126 select HAVE_DEBUG_BUGVERBOSE
127 select HAVE_DEBUG_KMEMLEAK
128 select HAVE_DMA_CONTIGUOUS
129 select HAVE_DYNAMIC_FTRACE
130 select HAVE_EFFICIENT_UNALIGNED_ACCESS
131 select HAVE_FTRACE_MCOUNT_RECORD
132 select HAVE_FUNCTION_TRACER
133 select HAVE_FUNCTION_GRAPH_TRACER
134 select HAVE_GCC_PLUGINS
135 select HAVE_GENERIC_DMA_COHERENT
136 select HAVE_HW_BREAKPOINT if PERF_EVENTS
137 select HAVE_IRQ_TIME_ACCOUNTING
139 select HAVE_MEMBLOCK_NODE_MAP if NUMA
141 select HAVE_PATA_PLATFORM
142 select HAVE_PERF_EVENTS
143 select HAVE_PERF_REGS
144 select HAVE_PERF_USER_STACK_DUMP
145 select HAVE_REGS_AND_STACK_ACCESS_API
146 select HAVE_RCU_TABLE_FREE
147 select HAVE_RCU_TABLE_INVALIDATE
149 select HAVE_STACKPROTECTOR
150 select HAVE_SYSCALL_TRACEPOINTS
152 select HAVE_KRETPROBES
153 select IOMMU_DMA if IOMMU_SUPPORT
155 select IRQ_FORCED_THREADING
156 select MODULES_USE_ELF_RELA
157 select MULTI_IRQ_HANDLER
158 select NEED_DMA_MAP_STATE
159 select NEED_SG_DMA_LENGTH
162 select OF_EARLY_FLATTREE
163 select OF_RESERVED_MEM
164 select PCI_ECAM if ACPI
170 select SYSCTL_EXCEPTION_TRACE
171 select THREAD_INFO_IN_TASK
173 ARM 64-bit (AArch64) Linux support.
181 config ARM64_PAGE_SHIFT
183 default 16 if ARM64_64K_PAGES
184 default 14 if ARM64_16K_PAGES
187 config ARM64_CONT_SHIFT
189 default 5 if ARM64_64K_PAGES
190 default 7 if ARM64_16K_PAGES
193 config ARCH_MMAP_RND_BITS_MIN
194 default 14 if ARM64_64K_PAGES
195 default 16 if ARM64_16K_PAGES
198 # max bits determined by the following formula:
199 # VA_BITS - PAGE_SHIFT - 3
200 config ARCH_MMAP_RND_BITS_MAX
201 default 19 if ARM64_VA_BITS=36
202 default 24 if ARM64_VA_BITS=39
203 default 27 if ARM64_VA_BITS=42
204 default 30 if ARM64_VA_BITS=47
205 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
206 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
207 default 33 if ARM64_VA_BITS=48
208 default 14 if ARM64_64K_PAGES
209 default 16 if ARM64_16K_PAGES
212 config ARCH_MMAP_RND_COMPAT_BITS_MIN
213 default 7 if ARM64_64K_PAGES
214 default 9 if ARM64_16K_PAGES
217 config ARCH_MMAP_RND_COMPAT_BITS_MAX
223 config STACKTRACE_SUPPORT
226 config ILLEGAL_POINTER_VALUE
228 default 0xdead000000000000
230 config LOCKDEP_SUPPORT
233 config TRACE_IRQFLAGS_SUPPORT
236 config RWSEM_XCHGADD_ALGORITHM
243 config GENERIC_BUG_RELATIVE_POINTERS
245 depends on GENERIC_BUG
247 config GENERIC_HWEIGHT
253 config GENERIC_CALIBRATE_DELAY
259 config HAVE_GENERIC_GUP
265 config KERNEL_MODE_NEON
268 config FIX_EARLYCON_MEM
271 config PGTABLE_LEVELS
273 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
274 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
275 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
276 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
277 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
278 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
280 config ARCH_SUPPORTS_UPROBES
283 config ARCH_PROC_KCORE_TEXT
286 source "arch/arm64/Kconfig.platforms"
293 This feature enables support for PCI bus system. If you say Y
294 here, the kernel will include drivers and infrastructure code
295 to support PCI bus devices.
300 config PCI_DOMAINS_GENERIC
306 source "drivers/pci/Kconfig"
310 menu "Kernel Features"
312 menu "ARM errata workarounds via the alternatives framework"
314 config ARM64_ERRATUM_826319
315 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
318 This option adds an alternative code sequence to work around ARM
319 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
320 AXI master interface and an L2 cache.
322 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
323 and is unable to accept a certain write via this interface, it will
324 not progress on read data presented on the read data channel and the
327 The workaround promotes data cache clean instructions to
328 data cache clean-and-invalidate.
329 Please note that this does not necessarily enable the workaround,
330 as it depends on the alternative framework, which will only patch
331 the kernel if an affected CPU is detected.
335 config ARM64_ERRATUM_827319
336 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
339 This option adds an alternative code sequence to work around ARM
340 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
341 master interface and an L2 cache.
343 Under certain conditions this erratum can cause a clean line eviction
344 to occur at the same time as another transaction to the same address
345 on the AMBA 5 CHI interface, which can cause data corruption if the
346 interconnect reorders the two transactions.
348 The workaround promotes data cache clean instructions to
349 data cache clean-and-invalidate.
350 Please note that this does not necessarily enable the workaround,
351 as it depends on the alternative framework, which will only patch
352 the kernel if an affected CPU is detected.
356 config ARM64_ERRATUM_824069
357 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
360 This option adds an alternative code sequence to work around ARM
361 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
362 to a coherent interconnect.
364 If a Cortex-A53 processor is executing a store or prefetch for
365 write instruction at the same time as a processor in another
366 cluster is executing a cache maintenance operation to the same
367 address, then this erratum might cause a clean cache line to be
368 incorrectly marked as dirty.
370 The workaround promotes data cache clean instructions to
371 data cache clean-and-invalidate.
372 Please note that this option does not necessarily enable the
373 workaround, as it depends on the alternative framework, which will
374 only patch the kernel if an affected CPU is detected.
378 config ARM64_ERRATUM_819472
379 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
382 This option adds an alternative code sequence to work around ARM
383 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
384 present when it is connected to a coherent interconnect.
386 If the processor is executing a load and store exclusive sequence at
387 the same time as a processor in another cluster is executing a cache
388 maintenance operation to the same address, then this erratum might
389 cause data corruption.
391 The workaround promotes data cache clean instructions to
392 data cache clean-and-invalidate.
393 Please note that this does not necessarily enable the workaround,
394 as it depends on the alternative framework, which will only patch
395 the kernel if an affected CPU is detected.
399 config ARM64_ERRATUM_832075
400 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
403 This option adds an alternative code sequence to work around ARM
404 erratum 832075 on Cortex-A57 parts up to r1p2.
406 Affected Cortex-A57 parts might deadlock when exclusive load/store
407 instructions to Write-Back memory are mixed with Device loads.
409 The workaround is to promote device loads to use Load-Acquire
411 Please note that this does not necessarily enable the workaround,
412 as it depends on the alternative framework, which will only patch
413 the kernel if an affected CPU is detected.
417 config ARM64_ERRATUM_834220
418 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
422 This option adds an alternative code sequence to work around ARM
423 erratum 834220 on Cortex-A57 parts up to r1p2.
425 Affected Cortex-A57 parts might report a Stage 2 translation
426 fault as the result of a Stage 1 fault for load crossing a
427 page boundary when there is a permission or device memory
428 alignment fault at Stage 1 and a translation fault at Stage 2.
430 The workaround is to verify that the Stage 1 translation
431 doesn't generate a fault before handling the Stage 2 fault.
432 Please note that this does not necessarily enable the workaround,
433 as it depends on the alternative framework, which will only patch
434 the kernel if an affected CPU is detected.
438 config ARM64_ERRATUM_845719
439 bool "Cortex-A53: 845719: a load might read incorrect data"
443 This option adds an alternative code sequence to work around ARM
444 erratum 845719 on Cortex-A53 parts up to r0p4.
446 When running a compat (AArch32) userspace on an affected Cortex-A53
447 part, a load at EL0 from a virtual address that matches the bottom 32
448 bits of the virtual address used by a recent load at (AArch64) EL1
449 might return incorrect data.
451 The workaround is to write the contextidr_el1 register on exception
452 return to a 32-bit task.
453 Please note that this does not necessarily enable the workaround,
454 as it depends on the alternative framework, which will only patch
455 the kernel if an affected CPU is detected.
459 config ARM64_ERRATUM_843419
460 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
462 select ARM64_MODULE_PLTS if MODULES
464 This option links the kernel with '--fix-cortex-a53-843419' and
465 enables PLT support to replace certain ADRP instructions, which can
466 cause subsequent memory accesses to use an incorrect address on
467 Cortex-A53 parts up to r0p4.
471 config ARM64_ERRATUM_1024718
472 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
475 This option adds work around for Arm Cortex-A55 Erratum 1024718.
477 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
478 update of the hardware dirty bit when the DBM/AP bits are updated
479 without a break-before-make. The work around is to disable the usage
480 of hardware DBM locally on the affected cores. CPUs not affected by
481 erratum will continue to use the feature.
485 config ARM64_ERRATUM_1188873
486 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
488 select ARM_ARCH_TIMER_OOL_WORKAROUND
490 This option adds work arounds for ARM Cortex-A76 erratum 1188873
492 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
493 register corruption when accessing the timer registers from
498 config CAVIUM_ERRATUM_22375
499 bool "Cavium erratum 22375, 24313"
502 Enable workaround for erratum 22375, 24313.
504 This implements two gicv3-its errata workarounds for ThunderX. Both
505 with small impact affecting only ITS table allocation.
507 erratum 22375: only alloc 8MB table size
508 erratum 24313: ignore memory access type
510 The fixes are in ITS initialization and basically ignore memory access
511 type and table size provided by the TYPER and BASER registers.
515 config CAVIUM_ERRATUM_23144
516 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
520 ITS SYNC command hang for cross node io and collections/cpu mapping.
524 config CAVIUM_ERRATUM_23154
525 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
528 The gicv3 of ThunderX requires a modified version for
529 reading the IAR status to ensure data synchronization
530 (access to icc_iar1_el1 is not sync'ed before and after).
534 config CAVIUM_ERRATUM_27456
535 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
538 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
539 instructions may cause the icache to become corrupted if it
540 contains data for a non-current ASID. The fix is to
541 invalidate the icache when changing the mm context.
545 config CAVIUM_ERRATUM_30115
546 bool "Cavium erratum 30115: Guest may disable interrupts in host"
549 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
550 1.2, and T83 Pass 1.0, KVM guest execution may disable
551 interrupts in host. Trapping both GICv3 group-0 and group-1
552 accesses sidesteps the issue.
556 config QCOM_FALKOR_ERRATUM_1003
557 bool "Falkor E1003: Incorrect translation due to ASID change"
560 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
561 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
562 in TTBR1_EL1, this situation only occurs in the entry trampoline and
563 then only for entries in the walk cache, since the leaf translation
564 is unchanged. Work around the erratum by invalidating the walk cache
565 entries for the trampoline before entering the kernel proper.
567 config QCOM_FALKOR_ERRATUM_1009
568 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
571 On Falkor v1, the CPU may prematurely complete a DSB following a
572 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
573 one more time to fix the issue.
577 config QCOM_QDF2400_ERRATUM_0065
578 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
581 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
582 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
583 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
587 config SOCIONEXT_SYNQUACER_PREITS
588 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
591 Socionext Synquacer SoCs implement a separate h/w block to generate
592 MSI doorbell writes with non-zero values for the device ID.
596 config HISILICON_ERRATUM_161600802
597 bool "Hip07 161600802: Erroneous redistributor VLPI base"
600 The HiSilicon Hip07 SoC usees the wrong redistributor base
601 when issued ITS commands such as VMOVP and VMAPP, and requires
602 a 128kB offset to be applied to the target address in this commands.
606 config QCOM_FALKOR_ERRATUM_E1041
607 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
610 Falkor CPU may speculatively fetch instructions from an improper
611 memory location when MMU translation is changed from SCTLR_ELn[M]=1
612 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
621 default ARM64_4K_PAGES
623 Page size (translation granule) configuration.
625 config ARM64_4K_PAGES
628 This feature enables 4KB pages support.
630 config ARM64_16K_PAGES
633 The system will use 16KB pages support. AArch32 emulation
634 requires applications compiled with 16K (or a multiple of 16K)
637 config ARM64_64K_PAGES
640 This feature enables 64KB pages support (4KB by default)
641 allowing only two levels of page tables and faster TLB
642 look-up. AArch32 emulation requires applications compiled
643 with 64K aligned segments.
648 prompt "Virtual address space size"
649 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
650 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
651 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
653 Allows choosing one of multiple possible virtual address
654 space sizes. The level of translation table is determined by
655 a combination of page size and virtual address space size.
657 config ARM64_VA_BITS_36
658 bool "36-bit" if EXPERT
659 depends on ARM64_16K_PAGES
661 config ARM64_VA_BITS_39
663 depends on ARM64_4K_PAGES
665 config ARM64_VA_BITS_42
667 depends on ARM64_64K_PAGES
669 config ARM64_VA_BITS_47
671 depends on ARM64_16K_PAGES
673 config ARM64_VA_BITS_48
680 default 36 if ARM64_VA_BITS_36
681 default 39 if ARM64_VA_BITS_39
682 default 42 if ARM64_VA_BITS_42
683 default 47 if ARM64_VA_BITS_47
684 default 48 if ARM64_VA_BITS_48
687 prompt "Physical address space size"
688 default ARM64_PA_BITS_48
690 Choose the maximum physical address range that the kernel will
693 config ARM64_PA_BITS_48
696 config ARM64_PA_BITS_52
697 bool "52-bit (ARMv8.2)"
698 depends on ARM64_64K_PAGES
699 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
701 Enable support for a 52-bit physical address space, introduced as
702 part of the ARMv8.2-LPA extension.
704 With this enabled, the kernel will also continue to work on CPUs that
705 do not support ARMv8.2-LPA, but with some added memory overhead (and
706 minor performance overhead).
712 default 48 if ARM64_PA_BITS_48
713 default 52 if ARM64_PA_BITS_52
715 config CPU_BIG_ENDIAN
716 bool "Build big-endian kernel"
718 Say Y if you plan on running a kernel in big-endian mode.
721 bool "Multi-core scheduler support"
723 Multi-core scheduler support improves the CPU scheduler's decision
724 making when dealing with multi-core CPU chips at a cost of slightly
725 increased overhead in some places. If unsure say N here.
728 bool "SMT scheduler support"
730 Improves the CPU scheduler's decision making when dealing with
731 MultiThreading at a cost of slightly increased overhead in some
732 places. If unsure say N here.
735 int "Maximum number of CPUs (2-4096)"
737 # These have to remain sorted largest to smallest
741 bool "Support for hot-pluggable CPUs"
742 select GENERIC_IRQ_MIGRATION
744 Say Y here to experiment with turning CPUs off and on. CPUs
745 can be controlled through /sys/devices/system/cpu.
747 # Common NUMA Features
749 bool "Numa Memory Allocation and Scheduler Support"
750 select ACPI_NUMA if ACPI
753 Enable NUMA (Non Uniform Memory Access) support.
755 The kernel will try to allocate memory used by a CPU on the
756 local memory of the CPU and add some more
757 NUMA awareness to the kernel.
760 int "Maximum NUMA Nodes (as a power of 2)"
763 depends on NEED_MULTIPLE_NODES
765 Specify the maximum number of NUMA Nodes available on the target
766 system. Increases memory reserved to accommodate various tables.
768 config USE_PERCPU_NUMA_NODE_ID
772 config HAVE_SETUP_PER_CPU_AREA
776 config NEED_PER_CPU_EMBED_FIRST_CHUNK
783 source kernel/Kconfig.hz
785 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
788 config ARCH_SPARSEMEM_ENABLE
790 select SPARSEMEM_VMEMMAP_ENABLE
792 config ARCH_SPARSEMEM_DEFAULT
793 def_bool ARCH_SPARSEMEM_ENABLE
795 config ARCH_SELECT_MEMORY_MODEL
796 def_bool ARCH_SPARSEMEM_ENABLE
798 config ARCH_FLATMEM_ENABLE
801 config HAVE_ARCH_PFN_VALID
804 config HW_PERF_EVENTS
808 config SYS_SUPPORTS_HUGETLBFS
811 config ARCH_WANT_HUGE_PMD_SHARE
812 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
814 config ARCH_HAS_CACHE_LINE_SIZE
818 bool "Enable seccomp to safely compute untrusted bytecode"
820 This kernel feature is useful for number crunching applications
821 that may need to compute untrusted bytecode during their
822 execution. By using pipes or other transports made available to
823 the process as file descriptors supporting the read/write
824 syscalls, it's possible to isolate those applications in
825 their own address space using seccomp. Once seccomp is
826 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
827 and the task is only allowed to execute a few safe syscalls
828 defined by each seccomp mode.
831 bool "Enable paravirtualization code"
833 This changes the kernel so it can modify itself when it is run
834 under a hypervisor, potentially improving performance significantly
835 over full virtualization.
837 config PARAVIRT_TIME_ACCOUNTING
838 bool "Paravirtual steal time accounting"
842 Select this option to enable fine granularity task steal time
843 accounting. Time spent executing other tasks in parallel with
844 the current vCPU is discounted from the vCPU power. To account for
845 that, there can be a small performance impact.
847 If in doubt, say N here.
850 depends on PM_SLEEP_SMP
852 bool "kexec system call"
854 kexec is a system call that implements the ability to shutdown your
855 current kernel, and to start another kernel. It is like a reboot
856 but it is independent of the system firmware. And like a reboot
857 you can start any kernel with it, not just Linux.
860 bool "Build kdump crash kernel"
862 Generate crash dump after being started by kexec. This should
863 be normally only set in special crash dump kernels which are
864 loaded in the main kernel with kexec-tools into a specially
865 reserved region and then later executed after a crash by
868 For more details see Documentation/kdump/kdump.txt
875 bool "Xen guest support on ARM64"
876 depends on ARM64 && OF
880 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
882 config FORCE_MAX_ZONEORDER
884 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
885 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
888 The kernel memory allocator divides physically contiguous memory
889 blocks into "zones", where each zone is a power of two number of
890 pages. This option selects the largest power of two that the kernel
891 keeps in the memory allocator. If you need to allocate very large
892 blocks of physically contiguous memory, then you may need to
895 This config option is actually maximum order plus one. For example,
896 a value of 11 means that the largest free memory block is 2^10 pages.
898 We make sure that we can allocate upto a HugePage size for each configuration.
900 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
902 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
903 4M allocations matching the default size used by generic code.
905 config UNMAP_KERNEL_AT_EL0
906 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
909 Speculation attacks against some high-performance processors can
910 be used to bypass MMU permission checks and leak kernel data to
911 userspace. This can be defended against by unmapping the kernel
912 when running in userspace, mapping it back in on exception entry
913 via a trampoline page in the vector table.
917 config HARDEN_BRANCH_PREDICTOR
918 bool "Harden the branch predictor against aliasing attacks" if EXPERT
921 Speculation attacks against some high-performance processors rely on
922 being able to manipulate the branch predictor for a victim context by
923 executing aliasing branches in the attacker context. Such attacks
924 can be partially mitigated against by clearing internal branch
925 predictor state and limiting the prediction logic in some situations.
927 This config option will take CPU-specific actions to harden the
928 branch predictor against aliasing attacks and may rely on specific
929 instruction sequences or control bits being set by the system
934 config HARDEN_EL2_VECTORS
935 bool "Harden EL2 vector mapping against system register leak" if EXPERT
938 Speculation attacks against some high-performance processors can
939 be used to leak privileged information such as the vector base
940 register, resulting in a potential defeat of the EL2 layout
943 This config option will map the vectors to a fixed location,
944 independent of the EL2 code mapping, so that revealing VBAR_EL2
945 to an attacker does not give away any extra information. This
946 only gets enabled on affected CPUs.
951 bool "Speculative Store Bypass Disable" if EXPERT
954 This enables mitigation of the bypassing of previous stores
955 by speculative loads.
959 menuconfig ARMV8_DEPRECATED
960 bool "Emulate deprecated/obsolete ARMv8 instructions"
964 Legacy software support may require certain instructions
965 that have been deprecated or obsoleted in the architecture.
967 Enable this config to enable selective emulation of these
975 bool "Emulate SWP/SWPB instructions"
977 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
978 they are always undefined. Say Y here to enable software
979 emulation of these instructions for userspace using LDXR/STXR.
981 In some older versions of glibc [<=2.8] SWP is used during futex
982 trylock() operations with the assumption that the code will not
983 be preempted. This invalid assumption may be more likely to fail
984 with SWP emulation enabled, leading to deadlock of the user
987 NOTE: when accessing uncached shared regions, LDXR/STXR rely
988 on an external transaction monitoring block called a global
989 monitor to maintain update atomicity. If your system does not
990 implement a global monitor, this option can cause programs that
991 perform SWP operations to uncached memory to deadlock.
995 config CP15_BARRIER_EMULATION
996 bool "Emulate CP15 Barrier instructions"
998 The CP15 barrier instructions - CP15ISB, CP15DSB, and
999 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1000 strongly recommended to use the ISB, DSB, and DMB
1001 instructions instead.
1003 Say Y here to enable software emulation of these
1004 instructions for AArch32 userspace code. When this option is
1005 enabled, CP15 barrier usage is traced which can help
1006 identify software that needs updating.
1010 config SETEND_EMULATION
1011 bool "Emulate SETEND instruction"
1013 The SETEND instruction alters the data-endianness of the
1014 AArch32 EL0, and is deprecated in ARMv8.
1016 Say Y here to enable software emulation of the instruction
1017 for AArch32 userspace code.
1019 Note: All the cpus on the system must have mixed endian support at EL0
1020 for this feature to be enabled. If a new CPU - which doesn't support mixed
1021 endian - is hotplugged in after this feature has been enabled, there could
1022 be unexpected results in the applications.
1027 config ARM64_SW_TTBR0_PAN
1028 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1030 Enabling this option prevents the kernel from accessing
1031 user-space memory directly by pointing TTBR0_EL1 to a reserved
1032 zeroed area and reserved ASID. The user access routines
1033 restore the valid TTBR0_EL1 temporarily.
1035 menu "ARMv8.1 architectural features"
1037 config ARM64_HW_AFDBM
1038 bool "Support for hardware updates of the Access and Dirty page flags"
1041 The ARMv8.1 architecture extensions introduce support for
1042 hardware updates of the access and dirty information in page
1043 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1044 capable processors, accesses to pages with PTE_AF cleared will
1045 set this bit instead of raising an access flag fault.
1046 Similarly, writes to read-only pages with the DBM bit set will
1047 clear the read-only bit (AP[2]) instead of raising a
1050 Kernels built with this configuration option enabled continue
1051 to work on pre-ARMv8.1 hardware and the performance impact is
1052 minimal. If unsure, say Y.
1055 bool "Enable support for Privileged Access Never (PAN)"
1058 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1059 prevents the kernel or hypervisor from accessing user-space (EL0)
1062 Choosing this option will cause any unprotected (not using
1063 copy_to_user et al) memory access to fail with a permission fault.
1065 The feature is detected at runtime, and will remain as a 'nop'
1066 instruction if the cpu does not implement the feature.
1068 config ARM64_LSE_ATOMICS
1069 bool "Atomic instructions"
1072 As part of the Large System Extensions, ARMv8.1 introduces new
1073 atomic instructions that are designed specifically to scale in
1076 Say Y here to make use of these instructions for the in-kernel
1077 atomic routines. This incurs a small overhead on CPUs that do
1078 not support these instructions and requires the kernel to be
1079 built with binutils >= 2.25 in order for the new instructions
1083 bool "Enable support for Virtualization Host Extensions (VHE)"
1086 Virtualization Host Extensions (VHE) allow the kernel to run
1087 directly at EL2 (instead of EL1) on processors that support
1088 it. This leads to better performance for KVM, as they reduce
1089 the cost of the world switch.
1091 Selecting this option allows the VHE feature to be detected
1092 at runtime, and does not affect processors that do not
1093 implement this feature.
1097 menu "ARMv8.2 architectural features"
1100 bool "Enable support for User Access Override (UAO)"
1103 User Access Override (UAO; part of the ARMv8.2 Extensions)
1104 causes the 'unprivileged' variant of the load/store instructions to
1105 be overridden to be privileged.
1107 This option changes get_user() and friends to use the 'unprivileged'
1108 variant of the load/store instructions. This ensures that user-space
1109 really did have access to the supplied memory. When addr_limit is
1110 set to kernel memory the UAO bit will be set, allowing privileged
1111 access to kernel memory.
1113 Choosing this option will cause copy_to_user() et al to use user-space
1116 The feature is detected at runtime, the kernel will use the
1117 regular load/store instructions if the cpu does not implement the
1121 bool "Enable support for persistent memory"
1122 select ARCH_HAS_PMEM_API
1123 select ARCH_HAS_UACCESS_FLUSHCACHE
1125 Say Y to enable support for the persistent memory API based on the
1126 ARMv8.2 DCPoP feature.
1128 The feature is detected at runtime, and the kernel will use DC CVAC
1129 operations if DC CVAP is not supported (following the behaviour of
1130 DC CVAP itself if the system does not define a point of persistence).
1132 config ARM64_RAS_EXTN
1133 bool "Enable support for RAS CPU Extensions"
1136 CPUs that support the Reliability, Availability and Serviceability
1137 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1138 errors, classify them and report them to software.
1140 On CPUs with these extensions system software can use additional
1141 barriers to determine if faults are pending and read the
1142 classification from a new set of registers.
1144 Selecting this feature will allow the kernel to use these barriers
1145 and access the new registers if the system supports the extension.
1146 Platform RAS features may additionally depend on firmware support.
1149 bool "Enable support for Common Not Private (CNP) translations"
1151 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1153 Common Not Private (CNP) allows translation table entries to
1154 be shared between different PEs in the same inner shareable
1155 domain, so the hardware can use this fact to optimise the
1156 caching of such entries in the TLB.
1158 Selecting this option allows the CNP feature to be detected
1159 at runtime, and does not affect PEs that do not implement
1165 bool "ARM Scalable Vector Extension support"
1167 depends on !KVM || ARM64_VHE
1169 The Scalable Vector Extension (SVE) is an extension to the AArch64
1170 execution state which complements and extends the SIMD functionality
1171 of the base architecture to support much larger vectors and to enable
1172 additional vectorisation opportunities.
1174 To enable use of this extension on CPUs that implement it, say Y.
1176 Note that for architectural reasons, firmware _must_ implement SVE
1177 support when running on SVE capable hardware. The required support
1180 * version 1.5 and later of the ARM Trusted Firmware
1181 * the AArch64 boot wrapper since commit 5e1261e08abf
1182 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1184 For other firmware implementations, consult the firmware documentation
1187 If you need the kernel to boot on SVE-capable hardware with broken
1188 firmware, you may need to say N here until you get your firmware
1189 fixed. Otherwise, you may experience firmware panics or lockups when
1190 booting the kernel. If unsure and you are not observing these
1191 symptoms, you should assume that it is safe to say Y.
1193 CPUs that support SVE are architecturally required to support the
1194 Virtualization Host Extensions (VHE), so the kernel makes no
1195 provision for supporting SVE alongside KVM without VHE enabled.
1196 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1197 KVM in the same kernel image.
1199 config ARM64_MODULE_PLTS
1201 select HAVE_MOD_ARCH_SPECIFIC
1206 This builds the kernel as a Position Independent Executable (PIE),
1207 which retains all relocation metadata required to relocate the
1208 kernel binary at runtime to a different virtual address than the
1209 address it was linked at.
1210 Since AArch64 uses the RELA relocation format, this requires a
1211 relocation pass at runtime even if the kernel is loaded at the
1212 same address it was linked at.
1214 config RANDOMIZE_BASE
1215 bool "Randomize the address of the kernel image"
1216 select ARM64_MODULE_PLTS if MODULES
1219 Randomizes the virtual address at which the kernel image is
1220 loaded, as a security feature that deters exploit attempts
1221 relying on knowledge of the location of kernel internals.
1223 It is the bootloader's job to provide entropy, by passing a
1224 random u64 value in /chosen/kaslr-seed at kernel entry.
1226 When booting via the UEFI stub, it will invoke the firmware's
1227 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1228 to the kernel proper. In addition, it will randomise the physical
1229 location of the kernel Image as well.
1233 config RANDOMIZE_MODULE_REGION_FULL
1234 bool "Randomize the module region over a 4 GB range"
1235 depends on RANDOMIZE_BASE
1238 Randomizes the location of the module region inside a 4 GB window
1239 covering the core kernel. This way, it is less likely for modules
1240 to leak information about the location of core kernel data structures
1241 but it does imply that function calls between modules and the core
1242 kernel will need to be resolved via veneers in the module PLT.
1244 When this option is not set, the module region will be randomized over
1245 a limited range that contains the [_stext, _etext] interval of the
1246 core kernel, so branch relocations are always in range.
1252 config ARM64_ACPI_PARKING_PROTOCOL
1253 bool "Enable support for the ARM64 ACPI parking protocol"
1256 Enable support for the ARM64 ACPI parking protocol. If disabled
1257 the kernel will not allow booting through the ARM64 ACPI parking
1258 protocol even if the corresponding data is present in the ACPI
1262 string "Default kernel command string"
1265 Provide a set of default command-line options at build time by
1266 entering them here. As a minimum, you should specify the the
1267 root device (e.g. root=/dev/nfs).
1269 config CMDLINE_FORCE
1270 bool "Always use the default kernel command string"
1272 Always use the default kernel command string, even if the boot
1273 loader passes other arguments to the kernel.
1274 This is useful if you cannot or don't want to change the
1275 command-line options your boot loader passes to the kernel.
1281 bool "UEFI runtime support"
1282 depends on OF && !CPU_BIG_ENDIAN
1283 depends on KERNEL_MODE_NEON
1284 select ARCH_SUPPORTS_ACPI
1287 select EFI_PARAMS_FROM_FDT
1288 select EFI_RUNTIME_WRAPPERS
1293 This option provides support for runtime services provided
1294 by UEFI firmware (such as non-volatile variables, realtime
1295 clock, and platform reset). A UEFI stub is also provided to
1296 allow the kernel to be booted as an EFI application. This
1297 is only useful on systems that have UEFI firmware.
1300 bool "Enable support for SMBIOS (DMI) tables"
1304 This enables SMBIOS/DMI feature for systems.
1306 This option is only useful on systems that have UEFI firmware.
1307 However, even with this option, the resultant kernel should
1308 continue to boot on existing non-UEFI platforms.
1313 bool "Kernel support for 32-bit EL0"
1314 depends on ARM64_4K_PAGES || EXPERT
1315 select COMPAT_BINFMT_ELF if BINFMT_ELF
1317 select OLD_SIGSUSPEND3
1318 select COMPAT_OLD_SIGACTION
1320 This option enables support for a 32-bit EL0 running under a 64-bit
1321 kernel at EL1. AArch32-specific components such as system calls,
1322 the user helper functions, VFP support and the ptrace interface are
1323 handled appropriately by the kernel.
1325 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1326 that you will only be able to execute AArch32 binaries that were compiled
1327 with page size aligned segments.
1329 If you want to execute 32-bit userspace applications, say Y.
1331 config SYSVIPC_COMPAT
1333 depends on COMPAT && SYSVIPC
1335 menu "Power management options"
1337 source "kernel/power/Kconfig"
1339 config ARCH_HIBERNATION_POSSIBLE
1343 config ARCH_HIBERNATION_HEADER
1345 depends on HIBERNATION
1347 config ARCH_SUSPEND_POSSIBLE
1352 menu "CPU Power Management"
1354 source "drivers/cpuidle/Kconfig"
1356 source "drivers/cpufreq/Kconfig"
1360 source "drivers/firmware/Kconfig"
1362 source "drivers/acpi/Kconfig"
1364 source "arch/arm64/kvm/Kconfig"
1367 source "arch/arm64/crypto/Kconfig"