1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_EXTRA_PHDRS
14 select ARCH_BINFMT_ELF_STATE
15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
17 select ARCH_ENABLE_MEMORY_HOTPLUG
18 select ARCH_ENABLE_MEMORY_HOTREMOVE
19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
21 select ARCH_HAS_CACHE_LINE_SIZE
22 select ARCH_HAS_CURRENT_STACK_POINTER
23 select ARCH_HAS_DEBUG_VIRTUAL
24 select ARCH_HAS_DEBUG_VM_PGTABLE
25 select ARCH_HAS_DMA_PREP_COHERENT
26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
27 select ARCH_HAS_FAST_MULTIPLIER
28 select ARCH_HAS_FORTIFY_SOURCE
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_HAS_GIGANTIC_PAGE
32 select ARCH_HAS_KEEPINITRD
33 select ARCH_HAS_MEMBARRIER_SYNC_CORE
34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
35 select ARCH_HAS_PTE_DEVMAP
36 select ARCH_HAS_PTE_SPECIAL
37 select ARCH_HAS_SETUP_DMA_OPS
38 select ARCH_HAS_SET_DIRECT_MAP
39 select ARCH_HAS_SET_MEMORY
41 select ARCH_HAS_STRICT_KERNEL_RWX
42 select ARCH_HAS_STRICT_MODULE_RWX
43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
44 select ARCH_HAS_SYNC_DMA_FOR_CPU
45 select ARCH_HAS_SYSCALL_WRAPPER
46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
48 select ARCH_HAS_ZONE_DMA_SET if EXPERT
49 select ARCH_HAVE_ELF_PROT
50 select ARCH_HAVE_NMI_SAFE_CMPXCHG
51 select ARCH_HAVE_TRACE_MMIO_ACCESS
52 select ARCH_INLINE_READ_LOCK if !PREEMPTION
53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
78 select ARCH_KEEP_MEMBLOCK
79 select ARCH_USE_CMPXCHG_LOCKREF
80 select ARCH_USE_GNU_PROPERTY
81 select ARCH_USE_MEMTEST
82 select ARCH_USE_QUEUED_RWLOCKS
83 select ARCH_USE_QUEUED_SPINLOCKS
84 select ARCH_USE_SYM_ANNOTATIONS
85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
86 select ARCH_SUPPORTS_HUGETLBFS
87 select ARCH_SUPPORTS_MEMORY_FAILURE
88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
90 select ARCH_SUPPORTS_LTO_CLANG_THIN
91 select ARCH_SUPPORTS_CFI_CLANG
92 select ARCH_SUPPORTS_ATOMIC_RMW
93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
94 select ARCH_SUPPORTS_NUMA_BALANCING
95 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
96 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
97 select ARCH_WANT_DEFAULT_BPF_JIT
98 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
99 select ARCH_WANT_FRAME_POINTERS
100 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
101 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
102 select ARCH_WANT_LD_ORPHAN_WARN
103 select ARCH_WANTS_NO_INSTR
104 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
105 select ARCH_HAS_UBSAN_SANITIZE_ALL
107 select ARM_ARCH_TIMER
109 select AUDIT_ARCH_COMPAT_GENERIC
110 select ARM_GIC_V2M if PCI
112 select ARM_GIC_V3_ITS if PCI
114 select BUILDTIME_TABLE_SORT
115 select CLONE_BACKWARDS
117 select CPU_PM if (SUSPEND || CPU_IDLE)
119 select DCACHE_WORD_ACCESS
120 select DMA_DIRECT_REMAP
123 select GENERIC_ALLOCATOR
124 select GENERIC_ARCH_TOPOLOGY
125 select GENERIC_CLOCKEVENTS_BROADCAST
126 select GENERIC_CPU_AUTOPROBE
127 select GENERIC_CPU_VULNERABILITIES
128 select GENERIC_EARLY_IOREMAP
129 select GENERIC_IDLE_POLL_SETUP
130 select GENERIC_IOREMAP
131 select GENERIC_IRQ_IPI
132 select GENERIC_IRQ_PROBE
133 select GENERIC_IRQ_SHOW
134 select GENERIC_IRQ_SHOW_LEVEL
135 select GENERIC_LIB_DEVMEM_IS_ALLOWED
136 select GENERIC_PCI_IOMAP
137 select GENERIC_PTDUMP
138 select GENERIC_SCHED_CLOCK
139 select GENERIC_SMP_IDLE_THREAD
140 select GENERIC_TIME_VSYSCALL
141 select GENERIC_GETTIMEOFDAY
142 select GENERIC_VDSO_TIME_NS
143 select HARDIRQS_SW_RESEND
147 select HAVE_ACPI_APEI if (ACPI && EFI)
148 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
149 select HAVE_ARCH_AUDITSYSCALL
150 select HAVE_ARCH_BITREVERSE
151 select HAVE_ARCH_COMPILER_H
152 select HAVE_ARCH_HUGE_VMALLOC
153 select HAVE_ARCH_HUGE_VMAP
154 select HAVE_ARCH_JUMP_LABEL
155 select HAVE_ARCH_JUMP_LABEL_RELATIVE
156 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
157 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
158 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
159 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
160 # Some instrumentation may be unsound, hence EXPERT
161 select HAVE_ARCH_KCSAN if EXPERT
162 select HAVE_ARCH_KFENCE
163 select HAVE_ARCH_KGDB
164 select HAVE_ARCH_MMAP_RND_BITS
165 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
166 select HAVE_ARCH_PREL32_RELOCATIONS
167 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
168 select HAVE_ARCH_SECCOMP_FILTER
169 select HAVE_ARCH_STACKLEAK
170 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
171 select HAVE_ARCH_TRACEHOOK
172 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
173 select HAVE_ARCH_VMAP_STACK
174 select HAVE_ARM_SMCCC
175 select HAVE_ASM_MODVERSIONS
177 select HAVE_C_RECORDMCOUNT
178 select HAVE_CMPXCHG_DOUBLE
179 select HAVE_CMPXCHG_LOCAL
180 select HAVE_CONTEXT_TRACKING_USER
181 select HAVE_DEBUG_KMEMLEAK
182 select HAVE_DMA_CONTIGUOUS
183 select HAVE_DYNAMIC_FTRACE
184 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
185 if DYNAMIC_FTRACE_WITH_REGS
186 select HAVE_EFFICIENT_UNALIGNED_ACCESS
188 select HAVE_FTRACE_MCOUNT_RECORD
189 select HAVE_FUNCTION_TRACER
190 select HAVE_FUNCTION_ERROR_INJECTION
191 select HAVE_FUNCTION_GRAPH_TRACER
192 select HAVE_GCC_PLUGINS
193 select HAVE_HW_BREAKPOINT if PERF_EVENTS
194 select HAVE_IOREMAP_PROT
195 select HAVE_IRQ_TIME_ACCOUNTING
198 select HAVE_PATA_PLATFORM
199 select HAVE_PERF_EVENTS
200 select HAVE_PERF_REGS
201 select HAVE_PERF_USER_STACK_DUMP
202 select HAVE_PREEMPT_DYNAMIC_KEY
203 select HAVE_REGS_AND_STACK_ACCESS_API
204 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
205 select HAVE_FUNCTION_ARG_ACCESS_API
206 select MMU_GATHER_RCU_TABLE_FREE
208 select HAVE_STACKPROTECTOR
209 select HAVE_SYSCALL_TRACEPOINTS
211 select HAVE_KRETPROBES
212 select HAVE_GENERIC_VDSO
213 select IOMMU_DMA if IOMMU_SUPPORT
215 select IRQ_FORCED_THREADING
216 select KASAN_VMALLOC if KASAN
217 select MODULES_USE_ELF_RELA
218 select NEED_DMA_MAP_STATE
219 select NEED_SG_DMA_LENGTH
221 select OF_EARLY_FLATTREE
222 select PCI_DOMAINS_GENERIC if PCI
223 select PCI_ECAM if (ACPI && PCI)
224 select PCI_SYSCALL if PCI
229 select SYSCTL_EXCEPTION_TRACE
230 select THREAD_INFO_IN_TASK
231 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
232 select TRACE_IRQFLAGS_SUPPORT
233 select TRACE_IRQFLAGS_NMI_SUPPORT
234 select HAVE_SOFTIRQ_ON_OWN_STACK
236 ARM 64-bit (AArch64) Linux support.
238 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
240 # https://github.com/ClangBuiltLinux/linux/issues/1507
241 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
242 select HAVE_DYNAMIC_FTRACE_WITH_REGS
244 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
246 depends on $(cc-option,-fpatchable-function-entry=2)
247 select HAVE_DYNAMIC_FTRACE_WITH_REGS
255 config ARM64_PAGE_SHIFT
257 default 16 if ARM64_64K_PAGES
258 default 14 if ARM64_16K_PAGES
261 config ARM64_CONT_PTE_SHIFT
263 default 5 if ARM64_64K_PAGES
264 default 7 if ARM64_16K_PAGES
267 config ARM64_CONT_PMD_SHIFT
269 default 5 if ARM64_64K_PAGES
270 default 5 if ARM64_16K_PAGES
273 config ARCH_MMAP_RND_BITS_MIN
274 default 14 if ARM64_64K_PAGES
275 default 16 if ARM64_16K_PAGES
278 # max bits determined by the following formula:
279 # VA_BITS - PAGE_SHIFT - 3
280 config ARCH_MMAP_RND_BITS_MAX
281 default 19 if ARM64_VA_BITS=36
282 default 24 if ARM64_VA_BITS=39
283 default 27 if ARM64_VA_BITS=42
284 default 30 if ARM64_VA_BITS=47
285 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
286 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
287 default 33 if ARM64_VA_BITS=48
288 default 14 if ARM64_64K_PAGES
289 default 16 if ARM64_16K_PAGES
292 config ARCH_MMAP_RND_COMPAT_BITS_MIN
293 default 7 if ARM64_64K_PAGES
294 default 9 if ARM64_16K_PAGES
297 config ARCH_MMAP_RND_COMPAT_BITS_MAX
303 config STACKTRACE_SUPPORT
306 config ILLEGAL_POINTER_VALUE
308 default 0xdead000000000000
310 config LOCKDEP_SUPPORT
317 config GENERIC_BUG_RELATIVE_POINTERS
319 depends on GENERIC_BUG
321 config GENERIC_HWEIGHT
327 config GENERIC_CALIBRATE_DELAY
330 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
336 config KERNEL_MODE_NEON
339 config FIX_EARLYCON_MEM
342 config PGTABLE_LEVELS
344 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
345 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
346 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
347 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
348 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
349 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
351 config ARCH_SUPPORTS_UPROBES
354 config ARCH_PROC_KCORE_TEXT
357 config BROKEN_GAS_INST
358 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
360 config KASAN_SHADOW_OFFSET
362 depends on KASAN_GENERIC || KASAN_SW_TAGS
363 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
364 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
365 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
366 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
367 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
368 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
369 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
370 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
371 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
372 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
373 default 0xffffffffffffffff
375 source "arch/arm64/Kconfig.platforms"
377 menu "Kernel Features"
379 menu "ARM errata workarounds via the alternatives framework"
381 config ARM64_WORKAROUND_CLEAN_CACHE
384 config ARM64_ERRATUM_826319
385 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
387 select ARM64_WORKAROUND_CLEAN_CACHE
389 This option adds an alternative code sequence to work around ARM
390 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
391 AXI master interface and an L2 cache.
393 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
394 and is unable to accept a certain write via this interface, it will
395 not progress on read data presented on the read data channel and the
398 The workaround promotes data cache clean instructions to
399 data cache clean-and-invalidate.
400 Please note that this does not necessarily enable the workaround,
401 as it depends on the alternative framework, which will only patch
402 the kernel if an affected CPU is detected.
406 config ARM64_ERRATUM_827319
407 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
409 select ARM64_WORKAROUND_CLEAN_CACHE
411 This option adds an alternative code sequence to work around ARM
412 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
413 master interface and an L2 cache.
415 Under certain conditions this erratum can cause a clean line eviction
416 to occur at the same time as another transaction to the same address
417 on the AMBA 5 CHI interface, which can cause data corruption if the
418 interconnect reorders the two transactions.
420 The workaround promotes data cache clean instructions to
421 data cache clean-and-invalidate.
422 Please note that this does not necessarily enable the workaround,
423 as it depends on the alternative framework, which will only patch
424 the kernel if an affected CPU is detected.
428 config ARM64_ERRATUM_824069
429 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
431 select ARM64_WORKAROUND_CLEAN_CACHE
433 This option adds an alternative code sequence to work around ARM
434 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
435 to a coherent interconnect.
437 If a Cortex-A53 processor is executing a store or prefetch for
438 write instruction at the same time as a processor in another
439 cluster is executing a cache maintenance operation to the same
440 address, then this erratum might cause a clean cache line to be
441 incorrectly marked as dirty.
443 The workaround promotes data cache clean instructions to
444 data cache clean-and-invalidate.
445 Please note that this option does not necessarily enable the
446 workaround, as it depends on the alternative framework, which will
447 only patch the kernel if an affected CPU is detected.
451 config ARM64_ERRATUM_819472
452 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
454 select ARM64_WORKAROUND_CLEAN_CACHE
456 This option adds an alternative code sequence to work around ARM
457 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
458 present when it is connected to a coherent interconnect.
460 If the processor is executing a load and store exclusive sequence at
461 the same time as a processor in another cluster is executing a cache
462 maintenance operation to the same address, then this erratum might
463 cause data corruption.
465 The workaround promotes data cache clean instructions to
466 data cache clean-and-invalidate.
467 Please note that this does not necessarily enable the workaround,
468 as it depends on the alternative framework, which will only patch
469 the kernel if an affected CPU is detected.
473 config ARM64_ERRATUM_832075
474 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
477 This option adds an alternative code sequence to work around ARM
478 erratum 832075 on Cortex-A57 parts up to r1p2.
480 Affected Cortex-A57 parts might deadlock when exclusive load/store
481 instructions to Write-Back memory are mixed with Device loads.
483 The workaround is to promote device loads to use Load-Acquire
485 Please note that this does not necessarily enable the workaround,
486 as it depends on the alternative framework, which will only patch
487 the kernel if an affected CPU is detected.
491 config ARM64_ERRATUM_834220
492 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
496 This option adds an alternative code sequence to work around ARM
497 erratum 834220 on Cortex-A57 parts up to r1p2.
499 Affected Cortex-A57 parts might report a Stage 2 translation
500 fault as the result of a Stage 1 fault for load crossing a
501 page boundary when there is a permission or device memory
502 alignment fault at Stage 1 and a translation fault at Stage 2.
504 The workaround is to verify that the Stage 1 translation
505 doesn't generate a fault before handling the Stage 2 fault.
506 Please note that this does not necessarily enable the workaround,
507 as it depends on the alternative framework, which will only patch
508 the kernel if an affected CPU is detected.
512 config ARM64_ERRATUM_1742098
513 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
517 This option removes the AES hwcap for aarch32 user-space to
518 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
520 Affected parts may corrupt the AES state if an interrupt is
521 taken between a pair of AES instructions. These instructions
522 are only present if the cryptography extensions are present.
523 All software should have a fallback implementation for CPUs
524 that don't implement the cryptography extensions.
528 config ARM64_ERRATUM_845719
529 bool "Cortex-A53: 845719: a load might read incorrect data"
533 This option adds an alternative code sequence to work around ARM
534 erratum 845719 on Cortex-A53 parts up to r0p4.
536 When running a compat (AArch32) userspace on an affected Cortex-A53
537 part, a load at EL0 from a virtual address that matches the bottom 32
538 bits of the virtual address used by a recent load at (AArch64) EL1
539 might return incorrect data.
541 The workaround is to write the contextidr_el1 register on exception
542 return to a 32-bit task.
543 Please note that this does not necessarily enable the workaround,
544 as it depends on the alternative framework, which will only patch
545 the kernel if an affected CPU is detected.
549 config ARM64_ERRATUM_843419
550 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
552 select ARM64_MODULE_PLTS if MODULES
554 This option links the kernel with '--fix-cortex-a53-843419' and
555 enables PLT support to replace certain ADRP instructions, which can
556 cause subsequent memory accesses to use an incorrect address on
557 Cortex-A53 parts up to r0p4.
561 config ARM64_LD_HAS_FIX_ERRATUM_843419
562 def_bool $(ld-option,--fix-cortex-a53-843419)
564 config ARM64_ERRATUM_1024718
565 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
568 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
570 Affected Cortex-A55 cores (all revisions) could cause incorrect
571 update of the hardware dirty bit when the DBM/AP bits are updated
572 without a break-before-make. The workaround is to disable the usage
573 of hardware DBM locally on the affected cores. CPUs not affected by
574 this erratum will continue to use the feature.
578 config ARM64_ERRATUM_1418040
579 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
583 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
584 errata 1188873 and 1418040.
586 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
587 cause register corruption when accessing the timer registers
588 from AArch32 userspace.
592 config ARM64_WORKAROUND_SPECULATIVE_AT
595 config ARM64_ERRATUM_1165522
596 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
598 select ARM64_WORKAROUND_SPECULATIVE_AT
600 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
602 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
603 corrupted TLBs by speculating an AT instruction during a guest
608 config ARM64_ERRATUM_1319367
609 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
611 select ARM64_WORKAROUND_SPECULATIVE_AT
613 This option adds work arounds for ARM Cortex-A57 erratum 1319537
614 and A72 erratum 1319367
616 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
617 speculating an AT instruction during a guest context switch.
621 config ARM64_ERRATUM_1530923
622 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
624 select ARM64_WORKAROUND_SPECULATIVE_AT
626 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
628 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
629 corrupted TLBs by speculating an AT instruction during a guest
634 config ARM64_WORKAROUND_REPEAT_TLBI
637 config ARM64_ERRATUM_1286807
638 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
640 select ARM64_WORKAROUND_REPEAT_TLBI
642 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
644 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
645 address for a cacheable mapping of a location is being
646 accessed by a core while another core is remapping the virtual
647 address to a new physical page using the recommended
648 break-before-make sequence, then under very rare circumstances
649 TLBI+DSB completes before a read using the translation being
650 invalidated has been observed by other observers. The
651 workaround repeats the TLBI+DSB operation.
653 config ARM64_ERRATUM_1463225
654 bool "Cortex-A76: Software Step might prevent interrupt recognition"
657 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
659 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
660 of a system call instruction (SVC) can prevent recognition of
661 subsequent interrupts when software stepping is disabled in the
662 exception handler of the system call and either kernel debugging
663 is enabled or VHE is in use.
665 Work around the erratum by triggering a dummy step exception
666 when handling a system call from a task that is being stepped
667 in a VHE configuration of the kernel.
671 config ARM64_ERRATUM_1542419
672 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
675 This option adds a workaround for ARM Neoverse-N1 erratum
678 Affected Neoverse-N1 cores could execute a stale instruction when
679 modified by another CPU. The workaround depends on a firmware
682 Workaround the issue by hiding the DIC feature from EL0. This
683 forces user-space to perform cache maintenance.
687 config ARM64_ERRATUM_1508412
688 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
691 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
693 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
694 of a store-exclusive or read of PAR_EL1 and a load with device or
695 non-cacheable memory attributes. The workaround depends on a firmware
698 KVM guests must also have the workaround implemented or they can
701 Work around the issue by inserting DMB SY barriers around PAR_EL1
702 register reads and warning KVM users. The DMB barrier is sufficient
703 to prevent a speculative PAR_EL1 read.
707 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
710 config ARM64_ERRATUM_2051678
711 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
714 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
715 Affected Cortex-A510 might not respect the ordering rules for
716 hardware update of the page table's dirty bit. The workaround
717 is to not enable the feature on affected CPUs.
721 config ARM64_ERRATUM_2077057
722 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
725 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
726 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
727 expected, but a Pointer Authentication trap is taken instead. The
728 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
729 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
731 This can only happen when EL2 is stepping EL1.
733 When these conditions occur, the SPSR_EL2 value is unchanged from the
734 previous guest entry, and can be restored from the in-memory copy.
738 config ARM64_ERRATUM_2658417
739 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
742 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
743 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
744 BFMMLA or VMMLA instructions in rare circumstances when a pair of
745 A510 CPUs are using shared neon hardware. As the sharing is not
746 discoverable by the kernel, hide the BF16 HWCAP to indicate that
747 user-space should not be using these instructions.
751 config ARM64_ERRATUM_2119858
752 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
754 depends on CORESIGHT_TRBE
755 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
757 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
759 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
760 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
761 the event of a WRAP event.
763 Work around the issue by always making sure we move the TRBPTR_EL1 by
764 256 bytes before enabling the buffer and filling the first 256 bytes of
765 the buffer with ETM ignore packets upon disabling.
769 config ARM64_ERRATUM_2139208
770 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
772 depends on CORESIGHT_TRBE
773 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
775 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
777 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
778 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
779 the event of a WRAP event.
781 Work around the issue by always making sure we move the TRBPTR_EL1 by
782 256 bytes before enabling the buffer and filling the first 256 bytes of
783 the buffer with ETM ignore packets upon disabling.
787 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
790 config ARM64_ERRATUM_2054223
791 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
793 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
795 Enable workaround for ARM Cortex-A710 erratum 2054223
797 Affected cores may fail to flush the trace data on a TSB instruction, when
798 the PE is in trace prohibited state. This will cause losing a few bytes
801 Workaround is to issue two TSB consecutively on affected cores.
805 config ARM64_ERRATUM_2067961
806 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
808 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
810 Enable workaround for ARM Neoverse-N2 erratum 2067961
812 Affected cores may fail to flush the trace data on a TSB instruction, when
813 the PE is in trace prohibited state. This will cause losing a few bytes
816 Workaround is to issue two TSB consecutively on affected cores.
820 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
823 config ARM64_ERRATUM_2253138
824 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
825 depends on CORESIGHT_TRBE
827 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
829 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
831 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
832 for TRBE. Under some conditions, the TRBE might generate a write to the next
833 virtually addressed page following the last page of the TRBE address space
834 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
836 Work around this in the driver by always making sure that there is a
837 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
841 config ARM64_ERRATUM_2224489
842 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
843 depends on CORESIGHT_TRBE
845 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
847 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
849 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
850 for TRBE. Under some conditions, the TRBE might generate a write to the next
851 virtually addressed page following the last page of the TRBE address space
852 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
854 Work around this in the driver by always making sure that there is a
855 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
859 config ARM64_ERRATUM_2441009
860 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
862 select ARM64_WORKAROUND_REPEAT_TLBI
864 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
866 Under very rare circumstances, affected Cortex-A510 CPUs
867 may not handle a race between a break-before-make sequence on one
868 CPU, and another CPU accessing the same page. This could allow a
869 store to a page that has been unmapped.
871 Work around this by adding the affected CPUs to the list that needs
872 TLB sequences to be done twice.
876 config ARM64_ERRATUM_2064142
877 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
878 depends on CORESIGHT_TRBE
881 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
883 Affected Cortex-A510 core might fail to write into system registers after the
884 TRBE has been disabled. Under some conditions after the TRBE has been disabled
885 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
886 and TRBTRG_EL1 will be ignored and will not be effected.
888 Work around this in the driver by executing TSB CSYNC and DSB after collection
889 is stopped and before performing a system register write to one of the affected
894 config ARM64_ERRATUM_2038923
895 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
896 depends on CORESIGHT_TRBE
899 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
901 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
902 prohibited within the CPU. As a result, the trace buffer or trace buffer state
903 might be corrupted. This happens after TRBE buffer has been enabled by setting
904 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
905 execution changes from a context, in which trace is prohibited to one where it
906 isn't, or vice versa. In these mentioned conditions, the view of whether trace
907 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
908 the trace buffer state might be corrupted.
910 Work around this in the driver by preventing an inconsistent view of whether the
911 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
912 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
913 two ISB instructions if no ERET is to take place.
917 config ARM64_ERRATUM_1902691
918 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
919 depends on CORESIGHT_TRBE
922 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
924 Affected Cortex-A510 core might cause trace data corruption, when being written
925 into the memory. Effectively TRBE is broken and hence cannot be used to capture
928 Work around this problem in the driver by just preventing TRBE initialization on
929 affected cpus. The firmware must have disabled the access to TRBE for the kernel
930 on such implementations. This will cover the kernel for any firmware that doesn't
935 config ARM64_ERRATUM_2457168
936 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
937 depends on ARM64_AMU_EXTN
940 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
942 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
943 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
944 incorrectly giving a significantly higher output value.
946 Work around this problem by returning 0 when reading the affected counter in
947 key locations that results in disabling all users of this counter. This effect
948 is the same to firmware disabling affected counters.
952 config CAVIUM_ERRATUM_22375
953 bool "Cavium erratum 22375, 24313"
956 Enable workaround for errata 22375 and 24313.
958 This implements two gicv3-its errata workarounds for ThunderX. Both
959 with a small impact affecting only ITS table allocation.
961 erratum 22375: only alloc 8MB table size
962 erratum 24313: ignore memory access type
964 The fixes are in ITS initialization and basically ignore memory access
965 type and table size provided by the TYPER and BASER registers.
969 config CAVIUM_ERRATUM_23144
970 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
974 ITS SYNC command hang for cross node io and collections/cpu mapping.
978 config CAVIUM_ERRATUM_23154
979 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
982 The ThunderX GICv3 implementation requires a modified version for
983 reading the IAR status to ensure data synchronization
984 (access to icc_iar1_el1 is not sync'ed before and after).
986 It also suffers from erratum 38545 (also present on Marvell's
987 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
988 spuriously presented to the CPU interface.
992 config CAVIUM_ERRATUM_27456
993 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
996 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
997 instructions may cause the icache to become corrupted if it
998 contains data for a non-current ASID. The fix is to
999 invalidate the icache when changing the mm context.
1003 config CAVIUM_ERRATUM_30115
1004 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1007 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1008 1.2, and T83 Pass 1.0, KVM guest execution may disable
1009 interrupts in host. Trapping both GICv3 group-0 and group-1
1010 accesses sidesteps the issue.
1014 config CAVIUM_TX2_ERRATUM_219
1015 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1018 On Cavium ThunderX2, a load, store or prefetch instruction between a
1019 TTBR update and the corresponding context synchronizing operation can
1020 cause a spurious Data Abort to be delivered to any hardware thread in
1023 Work around the issue by avoiding the problematic code sequence and
1024 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1025 trap handler performs the corresponding register access, skips the
1026 instruction and ensures context synchronization by virtue of the
1031 config FUJITSU_ERRATUM_010001
1032 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1035 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1036 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1037 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1038 This fault occurs under a specific hardware condition when a
1039 load/store instruction performs an address translation using:
1040 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1041 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1042 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1043 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1045 The workaround is to ensure these bits are clear in TCR_ELx.
1046 The workaround only affects the Fujitsu-A64FX.
1050 config HISILICON_ERRATUM_161600802
1051 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1054 The HiSilicon Hip07 SoC uses the wrong redistributor base
1055 when issued ITS commands such as VMOVP and VMAPP, and requires
1056 a 128kB offset to be applied to the target address in this commands.
1060 config QCOM_FALKOR_ERRATUM_1003
1061 bool "Falkor E1003: Incorrect translation due to ASID change"
1064 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1065 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1066 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1067 then only for entries in the walk cache, since the leaf translation
1068 is unchanged. Work around the erratum by invalidating the walk cache
1069 entries for the trampoline before entering the kernel proper.
1071 config QCOM_FALKOR_ERRATUM_1009
1072 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1074 select ARM64_WORKAROUND_REPEAT_TLBI
1076 On Falkor v1, the CPU may prematurely complete a DSB following a
1077 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1078 one more time to fix the issue.
1082 config QCOM_QDF2400_ERRATUM_0065
1083 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1086 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1087 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1088 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1092 config QCOM_FALKOR_ERRATUM_E1041
1093 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1096 Falkor CPU may speculatively fetch instructions from an improper
1097 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1098 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1102 config NVIDIA_CARMEL_CNP_ERRATUM
1103 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1106 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1107 invalidate shared TLB entries installed by a different core, as it would
1108 on standard ARM cores.
1112 config SOCIONEXT_SYNQUACER_PREITS
1113 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1116 Socionext Synquacer SoCs implement a separate h/w block to generate
1117 MSI doorbell writes with non-zero values for the device ID.
1121 endmenu # "ARM errata workarounds via the alternatives framework"
1125 default ARM64_4K_PAGES
1127 Page size (translation granule) configuration.
1129 config ARM64_4K_PAGES
1132 This feature enables 4KB pages support.
1134 config ARM64_16K_PAGES
1137 The system will use 16KB pages support. AArch32 emulation
1138 requires applications compiled with 16K (or a multiple of 16K)
1141 config ARM64_64K_PAGES
1144 This feature enables 64KB pages support (4KB by default)
1145 allowing only two levels of page tables and faster TLB
1146 look-up. AArch32 emulation requires applications compiled
1147 with 64K aligned segments.
1152 prompt "Virtual address space size"
1153 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1154 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1155 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1157 Allows choosing one of multiple possible virtual address
1158 space sizes. The level of translation table is determined by
1159 a combination of page size and virtual address space size.
1161 config ARM64_VA_BITS_36
1162 bool "36-bit" if EXPERT
1163 depends on ARM64_16K_PAGES
1165 config ARM64_VA_BITS_39
1167 depends on ARM64_4K_PAGES
1169 config ARM64_VA_BITS_42
1171 depends on ARM64_64K_PAGES
1173 config ARM64_VA_BITS_47
1175 depends on ARM64_16K_PAGES
1177 config ARM64_VA_BITS_48
1180 config ARM64_VA_BITS_52
1182 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1184 Enable 52-bit virtual addressing for userspace when explicitly
1185 requested via a hint to mmap(). The kernel will also use 52-bit
1186 virtual addresses for its own mappings (provided HW support for
1187 this feature is available, otherwise it reverts to 48-bit).
1189 NOTE: Enabling 52-bit virtual addressing in conjunction with
1190 ARMv8.3 Pointer Authentication will result in the PAC being
1191 reduced from 7 bits to 3 bits, which may have a significant
1192 impact on its susceptibility to brute-force attacks.
1194 If unsure, select 48-bit virtual addressing instead.
1198 config ARM64_FORCE_52BIT
1199 bool "Force 52-bit virtual addresses for userspace"
1200 depends on ARM64_VA_BITS_52 && EXPERT
1202 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1203 to maintain compatibility with older software by providing 48-bit VAs
1204 unless a hint is supplied to mmap.
1206 This configuration option disables the 48-bit compatibility logic, and
1207 forces all userspace addresses to be 52-bit on HW that supports it. One
1208 should only enable this configuration option for stress testing userspace
1209 memory management code. If unsure say N here.
1211 config ARM64_VA_BITS
1213 default 36 if ARM64_VA_BITS_36
1214 default 39 if ARM64_VA_BITS_39
1215 default 42 if ARM64_VA_BITS_42
1216 default 47 if ARM64_VA_BITS_47
1217 default 48 if ARM64_VA_BITS_48
1218 default 52 if ARM64_VA_BITS_52
1221 prompt "Physical address space size"
1222 default ARM64_PA_BITS_48
1224 Choose the maximum physical address range that the kernel will
1227 config ARM64_PA_BITS_48
1230 config ARM64_PA_BITS_52
1231 bool "52-bit (ARMv8.2)"
1232 depends on ARM64_64K_PAGES
1233 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1235 Enable support for a 52-bit physical address space, introduced as
1236 part of the ARMv8.2-LPA extension.
1238 With this enabled, the kernel will also continue to work on CPUs that
1239 do not support ARMv8.2-LPA, but with some added memory overhead (and
1240 minor performance overhead).
1244 config ARM64_PA_BITS
1246 default 48 if ARM64_PA_BITS_48
1247 default 52 if ARM64_PA_BITS_52
1251 default CPU_LITTLE_ENDIAN
1253 Select the endianness of data accesses performed by the CPU. Userspace
1254 applications will need to be compiled and linked for the endianness
1255 that is selected here.
1257 config CPU_BIG_ENDIAN
1258 bool "Build big-endian kernel"
1259 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1261 Say Y if you plan on running a kernel with a big-endian userspace.
1263 config CPU_LITTLE_ENDIAN
1264 bool "Build little-endian kernel"
1266 Say Y if you plan on running a kernel with a little-endian userspace.
1267 This is usually the case for distributions targeting arm64.
1272 bool "Multi-core scheduler support"
1274 Multi-core scheduler support improves the CPU scheduler's decision
1275 making when dealing with multi-core CPU chips at a cost of slightly
1276 increased overhead in some places. If unsure say N here.
1278 config SCHED_CLUSTER
1279 bool "Cluster scheduler support"
1281 Cluster scheduler support improves the CPU scheduler's decision
1282 making when dealing with machines that have clusters of CPUs.
1283 Cluster usually means a couple of CPUs which are placed closely
1284 by sharing mid-level caches, last-level cache tags or internal
1288 bool "SMT scheduler support"
1290 Improves the CPU scheduler's decision making when dealing with
1291 MultiThreading at a cost of slightly increased overhead in some
1292 places. If unsure say N here.
1295 int "Maximum number of CPUs (2-4096)"
1300 bool "Support for hot-pluggable CPUs"
1301 select GENERIC_IRQ_MIGRATION
1303 Say Y here to experiment with turning CPUs off and on. CPUs
1304 can be controlled through /sys/devices/system/cpu.
1306 # Common NUMA Features
1308 bool "NUMA Memory Allocation and Scheduler Support"
1309 select GENERIC_ARCH_NUMA
1310 select ACPI_NUMA if ACPI
1312 select HAVE_SETUP_PER_CPU_AREA
1313 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1314 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1315 select USE_PERCPU_NUMA_NODE_ID
1317 Enable NUMA (Non-Uniform Memory Access) support.
1319 The kernel will try to allocate memory used by a CPU on the
1320 local memory of the CPU and add some more
1321 NUMA awareness to the kernel.
1324 int "Maximum NUMA Nodes (as a power of 2)"
1329 Specify the maximum number of NUMA Nodes available on the target
1330 system. Increases memory reserved to accommodate various tables.
1332 source "kernel/Kconfig.hz"
1334 config ARCH_SPARSEMEM_ENABLE
1336 select SPARSEMEM_VMEMMAP_ENABLE
1337 select SPARSEMEM_VMEMMAP
1339 config HW_PERF_EVENTS
1343 # Supported by clang >= 7.0 or GCC >= 12.0.0
1344 config CC_HAVE_SHADOW_CALL_STACK
1345 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1348 bool "Enable paravirtualization code"
1350 This changes the kernel so it can modify itself when it is run
1351 under a hypervisor, potentially improving performance significantly
1352 over full virtualization.
1354 config PARAVIRT_TIME_ACCOUNTING
1355 bool "Paravirtual steal time accounting"
1358 Select this option to enable fine granularity task steal time
1359 accounting. Time spent executing other tasks in parallel with
1360 the current vCPU is discounted from the vCPU power. To account for
1361 that, there can be a small performance impact.
1363 If in doubt, say N here.
1366 depends on PM_SLEEP_SMP
1368 bool "kexec system call"
1370 kexec is a system call that implements the ability to shutdown your
1371 current kernel, and to start another kernel. It is like a reboot
1372 but it is independent of the system firmware. And like a reboot
1373 you can start any kernel with it, not just Linux.
1376 bool "kexec file based system call"
1378 select HAVE_IMA_KEXEC if IMA
1380 This is new version of kexec system call. This system call is
1381 file based and takes file descriptors as system call argument
1382 for kernel and initramfs as opposed to list of segments as
1383 accepted by previous system call.
1386 bool "Verify kernel signature during kexec_file_load() syscall"
1387 depends on KEXEC_FILE
1389 Select this option to verify a signature with loaded kernel
1390 image. If configured, any attempt of loading a image without
1391 valid signature will fail.
1393 In addition to that option, you need to enable signature
1394 verification for the corresponding kernel image type being
1395 loaded in order for this to work.
1397 config KEXEC_IMAGE_VERIFY_SIG
1398 bool "Enable Image signature verification support"
1400 depends on KEXEC_SIG
1401 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1403 Enable Image signature verification support.
1405 comment "Support for PE file signature verification disabled"
1406 depends on KEXEC_SIG
1407 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1410 bool "Build kdump crash kernel"
1412 Generate crash dump after being started by kexec. This should
1413 be normally only set in special crash dump kernels which are
1414 loaded in the main kernel with kexec-tools into a specially
1415 reserved region and then later executed after a crash by
1418 For more details see Documentation/admin-guide/kdump/kdump.rst
1422 depends on HIBERNATION || KEXEC_CORE
1429 bool "Xen guest support on ARM64"
1430 depends on ARM64 && OF
1434 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1436 config FORCE_MAX_ZONEORDER
1438 default "14" if ARM64_64K_PAGES
1439 default "12" if ARM64_16K_PAGES
1442 The kernel memory allocator divides physically contiguous memory
1443 blocks into "zones", where each zone is a power of two number of
1444 pages. This option selects the largest power of two that the kernel
1445 keeps in the memory allocator. If you need to allocate very large
1446 blocks of physically contiguous memory, then you may need to
1447 increase this value.
1449 This config option is actually maximum order plus one. For example,
1450 a value of 11 means that the largest free memory block is 2^10 pages.
1452 We make sure that we can allocate upto a HugePage size for each configuration.
1454 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1456 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1457 4M allocations matching the default size used by generic code.
1459 config UNMAP_KERNEL_AT_EL0
1460 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1463 Speculation attacks against some high-performance processors can
1464 be used to bypass MMU permission checks and leak kernel data to
1465 userspace. This can be defended against by unmapping the kernel
1466 when running in userspace, mapping it back in on exception entry
1467 via a trampoline page in the vector table.
1471 config MITIGATE_SPECTRE_BRANCH_HISTORY
1472 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1475 Speculation attacks against some high-performance processors can
1476 make use of branch history to influence future speculation.
1477 When taking an exception from user-space, a sequence of branches
1478 or a firmware call overwrites the branch history.
1480 config RODATA_FULL_DEFAULT_ENABLED
1481 bool "Apply r/o permissions of VM areas also to their linear aliases"
1484 Apply read-only attributes of VM areas to the linear alias of
1485 the backing pages as well. This prevents code or read-only data
1486 from being modified (inadvertently or intentionally) via another
1487 mapping of the same memory page. This additional enhancement can
1488 be turned off at runtime by passing rodata=[off|on] (and turned on
1489 with rodata=full if this option is set to 'n')
1491 This requires the linear region to be mapped down to pages,
1492 which may adversely affect performance in some cases.
1494 config ARM64_SW_TTBR0_PAN
1495 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1497 Enabling this option prevents the kernel from accessing
1498 user-space memory directly by pointing TTBR0_EL1 to a reserved
1499 zeroed area and reserved ASID. The user access routines
1500 restore the valid TTBR0_EL1 temporarily.
1502 config ARM64_TAGGED_ADDR_ABI
1503 bool "Enable the tagged user addresses syscall ABI"
1506 When this option is enabled, user applications can opt in to a
1507 relaxed ABI via prctl() allowing tagged addresses to be passed
1508 to system calls as pointer arguments. For details, see
1509 Documentation/arm64/tagged-address-abi.rst.
1512 bool "Kernel support for 32-bit EL0"
1513 depends on ARM64_4K_PAGES || EXPERT
1515 select OLD_SIGSUSPEND3
1516 select COMPAT_OLD_SIGACTION
1518 This option enables support for a 32-bit EL0 running under a 64-bit
1519 kernel at EL1. AArch32-specific components such as system calls,
1520 the user helper functions, VFP support and the ptrace interface are
1521 handled appropriately by the kernel.
1523 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1524 that you will only be able to execute AArch32 binaries that were compiled
1525 with page size aligned segments.
1527 If you want to execute 32-bit userspace applications, say Y.
1531 config KUSER_HELPERS
1532 bool "Enable kuser helpers page for 32-bit applications"
1535 Warning: disabling this option may break 32-bit user programs.
1537 Provide kuser helpers to compat tasks. The kernel provides
1538 helper code to userspace in read only form at a fixed location
1539 to allow userspace to be independent of the CPU type fitted to
1540 the system. This permits binaries to be run on ARMv4 through
1541 to ARMv8 without modification.
1543 See Documentation/arm/kernel_user_helpers.rst for details.
1545 However, the fixed address nature of these helpers can be used
1546 by ROP (return orientated programming) authors when creating
1549 If all of the binaries and libraries which run on your platform
1550 are built specifically for your platform, and make no use of
1551 these helpers, then you can turn this option off to hinder
1552 such exploits. However, in that case, if a binary or library
1553 relying on those helpers is run, it will not function correctly.
1555 Say N here only if you are absolutely certain that you do not
1556 need these helpers; otherwise, the safe option is to say Y.
1559 bool "Enable vDSO for 32-bit applications"
1560 depends on !CPU_BIG_ENDIAN
1561 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1562 select GENERIC_COMPAT_VDSO
1565 Place in the process address space of 32-bit applications an
1566 ELF shared object providing fast implementations of gettimeofday
1569 You must have a 32-bit build of glibc 2.22 or later for programs
1570 to seamlessly take advantage of this.
1572 config THUMB2_COMPAT_VDSO
1573 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1574 depends on COMPAT_VDSO
1577 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1578 otherwise with '-marm'.
1580 config COMPAT_ALIGNMENT_FIXUPS
1581 bool "Fix up misaligned multi-word loads and stores in user space"
1583 menuconfig ARMV8_DEPRECATED
1584 bool "Emulate deprecated/obsolete ARMv8 instructions"
1587 Legacy software support may require certain instructions
1588 that have been deprecated or obsoleted in the architecture.
1590 Enable this config to enable selective emulation of these
1597 config SWP_EMULATION
1598 bool "Emulate SWP/SWPB instructions"
1600 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1601 they are always undefined. Say Y here to enable software
1602 emulation of these instructions for userspace using LDXR/STXR.
1603 This feature can be controlled at runtime with the abi.swp
1604 sysctl which is disabled by default.
1606 In some older versions of glibc [<=2.8] SWP is used during futex
1607 trylock() operations with the assumption that the code will not
1608 be preempted. This invalid assumption may be more likely to fail
1609 with SWP emulation enabled, leading to deadlock of the user
1612 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1613 on an external transaction monitoring block called a global
1614 monitor to maintain update atomicity. If your system does not
1615 implement a global monitor, this option can cause programs that
1616 perform SWP operations to uncached memory to deadlock.
1620 config CP15_BARRIER_EMULATION
1621 bool "Emulate CP15 Barrier instructions"
1623 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1624 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1625 strongly recommended to use the ISB, DSB, and DMB
1626 instructions instead.
1628 Say Y here to enable software emulation of these
1629 instructions for AArch32 userspace code. When this option is
1630 enabled, CP15 barrier usage is traced which can help
1631 identify software that needs updating. This feature can be
1632 controlled at runtime with the abi.cp15_barrier sysctl.
1636 config SETEND_EMULATION
1637 bool "Emulate SETEND instruction"
1639 The SETEND instruction alters the data-endianness of the
1640 AArch32 EL0, and is deprecated in ARMv8.
1642 Say Y here to enable software emulation of the instruction
1643 for AArch32 userspace code. This feature can be controlled
1644 at runtime with the abi.setend sysctl.
1646 Note: All the cpus on the system must have mixed endian support at EL0
1647 for this feature to be enabled. If a new CPU - which doesn't support mixed
1648 endian - is hotplugged in after this feature has been enabled, there could
1649 be unexpected results in the applications.
1652 endif # ARMV8_DEPRECATED
1656 menu "ARMv8.1 architectural features"
1658 config ARM64_HW_AFDBM
1659 bool "Support for hardware updates of the Access and Dirty page flags"
1662 The ARMv8.1 architecture extensions introduce support for
1663 hardware updates of the access and dirty information in page
1664 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1665 capable processors, accesses to pages with PTE_AF cleared will
1666 set this bit instead of raising an access flag fault.
1667 Similarly, writes to read-only pages with the DBM bit set will
1668 clear the read-only bit (AP[2]) instead of raising a
1671 Kernels built with this configuration option enabled continue
1672 to work on pre-ARMv8.1 hardware and the performance impact is
1673 minimal. If unsure, say Y.
1676 bool "Enable support for Privileged Access Never (PAN)"
1679 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1680 prevents the kernel or hypervisor from accessing user-space (EL0)
1683 Choosing this option will cause any unprotected (not using
1684 copy_to_user et al) memory access to fail with a permission fault.
1686 The feature is detected at runtime, and will remain as a 'nop'
1687 instruction if the cpu does not implement the feature.
1690 def_bool $(as-instr,.arch_extension rcpc)
1692 config AS_HAS_LSE_ATOMICS
1693 def_bool $(as-instr,.arch_extension lse)
1695 config ARM64_LSE_ATOMICS
1697 default ARM64_USE_LSE_ATOMICS
1698 depends on AS_HAS_LSE_ATOMICS
1700 config ARM64_USE_LSE_ATOMICS
1701 bool "Atomic instructions"
1702 depends on JUMP_LABEL
1705 As part of the Large System Extensions, ARMv8.1 introduces new
1706 atomic instructions that are designed specifically to scale in
1709 Say Y here to make use of these instructions for the in-kernel
1710 atomic routines. This incurs a small overhead on CPUs that do
1711 not support these instructions and requires the kernel to be
1712 built with binutils >= 2.25 in order for the new instructions
1715 endmenu # "ARMv8.1 architectural features"
1717 menu "ARMv8.2 architectural features"
1719 config AS_HAS_ARMV8_2
1720 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1723 def_bool $(as-instr,.arch armv8.2-a+sha3)
1726 bool "Enable support for persistent memory"
1727 select ARCH_HAS_PMEM_API
1728 select ARCH_HAS_UACCESS_FLUSHCACHE
1730 Say Y to enable support for the persistent memory API based on the
1731 ARMv8.2 DCPoP feature.
1733 The feature is detected at runtime, and the kernel will use DC CVAC
1734 operations if DC CVAP is not supported (following the behaviour of
1735 DC CVAP itself if the system does not define a point of persistence).
1737 config ARM64_RAS_EXTN
1738 bool "Enable support for RAS CPU Extensions"
1741 CPUs that support the Reliability, Availability and Serviceability
1742 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1743 errors, classify them and report them to software.
1745 On CPUs with these extensions system software can use additional
1746 barriers to determine if faults are pending and read the
1747 classification from a new set of registers.
1749 Selecting this feature will allow the kernel to use these barriers
1750 and access the new registers if the system supports the extension.
1751 Platform RAS features may additionally depend on firmware support.
1754 bool "Enable support for Common Not Private (CNP) translations"
1756 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1758 Common Not Private (CNP) allows translation table entries to
1759 be shared between different PEs in the same inner shareable
1760 domain, so the hardware can use this fact to optimise the
1761 caching of such entries in the TLB.
1763 Selecting this option allows the CNP feature to be detected
1764 at runtime, and does not affect PEs that do not implement
1767 endmenu # "ARMv8.2 architectural features"
1769 menu "ARMv8.3 architectural features"
1771 config ARM64_PTR_AUTH
1772 bool "Enable support for pointer authentication"
1775 Pointer authentication (part of the ARMv8.3 Extensions) provides
1776 instructions for signing and authenticating pointers against secret
1777 keys, which can be used to mitigate Return Oriented Programming (ROP)
1780 This option enables these instructions at EL0 (i.e. for userspace).
1781 Choosing this option will cause the kernel to initialise secret keys
1782 for each process at exec() time, with these keys being
1783 context-switched along with the process.
1785 The feature is detected at runtime. If the feature is not present in
1786 hardware it will not be advertised to userspace/KVM guest nor will it
1789 If the feature is present on the boot CPU but not on a late CPU, then
1790 the late CPU will be parked. Also, if the boot CPU does not have
1791 address auth and the late CPU has then the late CPU will still boot
1792 but with the feature disabled. On such a system, this option should
1795 config ARM64_PTR_AUTH_KERNEL
1796 bool "Use pointer authentication for kernel"
1798 depends on ARM64_PTR_AUTH
1799 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1800 # Modern compilers insert a .note.gnu.property section note for PAC
1801 # which is only understood by binutils starting with version 2.33.1.
1802 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1803 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1804 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1806 If the compiler supports the -mbranch-protection or
1807 -msign-return-address flag (e.g. GCC 7 or later), then this option
1808 will cause the kernel itself to be compiled with return address
1809 protection. In this case, and if the target hardware is known to
1810 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1811 disabled with minimal loss of protection.
1813 This feature works with FUNCTION_GRAPH_TRACER option only if
1814 DYNAMIC_FTRACE_WITH_REGS is enabled.
1816 config CC_HAS_BRANCH_PROT_PAC_RET
1817 # GCC 9 or later, clang 8 or later
1818 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1820 config CC_HAS_SIGN_RETURN_ADDRESS
1822 def_bool $(cc-option,-msign-return-address=all)
1825 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1827 config AS_HAS_CFI_NEGATE_RA_STATE
1828 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1830 endmenu # "ARMv8.3 architectural features"
1832 menu "ARMv8.4 architectural features"
1834 config ARM64_AMU_EXTN
1835 bool "Enable support for the Activity Monitors Unit CPU extension"
1838 The activity monitors extension is an optional extension introduced
1839 by the ARMv8.4 CPU architecture. This enables support for version 1
1840 of the activity monitors architecture, AMUv1.
1842 To enable the use of this extension on CPUs that implement it, say Y.
1844 Note that for architectural reasons, firmware _must_ implement AMU
1845 support when running on CPUs that present the activity monitors
1846 extension. The required support is present in:
1847 * Version 1.5 and later of the ARM Trusted Firmware
1849 For kernels that have this configuration enabled but boot with broken
1850 firmware, you may need to say N here until the firmware is fixed.
1851 Otherwise you may experience firmware panics or lockups when
1852 accessing the counter registers. Even if you are not observing these
1853 symptoms, the values returned by the register reads might not
1854 correctly reflect reality. Most commonly, the value read will be 0,
1855 indicating that the counter is not enabled.
1857 config AS_HAS_ARMV8_4
1858 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1860 config ARM64_TLB_RANGE
1861 bool "Enable support for tlbi range feature"
1863 depends on AS_HAS_ARMV8_4
1865 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1866 range of input addresses.
1868 The feature introduces new assembly instructions, and they were
1869 support when binutils >= 2.30.
1871 endmenu # "ARMv8.4 architectural features"
1873 menu "ARMv8.5 architectural features"
1875 config AS_HAS_ARMV8_5
1876 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1879 bool "Branch Target Identification support"
1882 Branch Target Identification (part of the ARMv8.5 Extensions)
1883 provides a mechanism to limit the set of locations to which computed
1884 branch instructions such as BR or BLR can jump.
1886 To make use of BTI on CPUs that support it, say Y.
1888 BTI is intended to provide complementary protection to other control
1889 flow integrity protection mechanisms, such as the Pointer
1890 authentication mechanism provided as part of the ARMv8.3 Extensions.
1891 For this reason, it does not make sense to enable this option without
1892 also enabling support for pointer authentication. Thus, when
1893 enabling this option you should also select ARM64_PTR_AUTH=y.
1895 Userspace binaries must also be specifically compiled to make use of
1896 this mechanism. If you say N here or the hardware does not support
1897 BTI, such binaries can still run, but you get no additional
1898 enforcement of branch destinations.
1900 config ARM64_BTI_KERNEL
1901 bool "Use Branch Target Identification for kernel"
1903 depends on ARM64_BTI
1904 depends on ARM64_PTR_AUTH_KERNEL
1905 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1906 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1907 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1908 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1909 depends on !CC_IS_GCC
1910 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1911 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1912 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1914 Build the kernel with Branch Target Identification annotations
1915 and enable enforcement of this for kernel code. When this option
1916 is enabled and the system supports BTI all kernel code including
1917 modular code must have BTI enabled.
1919 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1920 # GCC 9 or later, clang 8 or later
1921 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1924 bool "Enable support for E0PD"
1927 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1928 that EL0 accesses made via TTBR1 always fault in constant time,
1929 providing similar benefits to KASLR as those provided by KPTI, but
1930 with lower overhead and without disrupting legitimate access to
1931 kernel memory such as SPE.
1933 This option enables E0PD for TTBR1 where available.
1935 config ARM64_AS_HAS_MTE
1936 # Initial support for MTE went in binutils 2.32.0, checked with
1937 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1938 # as a late addition to the final architecture spec (LDGM/STGM)
1939 # is only supported in the newer 2.32.x and 2.33 binutils
1940 # versions, hence the extra "stgm" instruction check below.
1941 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1944 bool "Memory Tagging Extension support"
1946 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1947 depends on AS_HAS_ARMV8_5
1948 depends on AS_HAS_LSE_ATOMICS
1949 # Required for tag checking in the uaccess routines
1950 depends on ARM64_PAN
1951 select ARCH_HAS_SUBPAGE_FAULTS
1952 select ARCH_USES_HIGH_VMA_FLAGS
1954 Memory Tagging (part of the ARMv8.5 Extensions) provides
1955 architectural support for run-time, always-on detection of
1956 various classes of memory error to aid with software debugging
1957 to eliminate vulnerabilities arising from memory-unsafe
1960 This option enables the support for the Memory Tagging
1961 Extension at EL0 (i.e. for userspace).
1963 Selecting this option allows the feature to be detected at
1964 runtime. Any secondary CPU not implementing this feature will
1965 not be allowed a late bring-up.
1967 Userspace binaries that want to use this feature must
1968 explicitly opt in. The mechanism for the userspace is
1971 Documentation/arm64/memory-tagging-extension.rst.
1973 endmenu # "ARMv8.5 architectural features"
1975 menu "ARMv8.7 architectural features"
1978 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1980 depends on ARM64_PAN
1982 Enhanced Privileged Access Never (EPAN) allows Privileged
1983 Access Never to be used with Execute-only mappings.
1985 The feature is detected at runtime, and will remain disabled
1986 if the cpu does not implement the feature.
1987 endmenu # "ARMv8.7 architectural features"
1990 bool "ARM Scalable Vector Extension support"
1993 The Scalable Vector Extension (SVE) is an extension to the AArch64
1994 execution state which complements and extends the SIMD functionality
1995 of the base architecture to support much larger vectors and to enable
1996 additional vectorisation opportunities.
1998 To enable use of this extension on CPUs that implement it, say Y.
2000 On CPUs that support the SVE2 extensions, this option will enable
2003 Note that for architectural reasons, firmware _must_ implement SVE
2004 support when running on SVE capable hardware. The required support
2007 * version 1.5 and later of the ARM Trusted Firmware
2008 * the AArch64 boot wrapper since commit 5e1261e08abf
2009 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2011 For other firmware implementations, consult the firmware documentation
2014 If you need the kernel to boot on SVE-capable hardware with broken
2015 firmware, you may need to say N here until you get your firmware
2016 fixed. Otherwise, you may experience firmware panics or lockups when
2017 booting the kernel. If unsure and you are not observing these
2018 symptoms, you should assume that it is safe to say Y.
2021 bool "ARM Scalable Matrix Extension support"
2023 depends on ARM64_SVE
2025 The Scalable Matrix Extension (SME) is an extension to the AArch64
2026 execution state which utilises a substantial subset of the SVE
2027 instruction set, together with the addition of new architectural
2028 register state capable of holding two dimensional matrix tiles to
2029 enable various matrix operations.
2031 config ARM64_MODULE_PLTS
2032 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2034 select HAVE_MOD_ARCH_SPECIFIC
2036 Allocate PLTs when loading modules so that jumps and calls whose
2037 targets are too far away for their relative offsets to be encoded
2038 in the instructions themselves can be bounced via veneers in the
2039 module's PLT. This allows modules to be allocated in the generic
2040 vmalloc area after the dedicated module memory area has been
2043 When running with address space randomization (KASLR), the module
2044 region itself may be too far away for ordinary relative jumps and
2045 calls, and so in that case, module PLTs are required and cannot be
2048 Specific errata workaround(s) might also force module PLTs to be
2049 enabled (ARM64_ERRATUM_843419).
2051 config ARM64_PSEUDO_NMI
2052 bool "Support for NMI-like interrupts"
2055 Adds support for mimicking Non-Maskable Interrupts through the use of
2056 GIC interrupt priority. This support requires version 3 or later of
2059 This high priority configuration for interrupts needs to be
2060 explicitly enabled by setting the kernel parameter
2061 "irqchip.gicv3_pseudo_nmi" to 1.
2066 config ARM64_DEBUG_PRIORITY_MASKING
2067 bool "Debug interrupt priority masking"
2069 This adds runtime checks to functions enabling/disabling
2070 interrupts when using priority masking. The additional checks verify
2071 the validity of ICC_PMR_EL1 when calling concerned functions.
2074 endif # ARM64_PSEUDO_NMI
2077 bool "Build a relocatable kernel image" if EXPERT
2078 select ARCH_HAS_RELR
2081 This builds the kernel as a Position Independent Executable (PIE),
2082 which retains all relocation metadata required to relocate the
2083 kernel binary at runtime to a different virtual address than the
2084 address it was linked at.
2085 Since AArch64 uses the RELA relocation format, this requires a
2086 relocation pass at runtime even if the kernel is loaded at the
2087 same address it was linked at.
2089 config RANDOMIZE_BASE
2090 bool "Randomize the address of the kernel image"
2091 select ARM64_MODULE_PLTS if MODULES
2094 Randomizes the virtual address at which the kernel image is
2095 loaded, as a security feature that deters exploit attempts
2096 relying on knowledge of the location of kernel internals.
2098 It is the bootloader's job to provide entropy, by passing a
2099 random u64 value in /chosen/kaslr-seed at kernel entry.
2101 When booting via the UEFI stub, it will invoke the firmware's
2102 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2103 to the kernel proper. In addition, it will randomise the physical
2104 location of the kernel Image as well.
2108 config RANDOMIZE_MODULE_REGION_FULL
2109 bool "Randomize the module region over a 2 GB range"
2110 depends on RANDOMIZE_BASE
2113 Randomizes the location of the module region inside a 2 GB window
2114 covering the core kernel. This way, it is less likely for modules
2115 to leak information about the location of core kernel data structures
2116 but it does imply that function calls between modules and the core
2117 kernel will need to be resolved via veneers in the module PLT.
2119 When this option is not set, the module region will be randomized over
2120 a limited range that contains the [_stext, _etext] interval of the
2121 core kernel, so branch relocations are almost always in range unless
2122 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2123 particular case of region exhaustion, modules might be able to fall
2124 back to a larger 2GB area.
2126 config CC_HAVE_STACKPROTECTOR_SYSREG
2127 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2129 config STACKPROTECTOR_PER_TASK
2131 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2133 # The GPIO number here must be sorted by descending number. In case of
2134 # a multiplatform kernel, we just want the highest value required by the
2135 # selected platforms.
2138 default 2048 if ARCH_APPLE
2141 Maximum number of GPIOs in the system.
2143 If unsure, leave the default value.
2145 endmenu # "Kernel Features"
2149 config ARM64_ACPI_PARKING_PROTOCOL
2150 bool "Enable support for the ARM64 ACPI parking protocol"
2153 Enable support for the ARM64 ACPI parking protocol. If disabled
2154 the kernel will not allow booting through the ARM64 ACPI parking
2155 protocol even if the corresponding data is present in the ACPI
2159 string "Default kernel command string"
2162 Provide a set of default command-line options at build time by
2163 entering them here. As a minimum, you should specify the the
2164 root device (e.g. root=/dev/nfs).
2167 prompt "Kernel command line type" if CMDLINE != ""
2168 default CMDLINE_FROM_BOOTLOADER
2170 Choose how the kernel will handle the provided default kernel
2171 command line string.
2173 config CMDLINE_FROM_BOOTLOADER
2174 bool "Use bootloader kernel arguments if available"
2176 Uses the command-line options passed by the boot loader. If
2177 the boot loader doesn't provide any, the default kernel command
2178 string provided in CMDLINE will be used.
2180 config CMDLINE_FORCE
2181 bool "Always use the default kernel command string"
2183 Always use the default kernel command string, even if the boot
2184 loader passes other arguments to the kernel.
2185 This is useful if you cannot or don't want to change the
2186 command-line options your boot loader passes to the kernel.
2194 bool "UEFI runtime support"
2195 depends on OF && !CPU_BIG_ENDIAN
2196 depends on KERNEL_MODE_NEON
2197 select ARCH_SUPPORTS_ACPI
2200 select EFI_PARAMS_FROM_FDT
2201 select EFI_RUNTIME_WRAPPERS
2203 select EFI_GENERIC_STUB
2204 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2207 This option provides support for runtime services provided
2208 by UEFI firmware (such as non-volatile variables, realtime
2209 clock, and platform reset). A UEFI stub is also provided to
2210 allow the kernel to be booted as an EFI application. This
2211 is only useful on systems that have UEFI firmware.
2214 bool "Enable support for SMBIOS (DMI) tables"
2218 This enables SMBIOS/DMI feature for systems.
2220 This option is only useful on systems that have UEFI firmware.
2221 However, even with this option, the resultant kernel should
2222 continue to boot on existing non-UEFI platforms.
2224 endmenu # "Boot options"
2226 menu "Power management options"
2228 source "kernel/power/Kconfig"
2230 config ARCH_HIBERNATION_POSSIBLE
2234 config ARCH_HIBERNATION_HEADER
2236 depends on HIBERNATION
2238 config ARCH_SUSPEND_POSSIBLE
2241 endmenu # "Power management options"
2243 menu "CPU Power Management"
2245 source "drivers/cpuidle/Kconfig"
2247 source "drivers/cpufreq/Kconfig"
2249 endmenu # "CPU Power Management"
2251 source "drivers/acpi/Kconfig"
2253 source "arch/arm64/kvm/Kconfig"
2256 source "arch/arm64/crypto/Kconfig"