1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_MMAP_PGPROT
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_HAS_FAST_MULTIPLIER
21 select ARCH_HAS_FORTIFY_SOURCE
22 select ARCH_HAS_GCOV_PROFILE_ALL
23 select ARCH_HAS_GIGANTIC_PAGE
25 select ARCH_HAS_KEEPINITRD
26 select ARCH_HAS_MEMBARRIER_SYNC_CORE
27 select ARCH_HAS_PTE_DEVMAP
28 select ARCH_HAS_PTE_SPECIAL
29 select ARCH_HAS_SETUP_DMA_OPS
30 select ARCH_HAS_SET_DIRECT_MAP
31 select ARCH_HAS_SET_MEMORY
32 select ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_HAS_STRICT_MODULE_RWX
34 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35 select ARCH_HAS_SYNC_DMA_FOR_CPU
36 select ARCH_HAS_SYSCALL_WRAPPER
37 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39 select ARCH_HAVE_NMI_SAFE_CMPXCHG
40 select ARCH_INLINE_READ_LOCK if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
42 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
43 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
46 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
47 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
50 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
51 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
54 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
56 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
60 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
61 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
64 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
65 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
66 select ARCH_KEEP_MEMBLOCK
67 select ARCH_USE_CMPXCHG_LOCKREF
68 select ARCH_USE_QUEUED_RWLOCKS
69 select ARCH_USE_QUEUED_SPINLOCKS
70 select ARCH_SUPPORTS_MEMORY_FAILURE
71 select ARCH_SUPPORTS_ATOMIC_RMW
72 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
73 select ARCH_SUPPORTS_NUMA_BALANCING
74 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
75 select ARCH_WANT_FRAME_POINTERS
76 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
77 select ARCH_HAS_UBSAN_SANITIZE_ALL
81 select AUDIT_ARCH_COMPAT_GENERIC
82 select ARM_GIC_V2M if PCI
84 select ARM_GIC_V3_ITS if PCI
86 select BUILDTIME_EXTABLE_SORT
87 select CLONE_BACKWARDS
89 select CPU_PM if (SUSPEND || CPU_IDLE)
91 select DCACHE_WORD_ACCESS
92 select DMA_DIRECT_REMAP
95 select GENERIC_ALLOCATOR
96 select GENERIC_ARCH_TOPOLOGY
97 select GENERIC_CLOCKEVENTS
98 select GENERIC_CLOCKEVENTS_BROADCAST
99 select GENERIC_CPU_AUTOPROBE
100 select GENERIC_CPU_VULNERABILITIES
101 select GENERIC_EARLY_IOREMAP
102 select GENERIC_IDLE_POLL_SETUP
103 select GENERIC_IRQ_MULTI_HANDLER
104 select GENERIC_IRQ_PROBE
105 select GENERIC_IRQ_SHOW
106 select GENERIC_IRQ_SHOW_LEVEL
107 select GENERIC_PCI_IOMAP
108 select GENERIC_SCHED_CLOCK
109 select GENERIC_SMP_IDLE_THREAD
110 select GENERIC_STRNCPY_FROM_USER
111 select GENERIC_STRNLEN_USER
112 select GENERIC_TIME_VSYSCALL
113 select GENERIC_GETTIMEOFDAY
114 select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT)
115 select HANDLE_DOMAIN_IRQ
116 select HARDIRQS_SW_RESEND
118 select HAVE_ACPI_APEI if (ACPI && EFI)
119 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
120 select HAVE_ARCH_AUDITSYSCALL
121 select HAVE_ARCH_BITREVERSE
122 select HAVE_ARCH_HUGE_VMAP
123 select HAVE_ARCH_JUMP_LABEL
124 select HAVE_ARCH_JUMP_LABEL_RELATIVE
125 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
126 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
127 select HAVE_ARCH_KGDB
128 select HAVE_ARCH_MMAP_RND_BITS
129 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
130 select HAVE_ARCH_PREL32_RELOCATIONS
131 select HAVE_ARCH_SECCOMP_FILTER
132 select HAVE_ARCH_STACKLEAK
133 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
134 select HAVE_ARCH_TRACEHOOK
135 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
136 select HAVE_ARCH_VMAP_STACK
137 select HAVE_ARM_SMCCC
139 select HAVE_C_RECORDMCOUNT
140 select HAVE_CMPXCHG_DOUBLE
141 select HAVE_CMPXCHG_LOCAL
142 select HAVE_CONTEXT_TRACKING
143 select HAVE_DEBUG_BUGVERBOSE
144 select HAVE_DEBUG_KMEMLEAK
145 select HAVE_DMA_CONTIGUOUS
146 select HAVE_DYNAMIC_FTRACE
147 select HAVE_EFFICIENT_UNALIGNED_ACCESS
149 select HAVE_FTRACE_MCOUNT_RECORD
150 select HAVE_FUNCTION_TRACER
151 select HAVE_FUNCTION_ERROR_INJECTION
152 select HAVE_FUNCTION_GRAPH_TRACER
153 select HAVE_GCC_PLUGINS
154 select HAVE_HW_BREAKPOINT if PERF_EVENTS
155 select HAVE_IRQ_TIME_ACCOUNTING
156 select HAVE_MEMBLOCK_NODE_MAP if NUMA
158 select HAVE_PATA_PLATFORM
159 select HAVE_PERF_EVENTS
160 select HAVE_PERF_REGS
161 select HAVE_PERF_USER_STACK_DUMP
162 select HAVE_REGS_AND_STACK_ACCESS_API
163 select HAVE_FUNCTION_ARG_ACCESS_API
164 select HAVE_RCU_TABLE_FREE
166 select HAVE_STACKPROTECTOR
167 select HAVE_SYSCALL_TRACEPOINTS
169 select HAVE_KRETPROBES
170 select HAVE_GENERIC_VDSO
171 select IOMMU_DMA if IOMMU_SUPPORT
173 select IRQ_FORCED_THREADING
174 select MODULES_USE_ELF_RELA
175 select NEED_DMA_MAP_STATE
176 select NEED_SG_DMA_LENGTH
178 select OF_EARLY_FLATTREE
179 select PCI_DOMAINS_GENERIC if PCI
180 select PCI_ECAM if (ACPI && PCI)
181 select PCI_SYSCALL if PCI
187 select SYSCTL_EXCEPTION_TRACE
188 select THREAD_INFO_IN_TASK
190 ARM 64-bit (AArch64) Linux support.
198 config ARM64_PAGE_SHIFT
200 default 16 if ARM64_64K_PAGES
201 default 14 if ARM64_16K_PAGES
204 config ARM64_CONT_SHIFT
206 default 5 if ARM64_64K_PAGES
207 default 7 if ARM64_16K_PAGES
210 config ARCH_MMAP_RND_BITS_MIN
211 default 14 if ARM64_64K_PAGES
212 default 16 if ARM64_16K_PAGES
215 # max bits determined by the following formula:
216 # VA_BITS - PAGE_SHIFT - 3
217 config ARCH_MMAP_RND_BITS_MAX
218 default 19 if ARM64_VA_BITS=36
219 default 24 if ARM64_VA_BITS=39
220 default 27 if ARM64_VA_BITS=42
221 default 30 if ARM64_VA_BITS=47
222 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
223 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
224 default 33 if ARM64_VA_BITS=48
225 default 14 if ARM64_64K_PAGES
226 default 16 if ARM64_16K_PAGES
229 config ARCH_MMAP_RND_COMPAT_BITS_MIN
230 default 7 if ARM64_64K_PAGES
231 default 9 if ARM64_16K_PAGES
234 config ARCH_MMAP_RND_COMPAT_BITS_MAX
240 config STACKTRACE_SUPPORT
243 config ILLEGAL_POINTER_VALUE
245 default 0xdead000000000000
247 config LOCKDEP_SUPPORT
250 config TRACE_IRQFLAGS_SUPPORT
257 config GENERIC_BUG_RELATIVE_POINTERS
259 depends on GENERIC_BUG
261 config GENERIC_HWEIGHT
267 config GENERIC_CALIBRATE_DELAY
271 bool "Support DMA32 zone" if EXPERT
274 config ARCH_ENABLE_MEMORY_HOTPLUG
280 config KERNEL_MODE_NEON
283 config FIX_EARLYCON_MEM
286 config PGTABLE_LEVELS
288 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
289 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
290 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
291 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
292 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
293 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
295 config ARCH_SUPPORTS_UPROBES
298 config ARCH_PROC_KCORE_TEXT
301 config KASAN_SHADOW_OFFSET
304 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
305 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
306 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
307 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
308 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
309 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
310 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
311 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
312 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
313 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
314 default 0xffffffffffffffff
316 source "arch/arm64/Kconfig.platforms"
318 menu "Kernel Features"
320 menu "ARM errata workarounds via the alternatives framework"
322 config ARM64_WORKAROUND_CLEAN_CACHE
325 config ARM64_ERRATUM_826319
326 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
328 select ARM64_WORKAROUND_CLEAN_CACHE
330 This option adds an alternative code sequence to work around ARM
331 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
332 AXI master interface and an L2 cache.
334 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
335 and is unable to accept a certain write via this interface, it will
336 not progress on read data presented on the read data channel and the
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
347 config ARM64_ERRATUM_827319
348 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
350 select ARM64_WORKAROUND_CLEAN_CACHE
352 This option adds an alternative code sequence to work around ARM
353 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
354 master interface and an L2 cache.
356 Under certain conditions this erratum can cause a clean line eviction
357 to occur at the same time as another transaction to the same address
358 on the AMBA 5 CHI interface, which can cause data corruption if the
359 interconnect reorders the two transactions.
361 The workaround promotes data cache clean instructions to
362 data cache clean-and-invalidate.
363 Please note that this does not necessarily enable the workaround,
364 as it depends on the alternative framework, which will only patch
365 the kernel if an affected CPU is detected.
369 config ARM64_ERRATUM_824069
370 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
372 select ARM64_WORKAROUND_CLEAN_CACHE
374 This option adds an alternative code sequence to work around ARM
375 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
376 to a coherent interconnect.
378 If a Cortex-A53 processor is executing a store or prefetch for
379 write instruction at the same time as a processor in another
380 cluster is executing a cache maintenance operation to the same
381 address, then this erratum might cause a clean cache line to be
382 incorrectly marked as dirty.
384 The workaround promotes data cache clean instructions to
385 data cache clean-and-invalidate.
386 Please note that this option does not necessarily enable the
387 workaround, as it depends on the alternative framework, which will
388 only patch the kernel if an affected CPU is detected.
392 config ARM64_ERRATUM_819472
393 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
395 select ARM64_WORKAROUND_CLEAN_CACHE
397 This option adds an alternative code sequence to work around ARM
398 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
399 present when it is connected to a coherent interconnect.
401 If the processor is executing a load and store exclusive sequence at
402 the same time as a processor in another cluster is executing a cache
403 maintenance operation to the same address, then this erratum might
404 cause data corruption.
406 The workaround promotes data cache clean instructions to
407 data cache clean-and-invalidate.
408 Please note that this does not necessarily enable the workaround,
409 as it depends on the alternative framework, which will only patch
410 the kernel if an affected CPU is detected.
414 config ARM64_ERRATUM_832075
415 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
418 This option adds an alternative code sequence to work around ARM
419 erratum 832075 on Cortex-A57 parts up to r1p2.
421 Affected Cortex-A57 parts might deadlock when exclusive load/store
422 instructions to Write-Back memory are mixed with Device loads.
424 The workaround is to promote device loads to use Load-Acquire
426 Please note that this does not necessarily enable the workaround,
427 as it depends on the alternative framework, which will only patch
428 the kernel if an affected CPU is detected.
432 config ARM64_ERRATUM_834220
433 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
437 This option adds an alternative code sequence to work around ARM
438 erratum 834220 on Cortex-A57 parts up to r1p2.
440 Affected Cortex-A57 parts might report a Stage 2 translation
441 fault as the result of a Stage 1 fault for load crossing a
442 page boundary when there is a permission or device memory
443 alignment fault at Stage 1 and a translation fault at Stage 2.
445 The workaround is to verify that the Stage 1 translation
446 doesn't generate a fault before handling the Stage 2 fault.
447 Please note that this does not necessarily enable the workaround,
448 as it depends on the alternative framework, which will only patch
449 the kernel if an affected CPU is detected.
453 config ARM64_ERRATUM_845719
454 bool "Cortex-A53: 845719: a load might read incorrect data"
458 This option adds an alternative code sequence to work around ARM
459 erratum 845719 on Cortex-A53 parts up to r0p4.
461 When running a compat (AArch32) userspace on an affected Cortex-A53
462 part, a load at EL0 from a virtual address that matches the bottom 32
463 bits of the virtual address used by a recent load at (AArch64) EL1
464 might return incorrect data.
466 The workaround is to write the contextidr_el1 register on exception
467 return to a 32-bit task.
468 Please note that this does not necessarily enable the workaround,
469 as it depends on the alternative framework, which will only patch
470 the kernel if an affected CPU is detected.
474 config ARM64_ERRATUM_843419
475 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
477 select ARM64_MODULE_PLTS if MODULES
479 This option links the kernel with '--fix-cortex-a53-843419' and
480 enables PLT support to replace certain ADRP instructions, which can
481 cause subsequent memory accesses to use an incorrect address on
482 Cortex-A53 parts up to r0p4.
486 config ARM64_ERRATUM_1024718
487 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
490 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
492 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
493 update of the hardware dirty bit when the DBM/AP bits are updated
494 without a break-before-make. The workaround is to disable the usage
495 of hardware DBM locally on the affected cores. CPUs not affected by
496 this erratum will continue to use the feature.
500 config ARM64_ERRATUM_1418040
501 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
505 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
506 errata 1188873 and 1418040.
508 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
509 cause register corruption when accessing the timer registers
510 from AArch32 userspace.
514 config ARM64_ERRATUM_1165522
515 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
518 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
520 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
521 corrupted TLBs by speculating an AT instruction during a guest
526 config ARM64_ERRATUM_1286807
527 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
529 select ARM64_WORKAROUND_REPEAT_TLBI
531 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
533 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
534 address for a cacheable mapping of a location is being
535 accessed by a core while another core is remapping the virtual
536 address to a new physical page using the recommended
537 break-before-make sequence, then under very rare circumstances
538 TLBI+DSB completes before a read using the translation being
539 invalidated has been observed by other observers. The
540 workaround repeats the TLBI+DSB operation.
544 config ARM64_ERRATUM_1463225
545 bool "Cortex-A76: Software Step might prevent interrupt recognition"
548 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
550 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
551 of a system call instruction (SVC) can prevent recognition of
552 subsequent interrupts when software stepping is disabled in the
553 exception handler of the system call and either kernel debugging
554 is enabled or VHE is in use.
556 Work around the erratum by triggering a dummy step exception
557 when handling a system call from a task that is being stepped
558 in a VHE configuration of the kernel.
562 config CAVIUM_ERRATUM_22375
563 bool "Cavium erratum 22375, 24313"
566 Enable workaround for errata 22375 and 24313.
568 This implements two gicv3-its errata workarounds for ThunderX. Both
569 with a small impact affecting only ITS table allocation.
571 erratum 22375: only alloc 8MB table size
572 erratum 24313: ignore memory access type
574 The fixes are in ITS initialization and basically ignore memory access
575 type and table size provided by the TYPER and BASER registers.
579 config CAVIUM_ERRATUM_23144
580 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
584 ITS SYNC command hang for cross node io and collections/cpu mapping.
588 config CAVIUM_ERRATUM_23154
589 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
592 The gicv3 of ThunderX requires a modified version for
593 reading the IAR status to ensure data synchronization
594 (access to icc_iar1_el1 is not sync'ed before and after).
598 config CAVIUM_ERRATUM_27456
599 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
602 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
603 instructions may cause the icache to become corrupted if it
604 contains data for a non-current ASID. The fix is to
605 invalidate the icache when changing the mm context.
609 config CAVIUM_ERRATUM_30115
610 bool "Cavium erratum 30115: Guest may disable interrupts in host"
613 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
614 1.2, and T83 Pass 1.0, KVM guest execution may disable
615 interrupts in host. Trapping both GICv3 group-0 and group-1
616 accesses sidesteps the issue.
620 config QCOM_FALKOR_ERRATUM_1003
621 bool "Falkor E1003: Incorrect translation due to ASID change"
624 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
625 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
626 in TTBR1_EL1, this situation only occurs in the entry trampoline and
627 then only for entries in the walk cache, since the leaf translation
628 is unchanged. Work around the erratum by invalidating the walk cache
629 entries for the trampoline before entering the kernel proper.
631 config ARM64_WORKAROUND_REPEAT_TLBI
634 config QCOM_FALKOR_ERRATUM_1009
635 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
637 select ARM64_WORKAROUND_REPEAT_TLBI
639 On Falkor v1, the CPU may prematurely complete a DSB following a
640 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
641 one more time to fix the issue.
645 config QCOM_QDF2400_ERRATUM_0065
646 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
649 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
650 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
651 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
655 config SOCIONEXT_SYNQUACER_PREITS
656 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
659 Socionext Synquacer SoCs implement a separate h/w block to generate
660 MSI doorbell writes with non-zero values for the device ID.
664 config HISILICON_ERRATUM_161600802
665 bool "Hip07 161600802: Erroneous redistributor VLPI base"
668 The HiSilicon Hip07 SoC uses the wrong redistributor base
669 when issued ITS commands such as VMOVP and VMAPP, and requires
670 a 128kB offset to be applied to the target address in this commands.
674 config QCOM_FALKOR_ERRATUM_E1041
675 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
678 Falkor CPU may speculatively fetch instructions from an improper
679 memory location when MMU translation is changed from SCTLR_ELn[M]=1
680 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
684 config FUJITSU_ERRATUM_010001
685 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
688 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
689 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
690 accesses may cause undefined fault (Data abort, DFSC=0b111111).
691 This fault occurs under a specific hardware condition when a
692 load/store instruction performs an address translation using:
693 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
694 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
695 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
696 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
698 The workaround is to ensure these bits are clear in TCR_ELx.
699 The workaround only affects the Fujitsu-A64FX.
708 default ARM64_4K_PAGES
710 Page size (translation granule) configuration.
712 config ARM64_4K_PAGES
715 This feature enables 4KB pages support.
717 config ARM64_16K_PAGES
720 The system will use 16KB pages support. AArch32 emulation
721 requires applications compiled with 16K (or a multiple of 16K)
724 config ARM64_64K_PAGES
727 This feature enables 64KB pages support (4KB by default)
728 allowing only two levels of page tables and faster TLB
729 look-up. AArch32 emulation requires applications compiled
730 with 64K aligned segments.
735 prompt "Virtual address space size"
736 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
737 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
738 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
740 Allows choosing one of multiple possible virtual address
741 space sizes. The level of translation table is determined by
742 a combination of page size and virtual address space size.
744 config ARM64_VA_BITS_36
745 bool "36-bit" if EXPERT
746 depends on ARM64_16K_PAGES
748 config ARM64_VA_BITS_39
750 depends on ARM64_4K_PAGES
752 config ARM64_VA_BITS_42
754 depends on ARM64_64K_PAGES
756 config ARM64_VA_BITS_47
758 depends on ARM64_16K_PAGES
760 config ARM64_VA_BITS_48
763 config ARM64_VA_BITS_52
765 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
767 Enable 52-bit virtual addressing for userspace when explicitly
768 requested via a hint to mmap(). The kernel will also use 52-bit
769 virtual addresses for its own mappings (provided HW support for
770 this feature is available, otherwise it reverts to 48-bit).
772 NOTE: Enabling 52-bit virtual addressing in conjunction with
773 ARMv8.3 Pointer Authentication will result in the PAC being
774 reduced from 7 bits to 3 bits, which may have a significant
775 impact on its susceptibility to brute-force attacks.
777 If unsure, select 48-bit virtual addressing instead.
781 config ARM64_FORCE_52BIT
782 bool "Force 52-bit virtual addresses for userspace"
783 depends on ARM64_VA_BITS_52 && EXPERT
785 For systems with 52-bit userspace VAs enabled, the kernel will attempt
786 to maintain compatibility with older software by providing 48-bit VAs
787 unless a hint is supplied to mmap.
789 This configuration option disables the 48-bit compatibility logic, and
790 forces all userspace addresses to be 52-bit on HW that supports it. One
791 should only enable this configuration option for stress testing userspace
792 memory management code. If unsure say N here.
796 default 36 if ARM64_VA_BITS_36
797 default 39 if ARM64_VA_BITS_39
798 default 42 if ARM64_VA_BITS_42
799 default 47 if ARM64_VA_BITS_47
800 default 48 if ARM64_VA_BITS_48
801 default 52 if ARM64_VA_BITS_52
804 prompt "Physical address space size"
805 default ARM64_PA_BITS_48
807 Choose the maximum physical address range that the kernel will
810 config ARM64_PA_BITS_48
813 config ARM64_PA_BITS_52
814 bool "52-bit (ARMv8.2)"
815 depends on ARM64_64K_PAGES
816 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
818 Enable support for a 52-bit physical address space, introduced as
819 part of the ARMv8.2-LPA extension.
821 With this enabled, the kernel will also continue to work on CPUs that
822 do not support ARMv8.2-LPA, but with some added memory overhead (and
823 minor performance overhead).
829 default 48 if ARM64_PA_BITS_48
830 default 52 if ARM64_PA_BITS_52
832 config CPU_BIG_ENDIAN
833 bool "Build big-endian kernel"
835 Say Y if you plan on running a kernel in big-endian mode.
838 bool "Multi-core scheduler support"
840 Multi-core scheduler support improves the CPU scheduler's decision
841 making when dealing with multi-core CPU chips at a cost of slightly
842 increased overhead in some places. If unsure say N here.
845 bool "SMT scheduler support"
847 Improves the CPU scheduler's decision making when dealing with
848 MultiThreading at a cost of slightly increased overhead in some
849 places. If unsure say N here.
852 int "Maximum number of CPUs (2-4096)"
857 bool "Support for hot-pluggable CPUs"
858 select GENERIC_IRQ_MIGRATION
860 Say Y here to experiment with turning CPUs off and on. CPUs
861 can be controlled through /sys/devices/system/cpu.
863 # Common NUMA Features
865 bool "Numa Memory Allocation and Scheduler Support"
866 select ACPI_NUMA if ACPI
869 Enable NUMA (Non Uniform Memory Access) support.
871 The kernel will try to allocate memory used by a CPU on the
872 local memory of the CPU and add some more
873 NUMA awareness to the kernel.
876 int "Maximum NUMA Nodes (as a power of 2)"
879 depends on NEED_MULTIPLE_NODES
881 Specify the maximum number of NUMA Nodes available on the target
882 system. Increases memory reserved to accommodate various tables.
884 config USE_PERCPU_NUMA_NODE_ID
888 config HAVE_SETUP_PER_CPU_AREA
892 config NEED_PER_CPU_EMBED_FIRST_CHUNK
899 source "kernel/Kconfig.hz"
901 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
904 config ARCH_SPARSEMEM_ENABLE
906 select SPARSEMEM_VMEMMAP_ENABLE
908 config ARCH_SPARSEMEM_DEFAULT
909 def_bool ARCH_SPARSEMEM_ENABLE
911 config ARCH_SELECT_MEMORY_MODEL
912 def_bool ARCH_SPARSEMEM_ENABLE
914 config ARCH_FLATMEM_ENABLE
917 config HAVE_ARCH_PFN_VALID
920 config HW_PERF_EVENTS
924 config SYS_SUPPORTS_HUGETLBFS
927 config ARCH_WANT_HUGE_PMD_SHARE
929 config ARCH_HAS_CACHE_LINE_SIZE
932 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
933 def_bool y if PGTABLE_LEVELS > 2
936 bool "Enable seccomp to safely compute untrusted bytecode"
938 This kernel feature is useful for number crunching applications
939 that may need to compute untrusted bytecode during their
940 execution. By using pipes or other transports made available to
941 the process as file descriptors supporting the read/write
942 syscalls, it's possible to isolate those applications in
943 their own address space using seccomp. Once seccomp is
944 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
945 and the task is only allowed to execute a few safe syscalls
946 defined by each seccomp mode.
949 bool "Enable paravirtualization code"
951 This changes the kernel so it can modify itself when it is run
952 under a hypervisor, potentially improving performance significantly
953 over full virtualization.
955 config PARAVIRT_TIME_ACCOUNTING
956 bool "Paravirtual steal time accounting"
959 Select this option to enable fine granularity task steal time
960 accounting. Time spent executing other tasks in parallel with
961 the current vCPU is discounted from the vCPU power. To account for
962 that, there can be a small performance impact.
964 If in doubt, say N here.
967 depends on PM_SLEEP_SMP
969 bool "kexec system call"
971 kexec is a system call that implements the ability to shutdown your
972 current kernel, and to start another kernel. It is like a reboot
973 but it is independent of the system firmware. And like a reboot
974 you can start any kernel with it, not just Linux.
977 bool "kexec file based system call"
980 This is new version of kexec system call. This system call is
981 file based and takes file descriptors as system call argument
982 for kernel and initramfs as opposed to list of segments as
983 accepted by previous system call.
985 config KEXEC_VERIFY_SIG
986 bool "Verify kernel signature during kexec_file_load() syscall"
987 depends on KEXEC_FILE
989 Select this option to verify a signature with loaded kernel
990 image. If configured, any attempt of loading a image without
991 valid signature will fail.
993 In addition to that option, you need to enable signature
994 verification for the corresponding kernel image type being
995 loaded in order for this to work.
997 config KEXEC_IMAGE_VERIFY_SIG
998 bool "Enable Image signature verification support"
1000 depends on KEXEC_VERIFY_SIG
1001 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1003 Enable Image signature verification support.
1005 comment "Support for PE file signature verification disabled"
1006 depends on KEXEC_VERIFY_SIG
1007 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1010 bool "Build kdump crash kernel"
1012 Generate crash dump after being started by kexec. This should
1013 be normally only set in special crash dump kernels which are
1014 loaded in the main kernel with kexec-tools into a specially
1015 reserved region and then later executed after a crash by
1018 For more details see Documentation/admin-guide/kdump/kdump.rst
1025 bool "Xen guest support on ARM64"
1026 depends on ARM64 && OF
1030 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1032 config FORCE_MAX_ZONEORDER
1034 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1035 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1038 The kernel memory allocator divides physically contiguous memory
1039 blocks into "zones", where each zone is a power of two number of
1040 pages. This option selects the largest power of two that the kernel
1041 keeps in the memory allocator. If you need to allocate very large
1042 blocks of physically contiguous memory, then you may need to
1043 increase this value.
1045 This config option is actually maximum order plus one. For example,
1046 a value of 11 means that the largest free memory block is 2^10 pages.
1048 We make sure that we can allocate upto a HugePage size for each configuration.
1050 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1052 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1053 4M allocations matching the default size used by generic code.
1055 config UNMAP_KERNEL_AT_EL0
1056 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1059 Speculation attacks against some high-performance processors can
1060 be used to bypass MMU permission checks and leak kernel data to
1061 userspace. This can be defended against by unmapping the kernel
1062 when running in userspace, mapping it back in on exception entry
1063 via a trampoline page in the vector table.
1067 config HARDEN_BRANCH_PREDICTOR
1068 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1071 Speculation attacks against some high-performance processors rely on
1072 being able to manipulate the branch predictor for a victim context by
1073 executing aliasing branches in the attacker context. Such attacks
1074 can be partially mitigated against by clearing internal branch
1075 predictor state and limiting the prediction logic in some situations.
1077 This config option will take CPU-specific actions to harden the
1078 branch predictor against aliasing attacks and may rely on specific
1079 instruction sequences or control bits being set by the system
1084 config HARDEN_EL2_VECTORS
1085 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1088 Speculation attacks against some high-performance processors can
1089 be used to leak privileged information such as the vector base
1090 register, resulting in a potential defeat of the EL2 layout
1093 This config option will map the vectors to a fixed location,
1094 independent of the EL2 code mapping, so that revealing VBAR_EL2
1095 to an attacker does not give away any extra information. This
1096 only gets enabled on affected CPUs.
1101 bool "Speculative Store Bypass Disable" if EXPERT
1104 This enables mitigation of the bypassing of previous stores
1105 by speculative loads.
1109 config RODATA_FULL_DEFAULT_ENABLED
1110 bool "Apply r/o permissions of VM areas also to their linear aliases"
1113 Apply read-only attributes of VM areas to the linear alias of
1114 the backing pages as well. This prevents code or read-only data
1115 from being modified (inadvertently or intentionally) via another
1116 mapping of the same memory page. This additional enhancement can
1117 be turned off at runtime by passing rodata=[off|on] (and turned on
1118 with rodata=full if this option is set to 'n')
1120 This requires the linear region to be mapped down to pages,
1121 which may adversely affect performance in some cases.
1123 config ARM64_SW_TTBR0_PAN
1124 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1126 Enabling this option prevents the kernel from accessing
1127 user-space memory directly by pointing TTBR0_EL1 to a reserved
1128 zeroed area and reserved ASID. The user access routines
1129 restore the valid TTBR0_EL1 temporarily.
1131 config ARM64_TAGGED_ADDR_ABI
1132 bool "Enable the tagged user addresses syscall ABI"
1135 When this option is enabled, user applications can opt in to a
1136 relaxed ABI via prctl() allowing tagged addresses to be passed
1137 to system calls as pointer arguments. For details, see
1138 Documentation/arm64/tagged-address-abi.txt.
1141 bool "Kernel support for 32-bit EL0"
1142 depends on ARM64_4K_PAGES || EXPERT
1143 select COMPAT_BINFMT_ELF if BINFMT_ELF
1145 select OLD_SIGSUSPEND3
1146 select COMPAT_OLD_SIGACTION
1148 This option enables support for a 32-bit EL0 running under a 64-bit
1149 kernel at EL1. AArch32-specific components such as system calls,
1150 the user helper functions, VFP support and the ptrace interface are
1151 handled appropriately by the kernel.
1153 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1154 that you will only be able to execute AArch32 binaries that were compiled
1155 with page size aligned segments.
1157 If you want to execute 32-bit userspace applications, say Y.
1161 config KUSER_HELPERS
1162 bool "Enable kuser helpers page for 32 bit applications"
1165 Warning: disabling this option may break 32-bit user programs.
1167 Provide kuser helpers to compat tasks. The kernel provides
1168 helper code to userspace in read only form at a fixed location
1169 to allow userspace to be independent of the CPU type fitted to
1170 the system. This permits binaries to be run on ARMv4 through
1171 to ARMv8 without modification.
1173 See Documentation/arm/kernel_user_helpers.rst for details.
1175 However, the fixed address nature of these helpers can be used
1176 by ROP (return orientated programming) authors when creating
1179 If all of the binaries and libraries which run on your platform
1180 are built specifically for your platform, and make no use of
1181 these helpers, then you can turn this option off to hinder
1182 such exploits. However, in that case, if a binary or library
1183 relying on those helpers is run, it will not function correctly.
1185 Say N here only if you are absolutely certain that you do not
1186 need these helpers; otherwise, the safe option is to say Y.
1189 menuconfig ARMV8_DEPRECATED
1190 bool "Emulate deprecated/obsolete ARMv8 instructions"
1193 Legacy software support may require certain instructions
1194 that have been deprecated or obsoleted in the architecture.
1196 Enable this config to enable selective emulation of these
1203 config SWP_EMULATION
1204 bool "Emulate SWP/SWPB instructions"
1206 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1207 they are always undefined. Say Y here to enable software
1208 emulation of these instructions for userspace using LDXR/STXR.
1210 In some older versions of glibc [<=2.8] SWP is used during futex
1211 trylock() operations with the assumption that the code will not
1212 be preempted. This invalid assumption may be more likely to fail
1213 with SWP emulation enabled, leading to deadlock of the user
1216 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1217 on an external transaction monitoring block called a global
1218 monitor to maintain update atomicity. If your system does not
1219 implement a global monitor, this option can cause programs that
1220 perform SWP operations to uncached memory to deadlock.
1224 config CP15_BARRIER_EMULATION
1225 bool "Emulate CP15 Barrier instructions"
1227 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1228 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1229 strongly recommended to use the ISB, DSB, and DMB
1230 instructions instead.
1232 Say Y here to enable software emulation of these
1233 instructions for AArch32 userspace code. When this option is
1234 enabled, CP15 barrier usage is traced which can help
1235 identify software that needs updating.
1239 config SETEND_EMULATION
1240 bool "Emulate SETEND instruction"
1242 The SETEND instruction alters the data-endianness of the
1243 AArch32 EL0, and is deprecated in ARMv8.
1245 Say Y here to enable software emulation of the instruction
1246 for AArch32 userspace code.
1248 Note: All the cpus on the system must have mixed endian support at EL0
1249 for this feature to be enabled. If a new CPU - which doesn't support mixed
1250 endian - is hotplugged in after this feature has been enabled, there could
1251 be unexpected results in the applications.
1258 menu "ARMv8.1 architectural features"
1260 config ARM64_HW_AFDBM
1261 bool "Support for hardware updates of the Access and Dirty page flags"
1264 The ARMv8.1 architecture extensions introduce support for
1265 hardware updates of the access and dirty information in page
1266 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1267 capable processors, accesses to pages with PTE_AF cleared will
1268 set this bit instead of raising an access flag fault.
1269 Similarly, writes to read-only pages with the DBM bit set will
1270 clear the read-only bit (AP[2]) instead of raising a
1273 Kernels built with this configuration option enabled continue
1274 to work on pre-ARMv8.1 hardware and the performance impact is
1275 minimal. If unsure, say Y.
1278 bool "Enable support for Privileged Access Never (PAN)"
1281 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1282 prevents the kernel or hypervisor from accessing user-space (EL0)
1285 Choosing this option will cause any unprotected (not using
1286 copy_to_user et al) memory access to fail with a permission fault.
1288 The feature is detected at runtime, and will remain as a 'nop'
1289 instruction if the cpu does not implement the feature.
1291 config ARM64_LSE_ATOMICS
1292 bool "Atomic instructions"
1293 depends on JUMP_LABEL
1296 As part of the Large System Extensions, ARMv8.1 introduces new
1297 atomic instructions that are designed specifically to scale in
1300 Say Y here to make use of these instructions for the in-kernel
1301 atomic routines. This incurs a small overhead on CPUs that do
1302 not support these instructions and requires the kernel to be
1303 built with binutils >= 2.25 in order for the new instructions
1307 bool "Enable support for Virtualization Host Extensions (VHE)"
1310 Virtualization Host Extensions (VHE) allow the kernel to run
1311 directly at EL2 (instead of EL1) on processors that support
1312 it. This leads to better performance for KVM, as they reduce
1313 the cost of the world switch.
1315 Selecting this option allows the VHE feature to be detected
1316 at runtime, and does not affect processors that do not
1317 implement this feature.
1321 menu "ARMv8.2 architectural features"
1324 bool "Enable support for User Access Override (UAO)"
1327 User Access Override (UAO; part of the ARMv8.2 Extensions)
1328 causes the 'unprivileged' variant of the load/store instructions to
1329 be overridden to be privileged.
1331 This option changes get_user() and friends to use the 'unprivileged'
1332 variant of the load/store instructions. This ensures that user-space
1333 really did have access to the supplied memory. When addr_limit is
1334 set to kernel memory the UAO bit will be set, allowing privileged
1335 access to kernel memory.
1337 Choosing this option will cause copy_to_user() et al to use user-space
1340 The feature is detected at runtime, the kernel will use the
1341 regular load/store instructions if the cpu does not implement the
1345 bool "Enable support for persistent memory"
1346 select ARCH_HAS_PMEM_API
1347 select ARCH_HAS_UACCESS_FLUSHCACHE
1349 Say Y to enable support for the persistent memory API based on the
1350 ARMv8.2 DCPoP feature.
1352 The feature is detected at runtime, and the kernel will use DC CVAC
1353 operations if DC CVAP is not supported (following the behaviour of
1354 DC CVAP itself if the system does not define a point of persistence).
1356 config ARM64_RAS_EXTN
1357 bool "Enable support for RAS CPU Extensions"
1360 CPUs that support the Reliability, Availability and Serviceability
1361 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1362 errors, classify them and report them to software.
1364 On CPUs with these extensions system software can use additional
1365 barriers to determine if faults are pending and read the
1366 classification from a new set of registers.
1368 Selecting this feature will allow the kernel to use these barriers
1369 and access the new registers if the system supports the extension.
1370 Platform RAS features may additionally depend on firmware support.
1373 bool "Enable support for Common Not Private (CNP) translations"
1375 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1377 Common Not Private (CNP) allows translation table entries to
1378 be shared between different PEs in the same inner shareable
1379 domain, so the hardware can use this fact to optimise the
1380 caching of such entries in the TLB.
1382 Selecting this option allows the CNP feature to be detected
1383 at runtime, and does not affect PEs that do not implement
1388 menu "ARMv8.3 architectural features"
1390 config ARM64_PTR_AUTH
1391 bool "Enable support for pointer authentication"
1393 depends on !KVM || ARM64_VHE
1395 Pointer authentication (part of the ARMv8.3 Extensions) provides
1396 instructions for signing and authenticating pointers against secret
1397 keys, which can be used to mitigate Return Oriented Programming (ROP)
1400 This option enables these instructions at EL0 (i.e. for userspace).
1402 Choosing this option will cause the kernel to initialise secret keys
1403 for each process at exec() time, with these keys being
1404 context-switched along with the process.
1406 The feature is detected at runtime. If the feature is not present in
1407 hardware it will not be advertised to userspace/KVM guest nor will it
1408 be enabled. However, KVM guest also require VHE mode and hence
1409 CONFIG_ARM64_VHE=y option to use this feature.
1414 bool "ARM Scalable Vector Extension support"
1416 depends on !KVM || ARM64_VHE
1418 The Scalable Vector Extension (SVE) is an extension to the AArch64
1419 execution state which complements and extends the SIMD functionality
1420 of the base architecture to support much larger vectors and to enable
1421 additional vectorisation opportunities.
1423 To enable use of this extension on CPUs that implement it, say Y.
1425 On CPUs that support the SVE2 extensions, this option will enable
1428 Note that for architectural reasons, firmware _must_ implement SVE
1429 support when running on SVE capable hardware. The required support
1432 * version 1.5 and later of the ARM Trusted Firmware
1433 * the AArch64 boot wrapper since commit 5e1261e08abf
1434 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1436 For other firmware implementations, consult the firmware documentation
1439 If you need the kernel to boot on SVE-capable hardware with broken
1440 firmware, you may need to say N here until you get your firmware
1441 fixed. Otherwise, you may experience firmware panics or lockups when
1442 booting the kernel. If unsure and you are not observing these
1443 symptoms, you should assume that it is safe to say Y.
1445 CPUs that support SVE are architecturally required to support the
1446 Virtualization Host Extensions (VHE), so the kernel makes no
1447 provision for supporting SVE alongside KVM without VHE enabled.
1448 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1449 KVM in the same kernel image.
1451 config ARM64_MODULE_PLTS
1452 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1454 select HAVE_MOD_ARCH_SPECIFIC
1456 Allocate PLTs when loading modules so that jumps and calls whose
1457 targets are too far away for their relative offsets to be encoded
1458 in the instructions themselves can be bounced via veneers in the
1459 module's PLT. This allows modules to be allocated in the generic
1460 vmalloc area after the dedicated module memory area has been
1463 When running with address space randomization (KASLR), the module
1464 region itself may be too far away for ordinary relative jumps and
1465 calls, and so in that case, module PLTs are required and cannot be
1468 Specific errata workaround(s) might also force module PLTs to be
1469 enabled (ARM64_ERRATUM_843419).
1471 config ARM64_PSEUDO_NMI
1472 bool "Support for NMI-like interrupts"
1473 select CONFIG_ARM_GIC_V3
1475 Adds support for mimicking Non-Maskable Interrupts through the use of
1476 GIC interrupt priority. This support requires version 3 or later of
1479 This high priority configuration for interrupts needs to be
1480 explicitly enabled by setting the kernel parameter
1481 "irqchip.gicv3_pseudo_nmi" to 1.
1486 config ARM64_DEBUG_PRIORITY_MASKING
1487 bool "Debug interrupt priority masking"
1489 This adds runtime checks to functions enabling/disabling
1490 interrupts when using priority masking. The additional checks verify
1491 the validity of ICC_PMR_EL1 when calling concerned functions.
1498 select ARCH_HAS_RELR
1500 This builds the kernel as a Position Independent Executable (PIE),
1501 which retains all relocation metadata required to relocate the
1502 kernel binary at runtime to a different virtual address than the
1503 address it was linked at.
1504 Since AArch64 uses the RELA relocation format, this requires a
1505 relocation pass at runtime even if the kernel is loaded at the
1506 same address it was linked at.
1508 config RANDOMIZE_BASE
1509 bool "Randomize the address of the kernel image"
1510 select ARM64_MODULE_PLTS if MODULES
1513 Randomizes the virtual address at which the kernel image is
1514 loaded, as a security feature that deters exploit attempts
1515 relying on knowledge of the location of kernel internals.
1517 It is the bootloader's job to provide entropy, by passing a
1518 random u64 value in /chosen/kaslr-seed at kernel entry.
1520 When booting via the UEFI stub, it will invoke the firmware's
1521 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1522 to the kernel proper. In addition, it will randomise the physical
1523 location of the kernel Image as well.
1527 config RANDOMIZE_MODULE_REGION_FULL
1528 bool "Randomize the module region over a 4 GB range"
1529 depends on RANDOMIZE_BASE
1532 Randomizes the location of the module region inside a 4 GB window
1533 covering the core kernel. This way, it is less likely for modules
1534 to leak information about the location of core kernel data structures
1535 but it does imply that function calls between modules and the core
1536 kernel will need to be resolved via veneers in the module PLT.
1538 When this option is not set, the module region will be randomized over
1539 a limited range that contains the [_stext, _etext] interval of the
1540 core kernel, so branch relocations are always in range.
1542 config CC_HAVE_STACKPROTECTOR_SYSREG
1543 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1545 config STACKPROTECTOR_PER_TASK
1547 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1553 config ARM64_ACPI_PARKING_PROTOCOL
1554 bool "Enable support for the ARM64 ACPI parking protocol"
1557 Enable support for the ARM64 ACPI parking protocol. If disabled
1558 the kernel will not allow booting through the ARM64 ACPI parking
1559 protocol even if the corresponding data is present in the ACPI
1563 string "Default kernel command string"
1566 Provide a set of default command-line options at build time by
1567 entering them here. As a minimum, you should specify the the
1568 root device (e.g. root=/dev/nfs).
1570 config CMDLINE_FORCE
1571 bool "Always use the default kernel command string"
1573 Always use the default kernel command string, even if the boot
1574 loader passes other arguments to the kernel.
1575 This is useful if you cannot or don't want to change the
1576 command-line options your boot loader passes to the kernel.
1582 bool "UEFI runtime support"
1583 depends on OF && !CPU_BIG_ENDIAN
1584 depends on KERNEL_MODE_NEON
1585 select ARCH_SUPPORTS_ACPI
1588 select EFI_PARAMS_FROM_FDT
1589 select EFI_RUNTIME_WRAPPERS
1594 This option provides support for runtime services provided
1595 by UEFI firmware (such as non-volatile variables, realtime
1596 clock, and platform reset). A UEFI stub is also provided to
1597 allow the kernel to be booted as an EFI application. This
1598 is only useful on systems that have UEFI firmware.
1601 bool "Enable support for SMBIOS (DMI) tables"
1605 This enables SMBIOS/DMI feature for systems.
1607 This option is only useful on systems that have UEFI firmware.
1608 However, even with this option, the resultant kernel should
1609 continue to boot on existing non-UEFI platforms.
1613 config SYSVIPC_COMPAT
1615 depends on COMPAT && SYSVIPC
1617 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1619 depends on HUGETLB_PAGE && MIGRATION
1621 menu "Power management options"
1623 source "kernel/power/Kconfig"
1625 config ARCH_HIBERNATION_POSSIBLE
1629 config ARCH_HIBERNATION_HEADER
1631 depends on HIBERNATION
1633 config ARCH_SUSPEND_POSSIBLE
1638 menu "CPU Power Management"
1640 source "drivers/cpuidle/Kconfig"
1642 source "drivers/cpufreq/Kconfig"
1646 source "drivers/firmware/Kconfig"
1648 source "drivers/acpi/Kconfig"
1650 source "arch/arm64/kvm/Kconfig"
1653 source "arch/arm64/crypto/Kconfig"