3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_FORTIFY_SOURCE
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
19 select ARCH_HAS_MEMBARRIER_SYNC_CORE
20 select ARCH_HAS_SET_MEMORY
21 select ARCH_HAS_SG_CHAIN
22 select ARCH_HAS_STRICT_KERNEL_RWX
23 select ARCH_HAS_STRICT_MODULE_RWX
24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
25 select ARCH_HAVE_NMI_SAFE_CMPXCHG
26 select ARCH_INLINE_READ_LOCK if !PREEMPT
27 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
28 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
29 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
30 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
31 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
32 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
33 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
34 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
35 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
36 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
37 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
38 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
39 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
40 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
42 select ARCH_USE_CMPXCHG_LOCKREF
43 select ARCH_USE_QUEUED_RWLOCKS
44 select ARCH_SUPPORTS_MEMORY_FAILURE
45 select ARCH_SUPPORTS_ATOMIC_RMW
46 select ARCH_SUPPORTS_NUMA_BALANCING
47 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
48 select ARCH_WANT_FRAME_POINTERS
49 select ARCH_HAS_UBSAN_SANITIZE_ALL
53 select AUDIT_ARCH_COMPAT_GENERIC
54 select ARM_GIC_V2M if PCI
56 select ARM_GIC_V3_ITS if PCI
58 select BUILDTIME_EXTABLE_SORT
59 select CLONE_BACKWARDS
61 select CPU_PM if (SUSPEND || CPU_IDLE)
62 select DCACHE_WORD_ACCESS
66 select GENERIC_ALLOCATOR
67 select GENERIC_ARCH_TOPOLOGY
68 select GENERIC_CLOCKEVENTS
69 select GENERIC_CLOCKEVENTS_BROADCAST
70 select GENERIC_CPU_AUTOPROBE
71 select GENERIC_EARLY_IOREMAP
72 select GENERIC_IDLE_POLL_SETUP
73 select GENERIC_IRQ_PROBE
74 select GENERIC_IRQ_SHOW
75 select GENERIC_IRQ_SHOW_LEVEL
76 select GENERIC_PCI_IOMAP
77 select GENERIC_SCHED_CLOCK
78 select GENERIC_SMP_IDLE_THREAD
79 select GENERIC_STRNCPY_FROM_USER
80 select GENERIC_STRNLEN_USER
81 select GENERIC_TIME_VSYSCALL
82 select HANDLE_DOMAIN_IRQ
83 select HARDIRQS_SW_RESEND
84 select HAVE_ACPI_APEI if (ACPI && EFI)
85 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
86 select HAVE_ARCH_AUDITSYSCALL
87 select HAVE_ARCH_BITREVERSE
88 select HAVE_ARCH_HUGE_VMAP
89 select HAVE_ARCH_JUMP_LABEL
90 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
92 select HAVE_ARCH_MMAP_RND_BITS
93 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
94 select HAVE_ARCH_SECCOMP_FILTER
95 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
96 select HAVE_ARCH_TRACEHOOK
97 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
98 select HAVE_ARCH_VMAP_STACK
101 select HAVE_C_RECORDMCOUNT
102 select HAVE_CC_STACKPROTECTOR
103 select HAVE_CMPXCHG_DOUBLE
104 select HAVE_CMPXCHG_LOCAL
105 select HAVE_CONTEXT_TRACKING
106 select HAVE_DEBUG_BUGVERBOSE
107 select HAVE_DEBUG_KMEMLEAK
108 select HAVE_DMA_CONTIGUOUS
109 select HAVE_DYNAMIC_FTRACE
110 select HAVE_EFFICIENT_UNALIGNED_ACCESS
111 select HAVE_FTRACE_MCOUNT_RECORD
112 select HAVE_FUNCTION_TRACER
113 select HAVE_FUNCTION_GRAPH_TRACER
114 select HAVE_GCC_PLUGINS
115 select HAVE_GENERIC_DMA_COHERENT
116 select HAVE_HW_BREAKPOINT if PERF_EVENTS
117 select HAVE_IRQ_TIME_ACCOUNTING
119 select HAVE_MEMBLOCK_NODE_MAP if NUMA
121 select HAVE_PATA_PLATFORM
122 select HAVE_PERF_EVENTS
123 select HAVE_PERF_REGS
124 select HAVE_PERF_USER_STACK_DUMP
125 select HAVE_REGS_AND_STACK_ACCESS_API
126 select HAVE_RCU_TABLE_FREE
127 select HAVE_SYSCALL_TRACEPOINTS
129 select HAVE_KRETPROBES
130 select IOMMU_DMA if IOMMU_SUPPORT
132 select IRQ_FORCED_THREADING
133 select MODULES_USE_ELF_RELA
134 select MULTI_IRQ_HANDLER
135 select NEED_SG_DMA_LENGTH
138 select OF_EARLY_FLATTREE
139 select OF_RESERVED_MEM
140 select PCI_ECAM if ACPI
145 select SYSCTL_EXCEPTION_TRACE
146 select THREAD_INFO_IN_TASK
148 ARM 64-bit (AArch64) Linux support.
153 config ARCH_PHYS_ADDR_T_64BIT
159 config ARM64_PAGE_SHIFT
161 default 16 if ARM64_64K_PAGES
162 default 14 if ARM64_16K_PAGES
165 config ARM64_CONT_SHIFT
167 default 5 if ARM64_64K_PAGES
168 default 7 if ARM64_16K_PAGES
171 config ARCH_MMAP_RND_BITS_MIN
172 default 14 if ARM64_64K_PAGES
173 default 16 if ARM64_16K_PAGES
176 # max bits determined by the following formula:
177 # VA_BITS - PAGE_SHIFT - 3
178 config ARCH_MMAP_RND_BITS_MAX
179 default 19 if ARM64_VA_BITS=36
180 default 24 if ARM64_VA_BITS=39
181 default 27 if ARM64_VA_BITS=42
182 default 30 if ARM64_VA_BITS=47
183 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
184 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
185 default 33 if ARM64_VA_BITS=48
186 default 14 if ARM64_64K_PAGES
187 default 16 if ARM64_16K_PAGES
190 config ARCH_MMAP_RND_COMPAT_BITS_MIN
191 default 7 if ARM64_64K_PAGES
192 default 9 if ARM64_16K_PAGES
195 config ARCH_MMAP_RND_COMPAT_BITS_MAX
201 config STACKTRACE_SUPPORT
204 config ILLEGAL_POINTER_VALUE
206 default 0xdead000000000000
208 config LOCKDEP_SUPPORT
211 config TRACE_IRQFLAGS_SUPPORT
214 config RWSEM_XCHGADD_ALGORITHM
221 config GENERIC_BUG_RELATIVE_POINTERS
223 depends on GENERIC_BUG
225 config GENERIC_HWEIGHT
231 config GENERIC_CALIBRATE_DELAY
237 config HAVE_GENERIC_GUP
240 config ARCH_DMA_ADDR_T_64BIT
243 config NEED_DMA_MAP_STATE
252 config KERNEL_MODE_NEON
255 config FIX_EARLYCON_MEM
258 config PGTABLE_LEVELS
260 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
261 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
262 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
263 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
264 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
265 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
267 config ARCH_SUPPORTS_UPROBES
270 config ARCH_PROC_KCORE_TEXT
273 config MULTI_IRQ_HANDLER
276 source "init/Kconfig"
278 source "kernel/Kconfig.freezer"
280 source "arch/arm64/Kconfig.platforms"
287 This feature enables support for PCI bus system. If you say Y
288 here, the kernel will include drivers and infrastructure code
289 to support PCI bus devices.
294 config PCI_DOMAINS_GENERIC
300 source "drivers/pci/Kconfig"
304 menu "Kernel Features"
306 menu "ARM errata workarounds via the alternatives framework"
308 config ARM64_ERRATUM_826319
309 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
312 This option adds an alternative code sequence to work around ARM
313 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
314 AXI master interface and an L2 cache.
316 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
317 and is unable to accept a certain write via this interface, it will
318 not progress on read data presented on the read data channel and the
321 The workaround promotes data cache clean instructions to
322 data cache clean-and-invalidate.
323 Please note that this does not necessarily enable the workaround,
324 as it depends on the alternative framework, which will only patch
325 the kernel if an affected CPU is detected.
329 config ARM64_ERRATUM_827319
330 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
333 This option adds an alternative code sequence to work around ARM
334 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
335 master interface and an L2 cache.
337 Under certain conditions this erratum can cause a clean line eviction
338 to occur at the same time as another transaction to the same address
339 on the AMBA 5 CHI interface, which can cause data corruption if the
340 interconnect reorders the two transactions.
342 The workaround promotes data cache clean instructions to
343 data cache clean-and-invalidate.
344 Please note that this does not necessarily enable the workaround,
345 as it depends on the alternative framework, which will only patch
346 the kernel if an affected CPU is detected.
350 config ARM64_ERRATUM_824069
351 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
354 This option adds an alternative code sequence to work around ARM
355 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
356 to a coherent interconnect.
358 If a Cortex-A53 processor is executing a store or prefetch for
359 write instruction at the same time as a processor in another
360 cluster is executing a cache maintenance operation to the same
361 address, then this erratum might cause a clean cache line to be
362 incorrectly marked as dirty.
364 The workaround promotes data cache clean instructions to
365 data cache clean-and-invalidate.
366 Please note that this option does not necessarily enable the
367 workaround, as it depends on the alternative framework, which will
368 only patch the kernel if an affected CPU is detected.
372 config ARM64_ERRATUM_819472
373 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
376 This option adds an alternative code sequence to work around ARM
377 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
378 present when it is connected to a coherent interconnect.
380 If the processor is executing a load and store exclusive sequence at
381 the same time as a processor in another cluster is executing a cache
382 maintenance operation to the same address, then this erratum might
383 cause data corruption.
385 The workaround promotes data cache clean instructions to
386 data cache clean-and-invalidate.
387 Please note that this does not necessarily enable the workaround,
388 as it depends on the alternative framework, which will only patch
389 the kernel if an affected CPU is detected.
393 config ARM64_ERRATUM_832075
394 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
397 This option adds an alternative code sequence to work around ARM
398 erratum 832075 on Cortex-A57 parts up to r1p2.
400 Affected Cortex-A57 parts might deadlock when exclusive load/store
401 instructions to Write-Back memory are mixed with Device loads.
403 The workaround is to promote device loads to use Load-Acquire
405 Please note that this does not necessarily enable the workaround,
406 as it depends on the alternative framework, which will only patch
407 the kernel if an affected CPU is detected.
411 config ARM64_ERRATUM_834220
412 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
416 This option adds an alternative code sequence to work around ARM
417 erratum 834220 on Cortex-A57 parts up to r1p2.
419 Affected Cortex-A57 parts might report a Stage 2 translation
420 fault as the result of a Stage 1 fault for load crossing a
421 page boundary when there is a permission or device memory
422 alignment fault at Stage 1 and a translation fault at Stage 2.
424 The workaround is to verify that the Stage 1 translation
425 doesn't generate a fault before handling the Stage 2 fault.
426 Please note that this does not necessarily enable the workaround,
427 as it depends on the alternative framework, which will only patch
428 the kernel if an affected CPU is detected.
432 config ARM64_ERRATUM_845719
433 bool "Cortex-A53: 845719: a load might read incorrect data"
437 This option adds an alternative code sequence to work around ARM
438 erratum 845719 on Cortex-A53 parts up to r0p4.
440 When running a compat (AArch32) userspace on an affected Cortex-A53
441 part, a load at EL0 from a virtual address that matches the bottom 32
442 bits of the virtual address used by a recent load at (AArch64) EL1
443 might return incorrect data.
445 The workaround is to write the contextidr_el1 register on exception
446 return to a 32-bit task.
447 Please note that this does not necessarily enable the workaround,
448 as it depends on the alternative framework, which will only patch
449 the kernel if an affected CPU is detected.
453 config ARM64_ERRATUM_843419
454 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
456 select ARM64_MODULE_PLTS if MODULES
458 This option links the kernel with '--fix-cortex-a53-843419' and
459 enables PLT support to replace certain ADRP instructions, which can
460 cause subsequent memory accesses to use an incorrect address on
461 Cortex-A53 parts up to r0p4.
465 config ARM64_ERRATUM_1024718
466 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
469 This option adds work around for Arm Cortex-A55 Erratum 1024718.
471 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
472 update of the hardware dirty bit when the DBM/AP bits are updated
473 without a break-before-make. The work around is to disable the usage
474 of hardware DBM locally on the affected cores. CPUs not affected by
475 erratum will continue to use the feature.
479 config CAVIUM_ERRATUM_22375
480 bool "Cavium erratum 22375, 24313"
483 Enable workaround for erratum 22375, 24313.
485 This implements two gicv3-its errata workarounds for ThunderX. Both
486 with small impact affecting only ITS table allocation.
488 erratum 22375: only alloc 8MB table size
489 erratum 24313: ignore memory access type
491 The fixes are in ITS initialization and basically ignore memory access
492 type and table size provided by the TYPER and BASER registers.
496 config CAVIUM_ERRATUM_23144
497 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
501 ITS SYNC command hang for cross node io and collections/cpu mapping.
505 config CAVIUM_ERRATUM_23154
506 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
509 The gicv3 of ThunderX requires a modified version for
510 reading the IAR status to ensure data synchronization
511 (access to icc_iar1_el1 is not sync'ed before and after).
515 config CAVIUM_ERRATUM_27456
516 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
519 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
520 instructions may cause the icache to become corrupted if it
521 contains data for a non-current ASID. The fix is to
522 invalidate the icache when changing the mm context.
526 config CAVIUM_ERRATUM_30115
527 bool "Cavium erratum 30115: Guest may disable interrupts in host"
530 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
531 1.2, and T83 Pass 1.0, KVM guest execution may disable
532 interrupts in host. Trapping both GICv3 group-0 and group-1
533 accesses sidesteps the issue.
537 config QCOM_FALKOR_ERRATUM_1003
538 bool "Falkor E1003: Incorrect translation due to ASID change"
541 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
542 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
543 in TTBR1_EL1, this situation only occurs in the entry trampoline and
544 then only for entries in the walk cache, since the leaf translation
545 is unchanged. Work around the erratum by invalidating the walk cache
546 entries for the trampoline before entering the kernel proper.
548 config QCOM_FALKOR_ERRATUM_1009
549 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
552 On Falkor v1, the CPU may prematurely complete a DSB following a
553 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
554 one more time to fix the issue.
558 config QCOM_QDF2400_ERRATUM_0065
559 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
562 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
563 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
564 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
568 config SOCIONEXT_SYNQUACER_PREITS
569 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
572 Socionext Synquacer SoCs implement a separate h/w block to generate
573 MSI doorbell writes with non-zero values for the device ID.
577 config HISILICON_ERRATUM_161600802
578 bool "Hip07 161600802: Erroneous redistributor VLPI base"
581 The HiSilicon Hip07 SoC usees the wrong redistributor base
582 when issued ITS commands such as VMOVP and VMAPP, and requires
583 a 128kB offset to be applied to the target address in this commands.
587 config QCOM_FALKOR_ERRATUM_E1041
588 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
591 Falkor CPU may speculatively fetch instructions from an improper
592 memory location when MMU translation is changed from SCTLR_ELn[M]=1
593 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
602 default ARM64_4K_PAGES
604 Page size (translation granule) configuration.
606 config ARM64_4K_PAGES
609 This feature enables 4KB pages support.
611 config ARM64_16K_PAGES
614 The system will use 16KB pages support. AArch32 emulation
615 requires applications compiled with 16K (or a multiple of 16K)
618 config ARM64_64K_PAGES
621 This feature enables 64KB pages support (4KB by default)
622 allowing only two levels of page tables and faster TLB
623 look-up. AArch32 emulation requires applications compiled
624 with 64K aligned segments.
629 prompt "Virtual address space size"
630 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
631 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
632 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
634 Allows choosing one of multiple possible virtual address
635 space sizes. The level of translation table is determined by
636 a combination of page size and virtual address space size.
638 config ARM64_VA_BITS_36
639 bool "36-bit" if EXPERT
640 depends on ARM64_16K_PAGES
642 config ARM64_VA_BITS_39
644 depends on ARM64_4K_PAGES
646 config ARM64_VA_BITS_42
648 depends on ARM64_64K_PAGES
650 config ARM64_VA_BITS_47
652 depends on ARM64_16K_PAGES
654 config ARM64_VA_BITS_48
661 default 36 if ARM64_VA_BITS_36
662 default 39 if ARM64_VA_BITS_39
663 default 42 if ARM64_VA_BITS_42
664 default 47 if ARM64_VA_BITS_47
665 default 48 if ARM64_VA_BITS_48
668 prompt "Physical address space size"
669 default ARM64_PA_BITS_48
671 Choose the maximum physical address range that the kernel will
674 config ARM64_PA_BITS_48
677 config ARM64_PA_BITS_52
678 bool "52-bit (ARMv8.2)"
679 depends on ARM64_64K_PAGES
680 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
682 Enable support for a 52-bit physical address space, introduced as
683 part of the ARMv8.2-LPA extension.
685 With this enabled, the kernel will also continue to work on CPUs that
686 do not support ARMv8.2-LPA, but with some added memory overhead (and
687 minor performance overhead).
693 default 48 if ARM64_PA_BITS_48
694 default 52 if ARM64_PA_BITS_52
696 config CPU_BIG_ENDIAN
697 bool "Build big-endian kernel"
699 Say Y if you plan on running a kernel in big-endian mode.
702 bool "Multi-core scheduler support"
704 Multi-core scheduler support improves the CPU scheduler's decision
705 making when dealing with multi-core CPU chips at a cost of slightly
706 increased overhead in some places. If unsure say N here.
709 bool "SMT scheduler support"
711 Improves the CPU scheduler's decision making when dealing with
712 MultiThreading at a cost of slightly increased overhead in some
713 places. If unsure say N here.
716 int "Maximum number of CPUs (2-4096)"
718 # These have to remain sorted largest to smallest
722 bool "Support for hot-pluggable CPUs"
723 select GENERIC_IRQ_MIGRATION
725 Say Y here to experiment with turning CPUs off and on. CPUs
726 can be controlled through /sys/devices/system/cpu.
728 # Common NUMA Features
730 bool "Numa Memory Allocation and Scheduler Support"
731 select ACPI_NUMA if ACPI
734 Enable NUMA (Non Uniform Memory Access) support.
736 The kernel will try to allocate memory used by a CPU on the
737 local memory of the CPU and add some more
738 NUMA awareness to the kernel.
741 int "Maximum NUMA Nodes (as a power of 2)"
744 depends on NEED_MULTIPLE_NODES
746 Specify the maximum number of NUMA Nodes available on the target
747 system. Increases memory reserved to accommodate various tables.
749 config USE_PERCPU_NUMA_NODE_ID
753 config HAVE_SETUP_PER_CPU_AREA
757 config NEED_PER_CPU_EMBED_FIRST_CHUNK
765 source kernel/Kconfig.preempt
766 source kernel/Kconfig.hz
768 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
771 config ARCH_HAS_HOLES_MEMORYMODEL
772 def_bool y if SPARSEMEM
774 config ARCH_SPARSEMEM_ENABLE
776 select SPARSEMEM_VMEMMAP_ENABLE
778 config ARCH_SPARSEMEM_DEFAULT
779 def_bool ARCH_SPARSEMEM_ENABLE
781 config ARCH_SELECT_MEMORY_MODEL
782 def_bool ARCH_SPARSEMEM_ENABLE
784 config HAVE_ARCH_PFN_VALID
785 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
787 config HW_PERF_EVENTS
791 config SYS_SUPPORTS_HUGETLBFS
794 config ARCH_WANT_HUGE_PMD_SHARE
795 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
797 config ARCH_HAS_CACHE_LINE_SIZE
803 bool "Enable seccomp to safely compute untrusted bytecode"
805 This kernel feature is useful for number crunching applications
806 that may need to compute untrusted bytecode during their
807 execution. By using pipes or other transports made available to
808 the process as file descriptors supporting the read/write
809 syscalls, it's possible to isolate those applications in
810 their own address space using seccomp. Once seccomp is
811 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
812 and the task is only allowed to execute a few safe syscalls
813 defined by each seccomp mode.
816 bool "Enable paravirtualization code"
818 This changes the kernel so it can modify itself when it is run
819 under a hypervisor, potentially improving performance significantly
820 over full virtualization.
822 config PARAVIRT_TIME_ACCOUNTING
823 bool "Paravirtual steal time accounting"
827 Select this option to enable fine granularity task steal time
828 accounting. Time spent executing other tasks in parallel with
829 the current vCPU is discounted from the vCPU power. To account for
830 that, there can be a small performance impact.
832 If in doubt, say N here.
835 depends on PM_SLEEP_SMP
837 bool "kexec system call"
839 kexec is a system call that implements the ability to shutdown your
840 current kernel, and to start another kernel. It is like a reboot
841 but it is independent of the system firmware. And like a reboot
842 you can start any kernel with it, not just Linux.
845 bool "Build kdump crash kernel"
847 Generate crash dump after being started by kexec. This should
848 be normally only set in special crash dump kernels which are
849 loaded in the main kernel with kexec-tools into a specially
850 reserved region and then later executed after a crash by
853 For more details see Documentation/kdump/kdump.txt
860 bool "Xen guest support on ARM64"
861 depends on ARM64 && OF
865 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
867 config FORCE_MAX_ZONEORDER
869 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
870 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
873 The kernel memory allocator divides physically contiguous memory
874 blocks into "zones", where each zone is a power of two number of
875 pages. This option selects the largest power of two that the kernel
876 keeps in the memory allocator. If you need to allocate very large
877 blocks of physically contiguous memory, then you may need to
880 This config option is actually maximum order plus one. For example,
881 a value of 11 means that the largest free memory block is 2^10 pages.
883 We make sure that we can allocate upto a HugePage size for each configuration.
885 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
887 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
888 4M allocations matching the default size used by generic code.
890 config UNMAP_KERNEL_AT_EL0
891 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
894 Speculation attacks against some high-performance processors can
895 be used to bypass MMU permission checks and leak kernel data to
896 userspace. This can be defended against by unmapping the kernel
897 when running in userspace, mapping it back in on exception entry
898 via a trampoline page in the vector table.
902 config HARDEN_BRANCH_PREDICTOR
903 bool "Harden the branch predictor against aliasing attacks" if EXPERT
906 Speculation attacks against some high-performance processors rely on
907 being able to manipulate the branch predictor for a victim context by
908 executing aliasing branches in the attacker context. Such attacks
909 can be partially mitigated against by clearing internal branch
910 predictor state and limiting the prediction logic in some situations.
912 This config option will take CPU-specific actions to harden the
913 branch predictor against aliasing attacks and may rely on specific
914 instruction sequences or control bits being set by the system
919 config HARDEN_EL2_VECTORS
920 bool "Harden EL2 vector mapping against system register leak" if EXPERT
923 Speculation attacks against some high-performance processors can
924 be used to leak privileged information such as the vector base
925 register, resulting in a potential defeat of the EL2 layout
928 This config option will map the vectors to a fixed location,
929 independent of the EL2 code mapping, so that revealing VBAR_EL2
930 to an attacker does not give away any extra information. This
931 only gets enabled on affected CPUs.
935 menuconfig ARMV8_DEPRECATED
936 bool "Emulate deprecated/obsolete ARMv8 instructions"
940 Legacy software support may require certain instructions
941 that have been deprecated or obsoleted in the architecture.
943 Enable this config to enable selective emulation of these
951 bool "Emulate SWP/SWPB instructions"
953 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
954 they are always undefined. Say Y here to enable software
955 emulation of these instructions for userspace using LDXR/STXR.
957 In some older versions of glibc [<=2.8] SWP is used during futex
958 trylock() operations with the assumption that the code will not
959 be preempted. This invalid assumption may be more likely to fail
960 with SWP emulation enabled, leading to deadlock of the user
963 NOTE: when accessing uncached shared regions, LDXR/STXR rely
964 on an external transaction monitoring block called a global
965 monitor to maintain update atomicity. If your system does not
966 implement a global monitor, this option can cause programs that
967 perform SWP operations to uncached memory to deadlock.
971 config CP15_BARRIER_EMULATION
972 bool "Emulate CP15 Barrier instructions"
974 The CP15 barrier instructions - CP15ISB, CP15DSB, and
975 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
976 strongly recommended to use the ISB, DSB, and DMB
977 instructions instead.
979 Say Y here to enable software emulation of these
980 instructions for AArch32 userspace code. When this option is
981 enabled, CP15 barrier usage is traced which can help
982 identify software that needs updating.
986 config SETEND_EMULATION
987 bool "Emulate SETEND instruction"
989 The SETEND instruction alters the data-endianness of the
990 AArch32 EL0, and is deprecated in ARMv8.
992 Say Y here to enable software emulation of the instruction
993 for AArch32 userspace code.
995 Note: All the cpus on the system must have mixed endian support at EL0
996 for this feature to be enabled. If a new CPU - which doesn't support mixed
997 endian - is hotplugged in after this feature has been enabled, there could
998 be unexpected results in the applications.
1003 config ARM64_SW_TTBR0_PAN
1004 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1006 Enabling this option prevents the kernel from accessing
1007 user-space memory directly by pointing TTBR0_EL1 to a reserved
1008 zeroed area and reserved ASID. The user access routines
1009 restore the valid TTBR0_EL1 temporarily.
1011 menu "ARMv8.1 architectural features"
1013 config ARM64_HW_AFDBM
1014 bool "Support for hardware updates of the Access and Dirty page flags"
1017 The ARMv8.1 architecture extensions introduce support for
1018 hardware updates of the access and dirty information in page
1019 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1020 capable processors, accesses to pages with PTE_AF cleared will
1021 set this bit instead of raising an access flag fault.
1022 Similarly, writes to read-only pages with the DBM bit set will
1023 clear the read-only bit (AP[2]) instead of raising a
1026 Kernels built with this configuration option enabled continue
1027 to work on pre-ARMv8.1 hardware and the performance impact is
1028 minimal. If unsure, say Y.
1031 bool "Enable support for Privileged Access Never (PAN)"
1034 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1035 prevents the kernel or hypervisor from accessing user-space (EL0)
1038 Choosing this option will cause any unprotected (not using
1039 copy_to_user et al) memory access to fail with a permission fault.
1041 The feature is detected at runtime, and will remain as a 'nop'
1042 instruction if the cpu does not implement the feature.
1044 config ARM64_LSE_ATOMICS
1045 bool "Atomic instructions"
1047 As part of the Large System Extensions, ARMv8.1 introduces new
1048 atomic instructions that are designed specifically to scale in
1051 Say Y here to make use of these instructions for the in-kernel
1052 atomic routines. This incurs a small overhead on CPUs that do
1053 not support these instructions and requires the kernel to be
1054 built with binutils >= 2.25.
1057 bool "Enable support for Virtualization Host Extensions (VHE)"
1060 Virtualization Host Extensions (VHE) allow the kernel to run
1061 directly at EL2 (instead of EL1) on processors that support
1062 it. This leads to better performance for KVM, as they reduce
1063 the cost of the world switch.
1065 Selecting this option allows the VHE feature to be detected
1066 at runtime, and does not affect processors that do not
1067 implement this feature.
1071 menu "ARMv8.2 architectural features"
1074 bool "Enable support for User Access Override (UAO)"
1077 User Access Override (UAO; part of the ARMv8.2 Extensions)
1078 causes the 'unprivileged' variant of the load/store instructions to
1079 be overridden to be privileged.
1081 This option changes get_user() and friends to use the 'unprivileged'
1082 variant of the load/store instructions. This ensures that user-space
1083 really did have access to the supplied memory. When addr_limit is
1084 set to kernel memory the UAO bit will be set, allowing privileged
1085 access to kernel memory.
1087 Choosing this option will cause copy_to_user() et al to use user-space
1090 The feature is detected at runtime, the kernel will use the
1091 regular load/store instructions if the cpu does not implement the
1095 bool "Enable support for persistent memory"
1096 select ARCH_HAS_PMEM_API
1097 select ARCH_HAS_UACCESS_FLUSHCACHE
1099 Say Y to enable support for the persistent memory API based on the
1100 ARMv8.2 DCPoP feature.
1102 The feature is detected at runtime, and the kernel will use DC CVAC
1103 operations if DC CVAP is not supported (following the behaviour of
1104 DC CVAP itself if the system does not define a point of persistence).
1106 config ARM64_RAS_EXTN
1107 bool "Enable support for RAS CPU Extensions"
1110 CPUs that support the Reliability, Availability and Serviceability
1111 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1112 errors, classify them and report them to software.
1114 On CPUs with these extensions system software can use additional
1115 barriers to determine if faults are pending and read the
1116 classification from a new set of registers.
1118 Selecting this feature will allow the kernel to use these barriers
1119 and access the new registers if the system supports the extension.
1120 Platform RAS features may additionally depend on firmware support.
1125 bool "ARM Scalable Vector Extension support"
1128 The Scalable Vector Extension (SVE) is an extension to the AArch64
1129 execution state which complements and extends the SIMD functionality
1130 of the base architecture to support much larger vectors and to enable
1131 additional vectorisation opportunities.
1133 To enable use of this extension on CPUs that implement it, say Y.
1135 Note that for architectural reasons, firmware _must_ implement SVE
1136 support when running on SVE capable hardware. The required support
1139 * version 1.5 and later of the ARM Trusted Firmware
1140 * the AArch64 boot wrapper since commit 5e1261e08abf
1141 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1143 For other firmware implementations, consult the firmware documentation
1146 If you need the kernel to boot on SVE-capable hardware with broken
1147 firmware, you may need to say N here until you get your firmware
1148 fixed. Otherwise, you may experience firmware panics or lockups when
1149 booting the kernel. If unsure and you are not observing these
1150 symptoms, you should assume that it is safe to say Y.
1152 config ARM64_MODULE_PLTS
1154 select HAVE_MOD_ARCH_SPECIFIC
1159 This builds the kernel as a Position Independent Executable (PIE),
1160 which retains all relocation metadata required to relocate the
1161 kernel binary at runtime to a different virtual address than the
1162 address it was linked at.
1163 Since AArch64 uses the RELA relocation format, this requires a
1164 relocation pass at runtime even if the kernel is loaded at the
1165 same address it was linked at.
1167 config RANDOMIZE_BASE
1168 bool "Randomize the address of the kernel image"
1169 select ARM64_MODULE_PLTS if MODULES
1172 Randomizes the virtual address at which the kernel image is
1173 loaded, as a security feature that deters exploit attempts
1174 relying on knowledge of the location of kernel internals.
1176 It is the bootloader's job to provide entropy, by passing a
1177 random u64 value in /chosen/kaslr-seed at kernel entry.
1179 When booting via the UEFI stub, it will invoke the firmware's
1180 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1181 to the kernel proper. In addition, it will randomise the physical
1182 location of the kernel Image as well.
1186 config RANDOMIZE_MODULE_REGION_FULL
1187 bool "Randomize the module region over a 4 GB range"
1188 depends on RANDOMIZE_BASE
1191 Randomizes the location of the module region inside a 4 GB window
1192 covering the core kernel. This way, it is less likely for modules
1193 to leak information about the location of core kernel data structures
1194 but it does imply that function calls between modules and the core
1195 kernel will need to be resolved via veneers in the module PLT.
1197 When this option is not set, the module region will be randomized over
1198 a limited range that contains the [_stext, _etext] interval of the
1199 core kernel, so branch relocations are always in range.
1205 config ARM64_ACPI_PARKING_PROTOCOL
1206 bool "Enable support for the ARM64 ACPI parking protocol"
1209 Enable support for the ARM64 ACPI parking protocol. If disabled
1210 the kernel will not allow booting through the ARM64 ACPI parking
1211 protocol even if the corresponding data is present in the ACPI
1215 string "Default kernel command string"
1218 Provide a set of default command-line options at build time by
1219 entering them here. As a minimum, you should specify the the
1220 root device (e.g. root=/dev/nfs).
1222 config CMDLINE_FORCE
1223 bool "Always use the default kernel command string"
1225 Always use the default kernel command string, even if the boot
1226 loader passes other arguments to the kernel.
1227 This is useful if you cannot or don't want to change the
1228 command-line options your boot loader passes to the kernel.
1234 bool "UEFI runtime support"
1235 depends on OF && !CPU_BIG_ENDIAN
1236 depends on KERNEL_MODE_NEON
1239 select EFI_PARAMS_FROM_FDT
1240 select EFI_RUNTIME_WRAPPERS
1245 This option provides support for runtime services provided
1246 by UEFI firmware (such as non-volatile variables, realtime
1247 clock, and platform reset). A UEFI stub is also provided to
1248 allow the kernel to be booted as an EFI application. This
1249 is only useful on systems that have UEFI firmware.
1252 bool "Enable support for SMBIOS (DMI) tables"
1256 This enables SMBIOS/DMI feature for systems.
1258 This option is only useful on systems that have UEFI firmware.
1259 However, even with this option, the resultant kernel should
1260 continue to boot on existing non-UEFI platforms.
1264 menu "Userspace binary formats"
1266 source "fs/Kconfig.binfmt"
1269 bool "Kernel support for 32-bit EL0"
1270 depends on ARM64_4K_PAGES || EXPERT
1271 select COMPAT_BINFMT_ELF if BINFMT_ELF
1273 select OLD_SIGSUSPEND3
1274 select COMPAT_OLD_SIGACTION
1276 This option enables support for a 32-bit EL0 running under a 64-bit
1277 kernel at EL1. AArch32-specific components such as system calls,
1278 the user helper functions, VFP support and the ptrace interface are
1279 handled appropriately by the kernel.
1281 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1282 that you will only be able to execute AArch32 binaries that were compiled
1283 with page size aligned segments.
1285 If you want to execute 32-bit userspace applications, say Y.
1287 config SYSVIPC_COMPAT
1289 depends on COMPAT && SYSVIPC
1293 menu "Power management options"
1295 source "kernel/power/Kconfig"
1297 config ARCH_HIBERNATION_POSSIBLE
1301 config ARCH_HIBERNATION_HEADER
1303 depends on HIBERNATION
1305 config ARCH_SUSPEND_POSSIBLE
1310 menu "CPU Power Management"
1312 source "drivers/cpuidle/Kconfig"
1314 source "drivers/cpufreq/Kconfig"
1318 source "net/Kconfig"
1320 source "drivers/Kconfig"
1322 source "drivers/firmware/Kconfig"
1324 source "drivers/acpi/Kconfig"
1328 source "arch/arm64/kvm/Kconfig"
1330 source "arch/arm64/Kconfig.debug"
1332 source "security/Kconfig"
1334 source "crypto/Kconfig"
1336 source "arch/arm64/crypto/Kconfig"
1339 source "lib/Kconfig"