1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_EXTRA_PHDRS
14 select ARCH_BINFMT_ELF_STATE
15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
17 select ARCH_ENABLE_MEMORY_HOTPLUG
18 select ARCH_ENABLE_MEMORY_HOTREMOVE
19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
21 select ARCH_HAS_CACHE_LINE_SIZE
22 select ARCH_HAS_CURRENT_STACK_POINTER
23 select ARCH_HAS_DEBUG_VIRTUAL
24 select ARCH_HAS_DEBUG_VM_PGTABLE
25 select ARCH_HAS_DMA_PREP_COHERENT
26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
27 select ARCH_HAS_FAST_MULTIPLIER
28 select ARCH_HAS_FORTIFY_SOURCE
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_HAS_GIGANTIC_PAGE
32 select ARCH_HAS_KEEPINITRD
33 select ARCH_HAS_MEMBARRIER_SYNC_CORE
34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
35 select ARCH_HAS_PTE_DEVMAP
36 select ARCH_HAS_PTE_SPECIAL
37 select ARCH_HAS_SETUP_DMA_OPS
38 select ARCH_HAS_SET_DIRECT_MAP
39 select ARCH_HAS_SET_MEMORY
41 select ARCH_HAS_STRICT_KERNEL_RWX
42 select ARCH_HAS_STRICT_MODULE_RWX
43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
44 select ARCH_HAS_SYNC_DMA_FOR_CPU
45 select ARCH_HAS_SYSCALL_WRAPPER
46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
48 select ARCH_HAS_ZONE_DMA_SET if EXPERT
49 select ARCH_HAVE_ELF_PROT
50 select ARCH_HAVE_NMI_SAFE_CMPXCHG
51 select ARCH_HAVE_TRACE_MMIO_ACCESS
52 select ARCH_INLINE_READ_LOCK if !PREEMPTION
53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
78 select ARCH_KEEP_MEMBLOCK
79 select ARCH_USE_CMPXCHG_LOCKREF
80 select ARCH_USE_GNU_PROPERTY
81 select ARCH_USE_MEMTEST
82 select ARCH_USE_QUEUED_RWLOCKS
83 select ARCH_USE_QUEUED_SPINLOCKS
84 select ARCH_USE_SYM_ANNOTATIONS
85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
86 select ARCH_SUPPORTS_HUGETLBFS
87 select ARCH_SUPPORTS_MEMORY_FAILURE
88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
90 select ARCH_SUPPORTS_LTO_CLANG_THIN
91 select ARCH_SUPPORTS_CFI_CLANG
92 select ARCH_SUPPORTS_ATOMIC_RMW
93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
94 select ARCH_SUPPORTS_NUMA_BALANCING
95 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
96 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
97 select ARCH_WANT_DEFAULT_BPF_JIT
98 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
99 select ARCH_WANT_FRAME_POINTERS
100 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
101 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
102 select ARCH_WANT_LD_ORPHAN_WARN
103 select ARCH_WANTS_NO_INSTR
104 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
105 select ARCH_HAS_UBSAN_SANITIZE_ALL
107 select ARM_ARCH_TIMER
109 select AUDIT_ARCH_COMPAT_GENERIC
110 select ARM_GIC_V2M if PCI
112 select ARM_GIC_V3_ITS if PCI
114 select BUILDTIME_TABLE_SORT
115 select CLONE_BACKWARDS
117 select CPU_PM if (SUSPEND || CPU_IDLE)
119 select DCACHE_WORD_ACCESS
120 select DMA_DIRECT_REMAP
123 select GENERIC_ALLOCATOR
124 select GENERIC_ARCH_TOPOLOGY
125 select GENERIC_CLOCKEVENTS_BROADCAST
126 select GENERIC_CPU_AUTOPROBE
127 select GENERIC_CPU_VULNERABILITIES
128 select GENERIC_EARLY_IOREMAP
129 select GENERIC_IDLE_POLL_SETUP
130 select GENERIC_IOREMAP
131 select GENERIC_IRQ_IPI
132 select GENERIC_IRQ_PROBE
133 select GENERIC_IRQ_SHOW
134 select GENERIC_IRQ_SHOW_LEVEL
135 select GENERIC_LIB_DEVMEM_IS_ALLOWED
136 select GENERIC_PCI_IOMAP
137 select GENERIC_PTDUMP
138 select GENERIC_SCHED_CLOCK
139 select GENERIC_SMP_IDLE_THREAD
140 select GENERIC_TIME_VSYSCALL
141 select GENERIC_GETTIMEOFDAY
142 select GENERIC_VDSO_TIME_NS
143 select HARDIRQS_SW_RESEND
147 select HAVE_ACPI_APEI if (ACPI && EFI)
148 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
149 select HAVE_ARCH_AUDITSYSCALL
150 select HAVE_ARCH_BITREVERSE
151 select HAVE_ARCH_COMPILER_H
152 select HAVE_ARCH_HUGE_VMALLOC
153 select HAVE_ARCH_HUGE_VMAP
154 select HAVE_ARCH_JUMP_LABEL
155 select HAVE_ARCH_JUMP_LABEL_RELATIVE
156 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
157 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
158 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
159 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
160 # Some instrumentation may be unsound, hence EXPERT
161 select HAVE_ARCH_KCSAN if EXPERT
162 select HAVE_ARCH_KFENCE
163 select HAVE_ARCH_KGDB
164 select HAVE_ARCH_MMAP_RND_BITS
165 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
166 select HAVE_ARCH_PREL32_RELOCATIONS
167 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
168 select HAVE_ARCH_SECCOMP_FILTER
169 select HAVE_ARCH_STACKLEAK
170 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
171 select HAVE_ARCH_TRACEHOOK
172 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
173 select HAVE_ARCH_VMAP_STACK
174 select HAVE_ARM_SMCCC
175 select HAVE_ASM_MODVERSIONS
177 select HAVE_C_RECORDMCOUNT
178 select HAVE_CMPXCHG_DOUBLE
179 select HAVE_CMPXCHG_LOCAL
180 select HAVE_CONTEXT_TRACKING_USER
181 select HAVE_DEBUG_KMEMLEAK
182 select HAVE_DMA_CONTIGUOUS
183 select HAVE_DYNAMIC_FTRACE
184 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
185 if DYNAMIC_FTRACE_WITH_REGS
186 select HAVE_EFFICIENT_UNALIGNED_ACCESS
188 select HAVE_FTRACE_MCOUNT_RECORD
189 select HAVE_FUNCTION_TRACER
190 select HAVE_FUNCTION_ERROR_INJECTION
191 select HAVE_FUNCTION_GRAPH_TRACER
192 select HAVE_GCC_PLUGINS
193 select HAVE_HW_BREAKPOINT if PERF_EVENTS
194 select HAVE_IOREMAP_PROT
195 select HAVE_IRQ_TIME_ACCOUNTING
198 select HAVE_PERF_EVENTS
199 select HAVE_PERF_REGS
200 select HAVE_PERF_USER_STACK_DUMP
201 select HAVE_PREEMPT_DYNAMIC_KEY
202 select HAVE_REGS_AND_STACK_ACCESS_API
203 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
204 select HAVE_FUNCTION_ARG_ACCESS_API
205 select MMU_GATHER_RCU_TABLE_FREE
207 select HAVE_STACKPROTECTOR
208 select HAVE_SYSCALL_TRACEPOINTS
210 select HAVE_KRETPROBES
211 select HAVE_GENERIC_VDSO
212 select IOMMU_DMA if IOMMU_SUPPORT
214 select IRQ_FORCED_THREADING
215 select KASAN_VMALLOC if KASAN
216 select MODULES_USE_ELF_RELA
217 select NEED_DMA_MAP_STATE
218 select NEED_SG_DMA_LENGTH
220 select OF_EARLY_FLATTREE
221 select PCI_DOMAINS_GENERIC if PCI
222 select PCI_ECAM if (ACPI && PCI)
223 select PCI_SYSCALL if PCI
228 select SYSCTL_EXCEPTION_TRACE
229 select THREAD_INFO_IN_TASK
230 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
231 select TRACE_IRQFLAGS_SUPPORT
232 select TRACE_IRQFLAGS_NMI_SUPPORT
233 select HAVE_SOFTIRQ_ON_OWN_STACK
235 ARM 64-bit (AArch64) Linux support.
237 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
239 # https://github.com/ClangBuiltLinux/linux/issues/1507
240 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
241 select HAVE_DYNAMIC_FTRACE_WITH_REGS
243 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
245 depends on $(cc-option,-fpatchable-function-entry=2)
246 select HAVE_DYNAMIC_FTRACE_WITH_REGS
254 config ARM64_PAGE_SHIFT
256 default 16 if ARM64_64K_PAGES
257 default 14 if ARM64_16K_PAGES
260 config ARM64_CONT_PTE_SHIFT
262 default 5 if ARM64_64K_PAGES
263 default 7 if ARM64_16K_PAGES
266 config ARM64_CONT_PMD_SHIFT
268 default 5 if ARM64_64K_PAGES
269 default 5 if ARM64_16K_PAGES
272 config ARCH_MMAP_RND_BITS_MIN
273 default 14 if ARM64_64K_PAGES
274 default 16 if ARM64_16K_PAGES
277 # max bits determined by the following formula:
278 # VA_BITS - PAGE_SHIFT - 3
279 config ARCH_MMAP_RND_BITS_MAX
280 default 19 if ARM64_VA_BITS=36
281 default 24 if ARM64_VA_BITS=39
282 default 27 if ARM64_VA_BITS=42
283 default 30 if ARM64_VA_BITS=47
284 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
285 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
286 default 33 if ARM64_VA_BITS=48
287 default 14 if ARM64_64K_PAGES
288 default 16 if ARM64_16K_PAGES
291 config ARCH_MMAP_RND_COMPAT_BITS_MIN
292 default 7 if ARM64_64K_PAGES
293 default 9 if ARM64_16K_PAGES
296 config ARCH_MMAP_RND_COMPAT_BITS_MAX
302 config STACKTRACE_SUPPORT
305 config ILLEGAL_POINTER_VALUE
307 default 0xdead000000000000
309 config LOCKDEP_SUPPORT
316 config GENERIC_BUG_RELATIVE_POINTERS
318 depends on GENERIC_BUG
320 config GENERIC_HWEIGHT
326 config GENERIC_CALIBRATE_DELAY
329 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
335 config KERNEL_MODE_NEON
338 config FIX_EARLYCON_MEM
341 config PGTABLE_LEVELS
343 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
344 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
345 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
346 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
347 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
348 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
350 config ARCH_SUPPORTS_UPROBES
353 config ARCH_PROC_KCORE_TEXT
356 config BROKEN_GAS_INST
357 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
359 config KASAN_SHADOW_OFFSET
361 depends on KASAN_GENERIC || KASAN_SW_TAGS
362 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
363 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
364 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
365 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
366 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
367 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
368 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
369 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
370 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
371 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
372 default 0xffffffffffffffff
374 source "arch/arm64/Kconfig.platforms"
376 menu "Kernel Features"
378 menu "ARM errata workarounds via the alternatives framework"
380 config ARM64_WORKAROUND_CLEAN_CACHE
383 config ARM64_ERRATUM_826319
384 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
386 select ARM64_WORKAROUND_CLEAN_CACHE
388 This option adds an alternative code sequence to work around ARM
389 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
390 AXI master interface and an L2 cache.
392 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
393 and is unable to accept a certain write via this interface, it will
394 not progress on read data presented on the read data channel and the
397 The workaround promotes data cache clean instructions to
398 data cache clean-and-invalidate.
399 Please note that this does not necessarily enable the workaround,
400 as it depends on the alternative framework, which will only patch
401 the kernel if an affected CPU is detected.
405 config ARM64_ERRATUM_827319
406 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
408 select ARM64_WORKAROUND_CLEAN_CACHE
410 This option adds an alternative code sequence to work around ARM
411 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
412 master interface and an L2 cache.
414 Under certain conditions this erratum can cause a clean line eviction
415 to occur at the same time as another transaction to the same address
416 on the AMBA 5 CHI interface, which can cause data corruption if the
417 interconnect reorders the two transactions.
419 The workaround promotes data cache clean instructions to
420 data cache clean-and-invalidate.
421 Please note that this does not necessarily enable the workaround,
422 as it depends on the alternative framework, which will only patch
423 the kernel if an affected CPU is detected.
427 config ARM64_ERRATUM_824069
428 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
430 select ARM64_WORKAROUND_CLEAN_CACHE
432 This option adds an alternative code sequence to work around ARM
433 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
434 to a coherent interconnect.
436 If a Cortex-A53 processor is executing a store or prefetch for
437 write instruction at the same time as a processor in another
438 cluster is executing a cache maintenance operation to the same
439 address, then this erratum might cause a clean cache line to be
440 incorrectly marked as dirty.
442 The workaround promotes data cache clean instructions to
443 data cache clean-and-invalidate.
444 Please note that this option does not necessarily enable the
445 workaround, as it depends on the alternative framework, which will
446 only patch the kernel if an affected CPU is detected.
450 config ARM64_ERRATUM_819472
451 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
453 select ARM64_WORKAROUND_CLEAN_CACHE
455 This option adds an alternative code sequence to work around ARM
456 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
457 present when it is connected to a coherent interconnect.
459 If the processor is executing a load and store exclusive sequence at
460 the same time as a processor in another cluster is executing a cache
461 maintenance operation to the same address, then this erratum might
462 cause data corruption.
464 The workaround promotes data cache clean instructions to
465 data cache clean-and-invalidate.
466 Please note that this does not necessarily enable the workaround,
467 as it depends on the alternative framework, which will only patch
468 the kernel if an affected CPU is detected.
472 config ARM64_ERRATUM_832075
473 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
476 This option adds an alternative code sequence to work around ARM
477 erratum 832075 on Cortex-A57 parts up to r1p2.
479 Affected Cortex-A57 parts might deadlock when exclusive load/store
480 instructions to Write-Back memory are mixed with Device loads.
482 The workaround is to promote device loads to use Load-Acquire
484 Please note that this does not necessarily enable the workaround,
485 as it depends on the alternative framework, which will only patch
486 the kernel if an affected CPU is detected.
490 config ARM64_ERRATUM_834220
491 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
495 This option adds an alternative code sequence to work around ARM
496 erratum 834220 on Cortex-A57 parts up to r1p2.
498 Affected Cortex-A57 parts might report a Stage 2 translation
499 fault as the result of a Stage 1 fault for load crossing a
500 page boundary when there is a permission or device memory
501 alignment fault at Stage 1 and a translation fault at Stage 2.
503 The workaround is to verify that the Stage 1 translation
504 doesn't generate a fault before handling the Stage 2 fault.
505 Please note that this does not necessarily enable the workaround,
506 as it depends on the alternative framework, which will only patch
507 the kernel if an affected CPU is detected.
511 config ARM64_ERRATUM_1742098
512 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
516 This option removes the AES hwcap for aarch32 user-space to
517 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
519 Affected parts may corrupt the AES state if an interrupt is
520 taken between a pair of AES instructions. These instructions
521 are only present if the cryptography extensions are present.
522 All software should have a fallback implementation for CPUs
523 that don't implement the cryptography extensions.
527 config ARM64_ERRATUM_845719
528 bool "Cortex-A53: 845719: a load might read incorrect data"
532 This option adds an alternative code sequence to work around ARM
533 erratum 845719 on Cortex-A53 parts up to r0p4.
535 When running a compat (AArch32) userspace on an affected Cortex-A53
536 part, a load at EL0 from a virtual address that matches the bottom 32
537 bits of the virtual address used by a recent load at (AArch64) EL1
538 might return incorrect data.
540 The workaround is to write the contextidr_el1 register on exception
541 return to a 32-bit task.
542 Please note that this does not necessarily enable the workaround,
543 as it depends on the alternative framework, which will only patch
544 the kernel if an affected CPU is detected.
548 config ARM64_ERRATUM_843419
549 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
551 select ARM64_MODULE_PLTS if MODULES
553 This option links the kernel with '--fix-cortex-a53-843419' and
554 enables PLT support to replace certain ADRP instructions, which can
555 cause subsequent memory accesses to use an incorrect address on
556 Cortex-A53 parts up to r0p4.
560 config ARM64_LD_HAS_FIX_ERRATUM_843419
561 def_bool $(ld-option,--fix-cortex-a53-843419)
563 config ARM64_ERRATUM_1024718
564 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
567 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
569 Affected Cortex-A55 cores (all revisions) could cause incorrect
570 update of the hardware dirty bit when the DBM/AP bits are updated
571 without a break-before-make. The workaround is to disable the usage
572 of hardware DBM locally on the affected cores. CPUs not affected by
573 this erratum will continue to use the feature.
577 config ARM64_ERRATUM_1418040
578 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
582 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
583 errata 1188873 and 1418040.
585 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
586 cause register corruption when accessing the timer registers
587 from AArch32 userspace.
591 config ARM64_WORKAROUND_SPECULATIVE_AT
594 config ARM64_ERRATUM_1165522
595 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
597 select ARM64_WORKAROUND_SPECULATIVE_AT
599 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
601 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
602 corrupted TLBs by speculating an AT instruction during a guest
607 config ARM64_ERRATUM_1319367
608 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
610 select ARM64_WORKAROUND_SPECULATIVE_AT
612 This option adds work arounds for ARM Cortex-A57 erratum 1319537
613 and A72 erratum 1319367
615 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
616 speculating an AT instruction during a guest context switch.
620 config ARM64_ERRATUM_1530923
621 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
623 select ARM64_WORKAROUND_SPECULATIVE_AT
625 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
627 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
628 corrupted TLBs by speculating an AT instruction during a guest
633 config ARM64_WORKAROUND_REPEAT_TLBI
636 config ARM64_ERRATUM_1286807
637 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
639 select ARM64_WORKAROUND_REPEAT_TLBI
641 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
643 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
644 address for a cacheable mapping of a location is being
645 accessed by a core while another core is remapping the virtual
646 address to a new physical page using the recommended
647 break-before-make sequence, then under very rare circumstances
648 TLBI+DSB completes before a read using the translation being
649 invalidated has been observed by other observers. The
650 workaround repeats the TLBI+DSB operation.
652 config ARM64_ERRATUM_1463225
653 bool "Cortex-A76: Software Step might prevent interrupt recognition"
656 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
658 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
659 of a system call instruction (SVC) can prevent recognition of
660 subsequent interrupts when software stepping is disabled in the
661 exception handler of the system call and either kernel debugging
662 is enabled or VHE is in use.
664 Work around the erratum by triggering a dummy step exception
665 when handling a system call from a task that is being stepped
666 in a VHE configuration of the kernel.
670 config ARM64_ERRATUM_1542419
671 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
674 This option adds a workaround for ARM Neoverse-N1 erratum
677 Affected Neoverse-N1 cores could execute a stale instruction when
678 modified by another CPU. The workaround depends on a firmware
681 Workaround the issue by hiding the DIC feature from EL0. This
682 forces user-space to perform cache maintenance.
686 config ARM64_ERRATUM_1508412
687 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
690 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
692 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
693 of a store-exclusive or read of PAR_EL1 and a load with device or
694 non-cacheable memory attributes. The workaround depends on a firmware
697 KVM guests must also have the workaround implemented or they can
700 Work around the issue by inserting DMB SY barriers around PAR_EL1
701 register reads and warning KVM users. The DMB barrier is sufficient
702 to prevent a speculative PAR_EL1 read.
706 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
709 config ARM64_ERRATUM_2051678
710 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
713 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
714 Affected Cortex-A510 might not respect the ordering rules for
715 hardware update of the page table's dirty bit. The workaround
716 is to not enable the feature on affected CPUs.
720 config ARM64_ERRATUM_2077057
721 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
724 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
725 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
726 expected, but a Pointer Authentication trap is taken instead. The
727 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
728 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
730 This can only happen when EL2 is stepping EL1.
732 When these conditions occur, the SPSR_EL2 value is unchanged from the
733 previous guest entry, and can be restored from the in-memory copy.
737 config ARM64_ERRATUM_2658417
738 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
741 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
742 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
743 BFMMLA or VMMLA instructions in rare circumstances when a pair of
744 A510 CPUs are using shared neon hardware. As the sharing is not
745 discoverable by the kernel, hide the BF16 HWCAP to indicate that
746 user-space should not be using these instructions.
750 config ARM64_ERRATUM_2119858
751 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
753 depends on CORESIGHT_TRBE
754 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
756 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
758 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
759 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
760 the event of a WRAP event.
762 Work around the issue by always making sure we move the TRBPTR_EL1 by
763 256 bytes before enabling the buffer and filling the first 256 bytes of
764 the buffer with ETM ignore packets upon disabling.
768 config ARM64_ERRATUM_2139208
769 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
771 depends on CORESIGHT_TRBE
772 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
774 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
776 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
777 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
778 the event of a WRAP event.
780 Work around the issue by always making sure we move the TRBPTR_EL1 by
781 256 bytes before enabling the buffer and filling the first 256 bytes of
782 the buffer with ETM ignore packets upon disabling.
786 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
789 config ARM64_ERRATUM_2054223
790 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
792 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
794 Enable workaround for ARM Cortex-A710 erratum 2054223
796 Affected cores may fail to flush the trace data on a TSB instruction, when
797 the PE is in trace prohibited state. This will cause losing a few bytes
800 Workaround is to issue two TSB consecutively on affected cores.
804 config ARM64_ERRATUM_2067961
805 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
807 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
809 Enable workaround for ARM Neoverse-N2 erratum 2067961
811 Affected cores may fail to flush the trace data on a TSB instruction, when
812 the PE is in trace prohibited state. This will cause losing a few bytes
815 Workaround is to issue two TSB consecutively on affected cores.
819 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
822 config ARM64_ERRATUM_2253138
823 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
824 depends on CORESIGHT_TRBE
826 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
828 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
830 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
831 for TRBE. Under some conditions, the TRBE might generate a write to the next
832 virtually addressed page following the last page of the TRBE address space
833 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
835 Work around this in the driver by always making sure that there is a
836 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
840 config ARM64_ERRATUM_2224489
841 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
842 depends on CORESIGHT_TRBE
844 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
846 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
848 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
849 for TRBE. Under some conditions, the TRBE might generate a write to the next
850 virtually addressed page following the last page of the TRBE address space
851 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
853 Work around this in the driver by always making sure that there is a
854 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
858 config ARM64_ERRATUM_2441009
859 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
861 select ARM64_WORKAROUND_REPEAT_TLBI
863 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
865 Under very rare circumstances, affected Cortex-A510 CPUs
866 may not handle a race between a break-before-make sequence on one
867 CPU, and another CPU accessing the same page. This could allow a
868 store to a page that has been unmapped.
870 Work around this by adding the affected CPUs to the list that needs
871 TLB sequences to be done twice.
875 config ARM64_ERRATUM_2064142
876 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
877 depends on CORESIGHT_TRBE
880 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
882 Affected Cortex-A510 core might fail to write into system registers after the
883 TRBE has been disabled. Under some conditions after the TRBE has been disabled
884 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
885 and TRBTRG_EL1 will be ignored and will not be effected.
887 Work around this in the driver by executing TSB CSYNC and DSB after collection
888 is stopped and before performing a system register write to one of the affected
893 config ARM64_ERRATUM_2038923
894 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
895 depends on CORESIGHT_TRBE
898 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
900 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
901 prohibited within the CPU. As a result, the trace buffer or trace buffer state
902 might be corrupted. This happens after TRBE buffer has been enabled by setting
903 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
904 execution changes from a context, in which trace is prohibited to one where it
905 isn't, or vice versa. In these mentioned conditions, the view of whether trace
906 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
907 the trace buffer state might be corrupted.
909 Work around this in the driver by preventing an inconsistent view of whether the
910 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
911 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
912 two ISB instructions if no ERET is to take place.
916 config ARM64_ERRATUM_1902691
917 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
918 depends on CORESIGHT_TRBE
921 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
923 Affected Cortex-A510 core might cause trace data corruption, when being written
924 into the memory. Effectively TRBE is broken and hence cannot be used to capture
927 Work around this problem in the driver by just preventing TRBE initialization on
928 affected cpus. The firmware must have disabled the access to TRBE for the kernel
929 on such implementations. This will cover the kernel for any firmware that doesn't
934 config ARM64_ERRATUM_2457168
935 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
936 depends on ARM64_AMU_EXTN
939 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
941 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
942 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
943 incorrectly giving a significantly higher output value.
945 Work around this problem by returning 0 when reading the affected counter in
946 key locations that results in disabling all users of this counter. This effect
947 is the same to firmware disabling affected counters.
951 config CAVIUM_ERRATUM_22375
952 bool "Cavium erratum 22375, 24313"
955 Enable workaround for errata 22375 and 24313.
957 This implements two gicv3-its errata workarounds for ThunderX. Both
958 with a small impact affecting only ITS table allocation.
960 erratum 22375: only alloc 8MB table size
961 erratum 24313: ignore memory access type
963 The fixes are in ITS initialization and basically ignore memory access
964 type and table size provided by the TYPER and BASER registers.
968 config CAVIUM_ERRATUM_23144
969 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
973 ITS SYNC command hang for cross node io and collections/cpu mapping.
977 config CAVIUM_ERRATUM_23154
978 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
981 The ThunderX GICv3 implementation requires a modified version for
982 reading the IAR status to ensure data synchronization
983 (access to icc_iar1_el1 is not sync'ed before and after).
985 It also suffers from erratum 38545 (also present on Marvell's
986 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
987 spuriously presented to the CPU interface.
991 config CAVIUM_ERRATUM_27456
992 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
995 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
996 instructions may cause the icache to become corrupted if it
997 contains data for a non-current ASID. The fix is to
998 invalidate the icache when changing the mm context.
1002 config CAVIUM_ERRATUM_30115
1003 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1006 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1007 1.2, and T83 Pass 1.0, KVM guest execution may disable
1008 interrupts in host. Trapping both GICv3 group-0 and group-1
1009 accesses sidesteps the issue.
1013 config CAVIUM_TX2_ERRATUM_219
1014 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1017 On Cavium ThunderX2, a load, store or prefetch instruction between a
1018 TTBR update and the corresponding context synchronizing operation can
1019 cause a spurious Data Abort to be delivered to any hardware thread in
1022 Work around the issue by avoiding the problematic code sequence and
1023 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1024 trap handler performs the corresponding register access, skips the
1025 instruction and ensures context synchronization by virtue of the
1030 config FUJITSU_ERRATUM_010001
1031 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1034 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1035 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1036 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1037 This fault occurs under a specific hardware condition when a
1038 load/store instruction performs an address translation using:
1039 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1040 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1041 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1042 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1044 The workaround is to ensure these bits are clear in TCR_ELx.
1045 The workaround only affects the Fujitsu-A64FX.
1049 config HISILICON_ERRATUM_161600802
1050 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1053 The HiSilicon Hip07 SoC uses the wrong redistributor base
1054 when issued ITS commands such as VMOVP and VMAPP, and requires
1055 a 128kB offset to be applied to the target address in this commands.
1059 config QCOM_FALKOR_ERRATUM_1003
1060 bool "Falkor E1003: Incorrect translation due to ASID change"
1063 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1064 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1065 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1066 then only for entries in the walk cache, since the leaf translation
1067 is unchanged. Work around the erratum by invalidating the walk cache
1068 entries for the trampoline before entering the kernel proper.
1070 config QCOM_FALKOR_ERRATUM_1009
1071 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1073 select ARM64_WORKAROUND_REPEAT_TLBI
1075 On Falkor v1, the CPU may prematurely complete a DSB following a
1076 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1077 one more time to fix the issue.
1081 config QCOM_QDF2400_ERRATUM_0065
1082 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1085 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1086 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1087 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1091 config QCOM_FALKOR_ERRATUM_E1041
1092 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1095 Falkor CPU may speculatively fetch instructions from an improper
1096 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1097 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1101 config NVIDIA_CARMEL_CNP_ERRATUM
1102 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1105 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1106 invalidate shared TLB entries installed by a different core, as it would
1107 on standard ARM cores.
1111 config SOCIONEXT_SYNQUACER_PREITS
1112 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1115 Socionext Synquacer SoCs implement a separate h/w block to generate
1116 MSI doorbell writes with non-zero values for the device ID.
1120 endmenu # "ARM errata workarounds via the alternatives framework"
1124 default ARM64_4K_PAGES
1126 Page size (translation granule) configuration.
1128 config ARM64_4K_PAGES
1131 This feature enables 4KB pages support.
1133 config ARM64_16K_PAGES
1136 The system will use 16KB pages support. AArch32 emulation
1137 requires applications compiled with 16K (or a multiple of 16K)
1140 config ARM64_64K_PAGES
1143 This feature enables 64KB pages support (4KB by default)
1144 allowing only two levels of page tables and faster TLB
1145 look-up. AArch32 emulation requires applications compiled
1146 with 64K aligned segments.
1151 prompt "Virtual address space size"
1152 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1153 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1154 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1156 Allows choosing one of multiple possible virtual address
1157 space sizes. The level of translation table is determined by
1158 a combination of page size and virtual address space size.
1160 config ARM64_VA_BITS_36
1161 bool "36-bit" if EXPERT
1162 depends on ARM64_16K_PAGES
1164 config ARM64_VA_BITS_39
1166 depends on ARM64_4K_PAGES
1168 config ARM64_VA_BITS_42
1170 depends on ARM64_64K_PAGES
1172 config ARM64_VA_BITS_47
1174 depends on ARM64_16K_PAGES
1176 config ARM64_VA_BITS_48
1179 config ARM64_VA_BITS_52
1181 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1183 Enable 52-bit virtual addressing for userspace when explicitly
1184 requested via a hint to mmap(). The kernel will also use 52-bit
1185 virtual addresses for its own mappings (provided HW support for
1186 this feature is available, otherwise it reverts to 48-bit).
1188 NOTE: Enabling 52-bit virtual addressing in conjunction with
1189 ARMv8.3 Pointer Authentication will result in the PAC being
1190 reduced from 7 bits to 3 bits, which may have a significant
1191 impact on its susceptibility to brute-force attacks.
1193 If unsure, select 48-bit virtual addressing instead.
1197 config ARM64_FORCE_52BIT
1198 bool "Force 52-bit virtual addresses for userspace"
1199 depends on ARM64_VA_BITS_52 && EXPERT
1201 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1202 to maintain compatibility with older software by providing 48-bit VAs
1203 unless a hint is supplied to mmap.
1205 This configuration option disables the 48-bit compatibility logic, and
1206 forces all userspace addresses to be 52-bit on HW that supports it. One
1207 should only enable this configuration option for stress testing userspace
1208 memory management code. If unsure say N here.
1210 config ARM64_VA_BITS
1212 default 36 if ARM64_VA_BITS_36
1213 default 39 if ARM64_VA_BITS_39
1214 default 42 if ARM64_VA_BITS_42
1215 default 47 if ARM64_VA_BITS_47
1216 default 48 if ARM64_VA_BITS_48
1217 default 52 if ARM64_VA_BITS_52
1220 prompt "Physical address space size"
1221 default ARM64_PA_BITS_48
1223 Choose the maximum physical address range that the kernel will
1226 config ARM64_PA_BITS_48
1229 config ARM64_PA_BITS_52
1230 bool "52-bit (ARMv8.2)"
1231 depends on ARM64_64K_PAGES
1232 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1234 Enable support for a 52-bit physical address space, introduced as
1235 part of the ARMv8.2-LPA extension.
1237 With this enabled, the kernel will also continue to work on CPUs that
1238 do not support ARMv8.2-LPA, but with some added memory overhead (and
1239 minor performance overhead).
1243 config ARM64_PA_BITS
1245 default 48 if ARM64_PA_BITS_48
1246 default 52 if ARM64_PA_BITS_52
1250 default CPU_LITTLE_ENDIAN
1252 Select the endianness of data accesses performed by the CPU. Userspace
1253 applications will need to be compiled and linked for the endianness
1254 that is selected here.
1256 config CPU_BIG_ENDIAN
1257 bool "Build big-endian kernel"
1258 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1260 Say Y if you plan on running a kernel with a big-endian userspace.
1262 config CPU_LITTLE_ENDIAN
1263 bool "Build little-endian kernel"
1265 Say Y if you plan on running a kernel with a little-endian userspace.
1266 This is usually the case for distributions targeting arm64.
1271 bool "Multi-core scheduler support"
1273 Multi-core scheduler support improves the CPU scheduler's decision
1274 making when dealing with multi-core CPU chips at a cost of slightly
1275 increased overhead in some places. If unsure say N here.
1277 config SCHED_CLUSTER
1278 bool "Cluster scheduler support"
1280 Cluster scheduler support improves the CPU scheduler's decision
1281 making when dealing with machines that have clusters of CPUs.
1282 Cluster usually means a couple of CPUs which are placed closely
1283 by sharing mid-level caches, last-level cache tags or internal
1287 bool "SMT scheduler support"
1289 Improves the CPU scheduler's decision making when dealing with
1290 MultiThreading at a cost of slightly increased overhead in some
1291 places. If unsure say N here.
1294 int "Maximum number of CPUs (2-4096)"
1299 bool "Support for hot-pluggable CPUs"
1300 select GENERIC_IRQ_MIGRATION
1302 Say Y here to experiment with turning CPUs off and on. CPUs
1303 can be controlled through /sys/devices/system/cpu.
1305 # Common NUMA Features
1307 bool "NUMA Memory Allocation and Scheduler Support"
1308 select GENERIC_ARCH_NUMA
1309 select ACPI_NUMA if ACPI
1311 select HAVE_SETUP_PER_CPU_AREA
1312 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1313 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1314 select USE_PERCPU_NUMA_NODE_ID
1316 Enable NUMA (Non-Uniform Memory Access) support.
1318 The kernel will try to allocate memory used by a CPU on the
1319 local memory of the CPU and add some more
1320 NUMA awareness to the kernel.
1323 int "Maximum NUMA Nodes (as a power of 2)"
1328 Specify the maximum number of NUMA Nodes available on the target
1329 system. Increases memory reserved to accommodate various tables.
1331 source "kernel/Kconfig.hz"
1333 config ARCH_SPARSEMEM_ENABLE
1335 select SPARSEMEM_VMEMMAP_ENABLE
1336 select SPARSEMEM_VMEMMAP
1338 config HW_PERF_EVENTS
1342 # Supported by clang >= 7.0 or GCC >= 12.0.0
1343 config CC_HAVE_SHADOW_CALL_STACK
1344 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1347 bool "Enable paravirtualization code"
1349 This changes the kernel so it can modify itself when it is run
1350 under a hypervisor, potentially improving performance significantly
1351 over full virtualization.
1353 config PARAVIRT_TIME_ACCOUNTING
1354 bool "Paravirtual steal time accounting"
1357 Select this option to enable fine granularity task steal time
1358 accounting. Time spent executing other tasks in parallel with
1359 the current vCPU is discounted from the vCPU power. To account for
1360 that, there can be a small performance impact.
1362 If in doubt, say N here.
1365 depends on PM_SLEEP_SMP
1367 bool "kexec system call"
1369 kexec is a system call that implements the ability to shutdown your
1370 current kernel, and to start another kernel. It is like a reboot
1371 but it is independent of the system firmware. And like a reboot
1372 you can start any kernel with it, not just Linux.
1375 bool "kexec file based system call"
1377 select HAVE_IMA_KEXEC if IMA
1379 This is new version of kexec system call. This system call is
1380 file based and takes file descriptors as system call argument
1381 for kernel and initramfs as opposed to list of segments as
1382 accepted by previous system call.
1385 bool "Verify kernel signature during kexec_file_load() syscall"
1386 depends on KEXEC_FILE
1388 Select this option to verify a signature with loaded kernel
1389 image. If configured, any attempt of loading a image without
1390 valid signature will fail.
1392 In addition to that option, you need to enable signature
1393 verification for the corresponding kernel image type being
1394 loaded in order for this to work.
1396 config KEXEC_IMAGE_VERIFY_SIG
1397 bool "Enable Image signature verification support"
1399 depends on KEXEC_SIG
1400 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1402 Enable Image signature verification support.
1404 comment "Support for PE file signature verification disabled"
1405 depends on KEXEC_SIG
1406 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1409 bool "Build kdump crash kernel"
1411 Generate crash dump after being started by kexec. This should
1412 be normally only set in special crash dump kernels which are
1413 loaded in the main kernel with kexec-tools into a specially
1414 reserved region and then later executed after a crash by
1417 For more details see Documentation/admin-guide/kdump/kdump.rst
1421 depends on HIBERNATION || KEXEC_CORE
1428 bool "Xen guest support on ARM64"
1429 depends on ARM64 && OF
1433 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1435 config FORCE_MAX_ZONEORDER
1437 default "14" if ARM64_64K_PAGES
1438 default "12" if ARM64_16K_PAGES
1441 The kernel memory allocator divides physically contiguous memory
1442 blocks into "zones", where each zone is a power of two number of
1443 pages. This option selects the largest power of two that the kernel
1444 keeps in the memory allocator. If you need to allocate very large
1445 blocks of physically contiguous memory, then you may need to
1446 increase this value.
1448 This config option is actually maximum order plus one. For example,
1449 a value of 11 means that the largest free memory block is 2^10 pages.
1451 We make sure that we can allocate upto a HugePage size for each configuration.
1453 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1455 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1456 4M allocations matching the default size used by generic code.
1458 config UNMAP_KERNEL_AT_EL0
1459 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1462 Speculation attacks against some high-performance processors can
1463 be used to bypass MMU permission checks and leak kernel data to
1464 userspace. This can be defended against by unmapping the kernel
1465 when running in userspace, mapping it back in on exception entry
1466 via a trampoline page in the vector table.
1470 config MITIGATE_SPECTRE_BRANCH_HISTORY
1471 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1474 Speculation attacks against some high-performance processors can
1475 make use of branch history to influence future speculation.
1476 When taking an exception from user-space, a sequence of branches
1477 or a firmware call overwrites the branch history.
1479 config RODATA_FULL_DEFAULT_ENABLED
1480 bool "Apply r/o permissions of VM areas also to their linear aliases"
1483 Apply read-only attributes of VM areas to the linear alias of
1484 the backing pages as well. This prevents code or read-only data
1485 from being modified (inadvertently or intentionally) via another
1486 mapping of the same memory page. This additional enhancement can
1487 be turned off at runtime by passing rodata=[off|on] (and turned on
1488 with rodata=full if this option is set to 'n')
1490 This requires the linear region to be mapped down to pages,
1491 which may adversely affect performance in some cases.
1493 config ARM64_SW_TTBR0_PAN
1494 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1496 Enabling this option prevents the kernel from accessing
1497 user-space memory directly by pointing TTBR0_EL1 to a reserved
1498 zeroed area and reserved ASID. The user access routines
1499 restore the valid TTBR0_EL1 temporarily.
1501 config ARM64_TAGGED_ADDR_ABI
1502 bool "Enable the tagged user addresses syscall ABI"
1505 When this option is enabled, user applications can opt in to a
1506 relaxed ABI via prctl() allowing tagged addresses to be passed
1507 to system calls as pointer arguments. For details, see
1508 Documentation/arm64/tagged-address-abi.rst.
1511 bool "Kernel support for 32-bit EL0"
1512 depends on ARM64_4K_PAGES || EXPERT
1514 select OLD_SIGSUSPEND3
1515 select COMPAT_OLD_SIGACTION
1517 This option enables support for a 32-bit EL0 running under a 64-bit
1518 kernel at EL1. AArch32-specific components such as system calls,
1519 the user helper functions, VFP support and the ptrace interface are
1520 handled appropriately by the kernel.
1522 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1523 that you will only be able to execute AArch32 binaries that were compiled
1524 with page size aligned segments.
1526 If you want to execute 32-bit userspace applications, say Y.
1530 config KUSER_HELPERS
1531 bool "Enable kuser helpers page for 32-bit applications"
1534 Warning: disabling this option may break 32-bit user programs.
1536 Provide kuser helpers to compat tasks. The kernel provides
1537 helper code to userspace in read only form at a fixed location
1538 to allow userspace to be independent of the CPU type fitted to
1539 the system. This permits binaries to be run on ARMv4 through
1540 to ARMv8 without modification.
1542 See Documentation/arm/kernel_user_helpers.rst for details.
1544 However, the fixed address nature of these helpers can be used
1545 by ROP (return orientated programming) authors when creating
1548 If all of the binaries and libraries which run on your platform
1549 are built specifically for your platform, and make no use of
1550 these helpers, then you can turn this option off to hinder
1551 such exploits. However, in that case, if a binary or library
1552 relying on those helpers is run, it will not function correctly.
1554 Say N here only if you are absolutely certain that you do not
1555 need these helpers; otherwise, the safe option is to say Y.
1558 bool "Enable vDSO for 32-bit applications"
1559 depends on !CPU_BIG_ENDIAN
1560 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1561 select GENERIC_COMPAT_VDSO
1564 Place in the process address space of 32-bit applications an
1565 ELF shared object providing fast implementations of gettimeofday
1568 You must have a 32-bit build of glibc 2.22 or later for programs
1569 to seamlessly take advantage of this.
1571 config THUMB2_COMPAT_VDSO
1572 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1573 depends on COMPAT_VDSO
1576 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1577 otherwise with '-marm'.
1579 config COMPAT_ALIGNMENT_FIXUPS
1580 bool "Fix up misaligned multi-word loads and stores in user space"
1582 menuconfig ARMV8_DEPRECATED
1583 bool "Emulate deprecated/obsolete ARMv8 instructions"
1586 Legacy software support may require certain instructions
1587 that have been deprecated or obsoleted in the architecture.
1589 Enable this config to enable selective emulation of these
1596 config SWP_EMULATION
1597 bool "Emulate SWP/SWPB instructions"
1599 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1600 they are always undefined. Say Y here to enable software
1601 emulation of these instructions for userspace using LDXR/STXR.
1602 This feature can be controlled at runtime with the abi.swp
1603 sysctl which is disabled by default.
1605 In some older versions of glibc [<=2.8] SWP is used during futex
1606 trylock() operations with the assumption that the code will not
1607 be preempted. This invalid assumption may be more likely to fail
1608 with SWP emulation enabled, leading to deadlock of the user
1611 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1612 on an external transaction monitoring block called a global
1613 monitor to maintain update atomicity. If your system does not
1614 implement a global monitor, this option can cause programs that
1615 perform SWP operations to uncached memory to deadlock.
1619 config CP15_BARRIER_EMULATION
1620 bool "Emulate CP15 Barrier instructions"
1622 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1623 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1624 strongly recommended to use the ISB, DSB, and DMB
1625 instructions instead.
1627 Say Y here to enable software emulation of these
1628 instructions for AArch32 userspace code. When this option is
1629 enabled, CP15 barrier usage is traced which can help
1630 identify software that needs updating. This feature can be
1631 controlled at runtime with the abi.cp15_barrier sysctl.
1635 config SETEND_EMULATION
1636 bool "Emulate SETEND instruction"
1638 The SETEND instruction alters the data-endianness of the
1639 AArch32 EL0, and is deprecated in ARMv8.
1641 Say Y here to enable software emulation of the instruction
1642 for AArch32 userspace code. This feature can be controlled
1643 at runtime with the abi.setend sysctl.
1645 Note: All the cpus on the system must have mixed endian support at EL0
1646 for this feature to be enabled. If a new CPU - which doesn't support mixed
1647 endian - is hotplugged in after this feature has been enabled, there could
1648 be unexpected results in the applications.
1651 endif # ARMV8_DEPRECATED
1655 menu "ARMv8.1 architectural features"
1657 config ARM64_HW_AFDBM
1658 bool "Support for hardware updates of the Access and Dirty page flags"
1661 The ARMv8.1 architecture extensions introduce support for
1662 hardware updates of the access and dirty information in page
1663 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1664 capable processors, accesses to pages with PTE_AF cleared will
1665 set this bit instead of raising an access flag fault.
1666 Similarly, writes to read-only pages with the DBM bit set will
1667 clear the read-only bit (AP[2]) instead of raising a
1670 Kernels built with this configuration option enabled continue
1671 to work on pre-ARMv8.1 hardware and the performance impact is
1672 minimal. If unsure, say Y.
1675 bool "Enable support for Privileged Access Never (PAN)"
1678 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1679 prevents the kernel or hypervisor from accessing user-space (EL0)
1682 Choosing this option will cause any unprotected (not using
1683 copy_to_user et al) memory access to fail with a permission fault.
1685 The feature is detected at runtime, and will remain as a 'nop'
1686 instruction if the cpu does not implement the feature.
1689 def_bool $(as-instr,.arch_extension rcpc)
1691 config AS_HAS_LSE_ATOMICS
1692 def_bool $(as-instr,.arch_extension lse)
1694 config ARM64_LSE_ATOMICS
1696 default ARM64_USE_LSE_ATOMICS
1697 depends on AS_HAS_LSE_ATOMICS
1699 config ARM64_USE_LSE_ATOMICS
1700 bool "Atomic instructions"
1701 depends on JUMP_LABEL
1704 As part of the Large System Extensions, ARMv8.1 introduces new
1705 atomic instructions that are designed specifically to scale in
1708 Say Y here to make use of these instructions for the in-kernel
1709 atomic routines. This incurs a small overhead on CPUs that do
1710 not support these instructions and requires the kernel to be
1711 built with binutils >= 2.25 in order for the new instructions
1714 endmenu # "ARMv8.1 architectural features"
1716 menu "ARMv8.2 architectural features"
1718 config AS_HAS_ARMV8_2
1719 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1722 def_bool $(as-instr,.arch armv8.2-a+sha3)
1725 bool "Enable support for persistent memory"
1726 select ARCH_HAS_PMEM_API
1727 select ARCH_HAS_UACCESS_FLUSHCACHE
1729 Say Y to enable support for the persistent memory API based on the
1730 ARMv8.2 DCPoP feature.
1732 The feature is detected at runtime, and the kernel will use DC CVAC
1733 operations if DC CVAP is not supported (following the behaviour of
1734 DC CVAP itself if the system does not define a point of persistence).
1736 config ARM64_RAS_EXTN
1737 bool "Enable support for RAS CPU Extensions"
1740 CPUs that support the Reliability, Availability and Serviceability
1741 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1742 errors, classify them and report them to software.
1744 On CPUs with these extensions system software can use additional
1745 barriers to determine if faults are pending and read the
1746 classification from a new set of registers.
1748 Selecting this feature will allow the kernel to use these barriers
1749 and access the new registers if the system supports the extension.
1750 Platform RAS features may additionally depend on firmware support.
1753 bool "Enable support for Common Not Private (CNP) translations"
1755 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1757 Common Not Private (CNP) allows translation table entries to
1758 be shared between different PEs in the same inner shareable
1759 domain, so the hardware can use this fact to optimise the
1760 caching of such entries in the TLB.
1762 Selecting this option allows the CNP feature to be detected
1763 at runtime, and does not affect PEs that do not implement
1766 endmenu # "ARMv8.2 architectural features"
1768 menu "ARMv8.3 architectural features"
1770 config ARM64_PTR_AUTH
1771 bool "Enable support for pointer authentication"
1774 Pointer authentication (part of the ARMv8.3 Extensions) provides
1775 instructions for signing and authenticating pointers against secret
1776 keys, which can be used to mitigate Return Oriented Programming (ROP)
1779 This option enables these instructions at EL0 (i.e. for userspace).
1780 Choosing this option will cause the kernel to initialise secret keys
1781 for each process at exec() time, with these keys being
1782 context-switched along with the process.
1784 The feature is detected at runtime. If the feature is not present in
1785 hardware it will not be advertised to userspace/KVM guest nor will it
1788 If the feature is present on the boot CPU but not on a late CPU, then
1789 the late CPU will be parked. Also, if the boot CPU does not have
1790 address auth and the late CPU has then the late CPU will still boot
1791 but with the feature disabled. On such a system, this option should
1794 config ARM64_PTR_AUTH_KERNEL
1795 bool "Use pointer authentication for kernel"
1797 depends on ARM64_PTR_AUTH
1798 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1799 # Modern compilers insert a .note.gnu.property section note for PAC
1800 # which is only understood by binutils starting with version 2.33.1.
1801 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1802 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1803 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1805 If the compiler supports the -mbranch-protection or
1806 -msign-return-address flag (e.g. GCC 7 or later), then this option
1807 will cause the kernel itself to be compiled with return address
1808 protection. In this case, and if the target hardware is known to
1809 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1810 disabled with minimal loss of protection.
1812 This feature works with FUNCTION_GRAPH_TRACER option only if
1813 DYNAMIC_FTRACE_WITH_REGS is enabled.
1815 config CC_HAS_BRANCH_PROT_PAC_RET
1816 # GCC 9 or later, clang 8 or later
1817 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1819 config CC_HAS_SIGN_RETURN_ADDRESS
1821 def_bool $(cc-option,-msign-return-address=all)
1824 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1826 config AS_HAS_CFI_NEGATE_RA_STATE
1827 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1829 endmenu # "ARMv8.3 architectural features"
1831 menu "ARMv8.4 architectural features"
1833 config ARM64_AMU_EXTN
1834 bool "Enable support for the Activity Monitors Unit CPU extension"
1837 The activity monitors extension is an optional extension introduced
1838 by the ARMv8.4 CPU architecture. This enables support for version 1
1839 of the activity monitors architecture, AMUv1.
1841 To enable the use of this extension on CPUs that implement it, say Y.
1843 Note that for architectural reasons, firmware _must_ implement AMU
1844 support when running on CPUs that present the activity monitors
1845 extension. The required support is present in:
1846 * Version 1.5 and later of the ARM Trusted Firmware
1848 For kernels that have this configuration enabled but boot with broken
1849 firmware, you may need to say N here until the firmware is fixed.
1850 Otherwise you may experience firmware panics or lockups when
1851 accessing the counter registers. Even if you are not observing these
1852 symptoms, the values returned by the register reads might not
1853 correctly reflect reality. Most commonly, the value read will be 0,
1854 indicating that the counter is not enabled.
1856 config AS_HAS_ARMV8_4
1857 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1859 config ARM64_TLB_RANGE
1860 bool "Enable support for tlbi range feature"
1862 depends on AS_HAS_ARMV8_4
1864 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1865 range of input addresses.
1867 The feature introduces new assembly instructions, and they were
1868 support when binutils >= 2.30.
1870 endmenu # "ARMv8.4 architectural features"
1872 menu "ARMv8.5 architectural features"
1874 config AS_HAS_ARMV8_5
1875 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1878 bool "Branch Target Identification support"
1881 Branch Target Identification (part of the ARMv8.5 Extensions)
1882 provides a mechanism to limit the set of locations to which computed
1883 branch instructions such as BR or BLR can jump.
1885 To make use of BTI on CPUs that support it, say Y.
1887 BTI is intended to provide complementary protection to other control
1888 flow integrity protection mechanisms, such as the Pointer
1889 authentication mechanism provided as part of the ARMv8.3 Extensions.
1890 For this reason, it does not make sense to enable this option without
1891 also enabling support for pointer authentication. Thus, when
1892 enabling this option you should also select ARM64_PTR_AUTH=y.
1894 Userspace binaries must also be specifically compiled to make use of
1895 this mechanism. If you say N here or the hardware does not support
1896 BTI, such binaries can still run, but you get no additional
1897 enforcement of branch destinations.
1899 config ARM64_BTI_KERNEL
1900 bool "Use Branch Target Identification for kernel"
1902 depends on ARM64_BTI
1903 depends on ARM64_PTR_AUTH_KERNEL
1904 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1905 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1906 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1907 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1908 depends on !CC_IS_GCC
1909 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1910 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1911 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1913 Build the kernel with Branch Target Identification annotations
1914 and enable enforcement of this for kernel code. When this option
1915 is enabled and the system supports BTI all kernel code including
1916 modular code must have BTI enabled.
1918 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1919 # GCC 9 or later, clang 8 or later
1920 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1923 bool "Enable support for E0PD"
1926 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1927 that EL0 accesses made via TTBR1 always fault in constant time,
1928 providing similar benefits to KASLR as those provided by KPTI, but
1929 with lower overhead and without disrupting legitimate access to
1930 kernel memory such as SPE.
1932 This option enables E0PD for TTBR1 where available.
1934 config ARM64_AS_HAS_MTE
1935 # Initial support for MTE went in binutils 2.32.0, checked with
1936 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1937 # as a late addition to the final architecture spec (LDGM/STGM)
1938 # is only supported in the newer 2.32.x and 2.33 binutils
1939 # versions, hence the extra "stgm" instruction check below.
1940 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1943 bool "Memory Tagging Extension support"
1945 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1946 depends on AS_HAS_ARMV8_5
1947 depends on AS_HAS_LSE_ATOMICS
1948 # Required for tag checking in the uaccess routines
1949 depends on ARM64_PAN
1950 select ARCH_HAS_SUBPAGE_FAULTS
1951 select ARCH_USES_HIGH_VMA_FLAGS
1953 Memory Tagging (part of the ARMv8.5 Extensions) provides
1954 architectural support for run-time, always-on detection of
1955 various classes of memory error to aid with software debugging
1956 to eliminate vulnerabilities arising from memory-unsafe
1959 This option enables the support for the Memory Tagging
1960 Extension at EL0 (i.e. for userspace).
1962 Selecting this option allows the feature to be detected at
1963 runtime. Any secondary CPU not implementing this feature will
1964 not be allowed a late bring-up.
1966 Userspace binaries that want to use this feature must
1967 explicitly opt in. The mechanism for the userspace is
1970 Documentation/arm64/memory-tagging-extension.rst.
1972 endmenu # "ARMv8.5 architectural features"
1974 menu "ARMv8.7 architectural features"
1977 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1979 depends on ARM64_PAN
1981 Enhanced Privileged Access Never (EPAN) allows Privileged
1982 Access Never to be used with Execute-only mappings.
1984 The feature is detected at runtime, and will remain disabled
1985 if the cpu does not implement the feature.
1986 endmenu # "ARMv8.7 architectural features"
1989 bool "ARM Scalable Vector Extension support"
1992 The Scalable Vector Extension (SVE) is an extension to the AArch64
1993 execution state which complements and extends the SIMD functionality
1994 of the base architecture to support much larger vectors and to enable
1995 additional vectorisation opportunities.
1997 To enable use of this extension on CPUs that implement it, say Y.
1999 On CPUs that support the SVE2 extensions, this option will enable
2002 Note that for architectural reasons, firmware _must_ implement SVE
2003 support when running on SVE capable hardware. The required support
2006 * version 1.5 and later of the ARM Trusted Firmware
2007 * the AArch64 boot wrapper since commit 5e1261e08abf
2008 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2010 For other firmware implementations, consult the firmware documentation
2013 If you need the kernel to boot on SVE-capable hardware with broken
2014 firmware, you may need to say N here until you get your firmware
2015 fixed. Otherwise, you may experience firmware panics or lockups when
2016 booting the kernel. If unsure and you are not observing these
2017 symptoms, you should assume that it is safe to say Y.
2020 bool "ARM Scalable Matrix Extension support"
2022 depends on ARM64_SVE
2024 The Scalable Matrix Extension (SME) is an extension to the AArch64
2025 execution state which utilises a substantial subset of the SVE
2026 instruction set, together with the addition of new architectural
2027 register state capable of holding two dimensional matrix tiles to
2028 enable various matrix operations.
2030 config ARM64_MODULE_PLTS
2031 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2033 select HAVE_MOD_ARCH_SPECIFIC
2035 Allocate PLTs when loading modules so that jumps and calls whose
2036 targets are too far away for their relative offsets to be encoded
2037 in the instructions themselves can be bounced via veneers in the
2038 module's PLT. This allows modules to be allocated in the generic
2039 vmalloc area after the dedicated module memory area has been
2042 When running with address space randomization (KASLR), the module
2043 region itself may be too far away for ordinary relative jumps and
2044 calls, and so in that case, module PLTs are required and cannot be
2047 Specific errata workaround(s) might also force module PLTs to be
2048 enabled (ARM64_ERRATUM_843419).
2050 config ARM64_PSEUDO_NMI
2051 bool "Support for NMI-like interrupts"
2054 Adds support for mimicking Non-Maskable Interrupts through the use of
2055 GIC interrupt priority. This support requires version 3 or later of
2058 This high priority configuration for interrupts needs to be
2059 explicitly enabled by setting the kernel parameter
2060 "irqchip.gicv3_pseudo_nmi" to 1.
2065 config ARM64_DEBUG_PRIORITY_MASKING
2066 bool "Debug interrupt priority masking"
2068 This adds runtime checks to functions enabling/disabling
2069 interrupts when using priority masking. The additional checks verify
2070 the validity of ICC_PMR_EL1 when calling concerned functions.
2073 endif # ARM64_PSEUDO_NMI
2076 bool "Build a relocatable kernel image" if EXPERT
2077 select ARCH_HAS_RELR
2080 This builds the kernel as a Position Independent Executable (PIE),
2081 which retains all relocation metadata required to relocate the
2082 kernel binary at runtime to a different virtual address than the
2083 address it was linked at.
2084 Since AArch64 uses the RELA relocation format, this requires a
2085 relocation pass at runtime even if the kernel is loaded at the
2086 same address it was linked at.
2088 config RANDOMIZE_BASE
2089 bool "Randomize the address of the kernel image"
2090 select ARM64_MODULE_PLTS if MODULES
2093 Randomizes the virtual address at which the kernel image is
2094 loaded, as a security feature that deters exploit attempts
2095 relying on knowledge of the location of kernel internals.
2097 It is the bootloader's job to provide entropy, by passing a
2098 random u64 value in /chosen/kaslr-seed at kernel entry.
2100 When booting via the UEFI stub, it will invoke the firmware's
2101 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2102 to the kernel proper. In addition, it will randomise the physical
2103 location of the kernel Image as well.
2107 config RANDOMIZE_MODULE_REGION_FULL
2108 bool "Randomize the module region over a 2 GB range"
2109 depends on RANDOMIZE_BASE
2112 Randomizes the location of the module region inside a 2 GB window
2113 covering the core kernel. This way, it is less likely for modules
2114 to leak information about the location of core kernel data structures
2115 but it does imply that function calls between modules and the core
2116 kernel will need to be resolved via veneers in the module PLT.
2118 When this option is not set, the module region will be randomized over
2119 a limited range that contains the [_stext, _etext] interval of the
2120 core kernel, so branch relocations are almost always in range unless
2121 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2122 particular case of region exhaustion, modules might be able to fall
2123 back to a larger 2GB area.
2125 config CC_HAVE_STACKPROTECTOR_SYSREG
2126 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2128 config STACKPROTECTOR_PER_TASK
2130 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2132 # The GPIO number here must be sorted by descending number. In case of
2133 # a multiplatform kernel, we just want the highest value required by the
2134 # selected platforms.
2137 default 2048 if ARCH_APPLE
2140 Maximum number of GPIOs in the system.
2142 If unsure, leave the default value.
2144 endmenu # "Kernel Features"
2148 config ARM64_ACPI_PARKING_PROTOCOL
2149 bool "Enable support for the ARM64 ACPI parking protocol"
2152 Enable support for the ARM64 ACPI parking protocol. If disabled
2153 the kernel will not allow booting through the ARM64 ACPI parking
2154 protocol even if the corresponding data is present in the ACPI
2158 string "Default kernel command string"
2161 Provide a set of default command-line options at build time by
2162 entering them here. As a minimum, you should specify the the
2163 root device (e.g. root=/dev/nfs).
2166 prompt "Kernel command line type" if CMDLINE != ""
2167 default CMDLINE_FROM_BOOTLOADER
2169 Choose how the kernel will handle the provided default kernel
2170 command line string.
2172 config CMDLINE_FROM_BOOTLOADER
2173 bool "Use bootloader kernel arguments if available"
2175 Uses the command-line options passed by the boot loader. If
2176 the boot loader doesn't provide any, the default kernel command
2177 string provided in CMDLINE will be used.
2179 config CMDLINE_FORCE
2180 bool "Always use the default kernel command string"
2182 Always use the default kernel command string, even if the boot
2183 loader passes other arguments to the kernel.
2184 This is useful if you cannot or don't want to change the
2185 command-line options your boot loader passes to the kernel.
2193 bool "UEFI runtime support"
2194 depends on OF && !CPU_BIG_ENDIAN
2195 depends on KERNEL_MODE_NEON
2196 select ARCH_SUPPORTS_ACPI
2199 select EFI_PARAMS_FROM_FDT
2200 select EFI_RUNTIME_WRAPPERS
2202 select EFI_GENERIC_STUB
2203 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2206 This option provides support for runtime services provided
2207 by UEFI firmware (such as non-volatile variables, realtime
2208 clock, and platform reset). A UEFI stub is also provided to
2209 allow the kernel to be booted as an EFI application. This
2210 is only useful on systems that have UEFI firmware.
2213 bool "Enable support for SMBIOS (DMI) tables"
2217 This enables SMBIOS/DMI feature for systems.
2219 This option is only useful on systems that have UEFI firmware.
2220 However, even with this option, the resultant kernel should
2221 continue to boot on existing non-UEFI platforms.
2223 endmenu # "Boot options"
2225 menu "Power management options"
2227 source "kernel/power/Kconfig"
2229 config ARCH_HIBERNATION_POSSIBLE
2233 config ARCH_HIBERNATION_HEADER
2235 depends on HIBERNATION
2237 config ARCH_SUSPEND_POSSIBLE
2240 endmenu # "Power management options"
2242 menu "CPU Power Management"
2244 source "drivers/cpuidle/Kconfig"
2246 source "drivers/cpufreq/Kconfig"
2248 endmenu # "CPU Power Management"
2250 source "drivers/acpi/Kconfig"
2252 source "arch/arm64/kvm/Kconfig"
2255 source "arch/arm64/crypto/Kconfig"