1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI
9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10 select ACPI_MCFG if (ACPI && PCI)
11 select ACPI_SPCR_TABLE if ACPI
12 select ACPI_PPTT if ACPI
13 select ARCH_HAS_DEBUG_WX
14 select ARCH_BINFMT_ELF_EXTRA_PHDRS
15 select ARCH_BINFMT_ELF_STATE
16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CURRENT_STACK_POINTER
24 select ARCH_HAS_DEBUG_VIRTUAL
25 select ARCH_HAS_DEBUG_VM_PGTABLE
26 select ARCH_HAS_DMA_PREP_COHERENT
27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28 select ARCH_HAS_FAST_MULTIPLIER
29 select ARCH_HAS_FORTIFY_SOURCE
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_HAS_GIGANTIC_PAGE
33 select ARCH_HAS_KEEPINITRD
34 select ARCH_HAS_MEMBARRIER_SYNC_CORE
35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37 select ARCH_HAS_PTE_DEVMAP
38 select ARCH_HAS_PTE_SPECIAL
39 select ARCH_HAS_SETUP_DMA_OPS
40 select ARCH_HAS_SET_DIRECT_MAP
41 select ARCH_HAS_SET_MEMORY
43 select ARCH_HAS_STRICT_KERNEL_RWX
44 select ARCH_HAS_STRICT_MODULE_RWX
45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
46 select ARCH_HAS_SYNC_DMA_FOR_CPU
47 select ARCH_HAS_SYSCALL_WRAPPER
48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
50 select ARCH_HAS_ZONE_DMA_SET if EXPERT
51 select ARCH_HAVE_ELF_PROT
52 select ARCH_HAVE_NMI_SAFE_CMPXCHG
53 select ARCH_HAVE_TRACE_MMIO_ACCESS
54 select ARCH_INLINE_READ_LOCK if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
80 select ARCH_KEEP_MEMBLOCK
81 select ARCH_USE_CMPXCHG_LOCKREF
82 select ARCH_USE_GNU_PROPERTY
83 select ARCH_USE_MEMTEST
84 select ARCH_USE_QUEUED_RWLOCKS
85 select ARCH_USE_QUEUED_SPINLOCKS
86 select ARCH_USE_SYM_ANNOTATIONS
87 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
88 select ARCH_SUPPORTS_HUGETLBFS
89 select ARCH_SUPPORTS_MEMORY_FAILURE
90 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
91 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
92 select ARCH_SUPPORTS_LTO_CLANG_THIN
93 select ARCH_SUPPORTS_CFI_CLANG
94 select ARCH_SUPPORTS_ATOMIC_RMW
95 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
96 select ARCH_SUPPORTS_NUMA_BALANCING
97 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
98 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
99 select ARCH_WANT_DEFAULT_BPF_JIT
100 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
101 select ARCH_WANT_FRAME_POINTERS
102 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
103 select ARCH_WANT_LD_ORPHAN_WARN
104 select ARCH_WANTS_NO_INSTR
105 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
106 select ARCH_HAS_UBSAN_SANITIZE_ALL
108 select ARM_ARCH_TIMER
110 select AUDIT_ARCH_COMPAT_GENERIC
111 select ARM_GIC_V2M if PCI
113 select ARM_GIC_V3_ITS if PCI
115 select BUILDTIME_TABLE_SORT
116 select CLONE_BACKWARDS
118 select CPU_PM if (SUSPEND || CPU_IDLE)
120 select DCACHE_WORD_ACCESS
121 select DYNAMIC_FTRACE if FUNCTION_TRACER
122 select DMA_DIRECT_REMAP
125 select FUNCTION_ALIGNMENT_4B
126 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
127 select GENERIC_ALLOCATOR
128 select GENERIC_ARCH_TOPOLOGY
129 select GENERIC_CLOCKEVENTS_BROADCAST
130 select GENERIC_CPU_AUTOPROBE
131 select GENERIC_CPU_VULNERABILITIES
132 select GENERIC_EARLY_IOREMAP
133 select GENERIC_IDLE_POLL_SETUP
134 select GENERIC_IOREMAP
135 select GENERIC_IRQ_IPI
136 select GENERIC_IRQ_PROBE
137 select GENERIC_IRQ_SHOW
138 select GENERIC_IRQ_SHOW_LEVEL
139 select GENERIC_LIB_DEVMEM_IS_ALLOWED
140 select GENERIC_PCI_IOMAP
141 select GENERIC_PTDUMP
142 select GENERIC_SCHED_CLOCK
143 select GENERIC_SMP_IDLE_THREAD
144 select GENERIC_TIME_VSYSCALL
145 select GENERIC_GETTIMEOFDAY
146 select GENERIC_VDSO_TIME_NS
147 select HARDIRQS_SW_RESEND
152 select HAVE_ACPI_APEI if (ACPI && EFI)
153 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
154 select HAVE_ARCH_AUDITSYSCALL
155 select HAVE_ARCH_BITREVERSE
156 select HAVE_ARCH_COMPILER_H
157 select HAVE_ARCH_HUGE_VMALLOC
158 select HAVE_ARCH_HUGE_VMAP
159 select HAVE_ARCH_JUMP_LABEL
160 select HAVE_ARCH_JUMP_LABEL_RELATIVE
161 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
162 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
163 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
164 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
165 # Some instrumentation may be unsound, hence EXPERT
166 select HAVE_ARCH_KCSAN if EXPERT
167 select HAVE_ARCH_KFENCE
168 select HAVE_ARCH_KGDB
169 select HAVE_ARCH_MMAP_RND_BITS
170 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
171 select HAVE_ARCH_PREL32_RELOCATIONS
172 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
173 select HAVE_ARCH_SECCOMP_FILTER
174 select HAVE_ARCH_STACKLEAK
175 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
176 select HAVE_ARCH_TRACEHOOK
177 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
178 select HAVE_ARCH_VMAP_STACK
179 select HAVE_ARM_SMCCC
180 select HAVE_ASM_MODVERSIONS
182 select HAVE_C_RECORDMCOUNT
183 select HAVE_CMPXCHG_DOUBLE
184 select HAVE_CMPXCHG_LOCAL
185 select HAVE_CONTEXT_TRACKING_USER
186 select HAVE_DEBUG_KMEMLEAK
187 select HAVE_DMA_CONTIGUOUS
188 select HAVE_DYNAMIC_FTRACE
189 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
190 if $(cc-option,-fpatchable-function-entry=2)
191 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
192 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
193 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
194 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
195 !CC_OPTIMIZE_FOR_SIZE)
196 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
197 if DYNAMIC_FTRACE_WITH_ARGS
198 select HAVE_EFFICIENT_UNALIGNED_ACCESS
200 select HAVE_FTRACE_MCOUNT_RECORD
201 select HAVE_FUNCTION_TRACER
202 select HAVE_FUNCTION_ERROR_INJECTION
203 select HAVE_FUNCTION_GRAPH_TRACER
204 select HAVE_GCC_PLUGINS
205 select HAVE_HW_BREAKPOINT if PERF_EVENTS
206 select HAVE_IOREMAP_PROT
207 select HAVE_IRQ_TIME_ACCOUNTING
210 select HAVE_PERF_EVENTS
211 select HAVE_PERF_REGS
212 select HAVE_PERF_USER_STACK_DUMP
213 select HAVE_PREEMPT_DYNAMIC_KEY
214 select HAVE_REGS_AND_STACK_ACCESS_API
215 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
216 select HAVE_FUNCTION_ARG_ACCESS_API
217 select MMU_GATHER_RCU_TABLE_FREE
219 select HAVE_STACKPROTECTOR
220 select HAVE_SYSCALL_TRACEPOINTS
222 select HAVE_KRETPROBES
223 select HAVE_GENERIC_VDSO
225 select IRQ_FORCED_THREADING
226 select KASAN_VMALLOC if KASAN
227 select MODULES_USE_ELF_RELA
228 select NEED_DMA_MAP_STATE
229 select NEED_SG_DMA_LENGTH
231 select OF_EARLY_FLATTREE
232 select PCI_DOMAINS_GENERIC if PCI
233 select PCI_ECAM if (ACPI && PCI)
234 select PCI_SYSCALL if PCI
239 select SYSCTL_EXCEPTION_TRACE
240 select THREAD_INFO_IN_TASK
241 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
242 select TRACE_IRQFLAGS_SUPPORT
243 select TRACE_IRQFLAGS_NMI_SUPPORT
244 select HAVE_SOFTIRQ_ON_OWN_STACK
246 ARM 64-bit (AArch64) Linux support.
248 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
250 # https://github.com/ClangBuiltLinux/linux/issues/1507
251 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
252 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
254 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
256 depends on $(cc-option,-fpatchable-function-entry=2)
257 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
265 config ARM64_PAGE_SHIFT
267 default 16 if ARM64_64K_PAGES
268 default 14 if ARM64_16K_PAGES
271 config ARM64_CONT_PTE_SHIFT
273 default 5 if ARM64_64K_PAGES
274 default 7 if ARM64_16K_PAGES
277 config ARM64_CONT_PMD_SHIFT
279 default 5 if ARM64_64K_PAGES
280 default 5 if ARM64_16K_PAGES
283 config ARCH_MMAP_RND_BITS_MIN
284 default 14 if ARM64_64K_PAGES
285 default 16 if ARM64_16K_PAGES
288 # max bits determined by the following formula:
289 # VA_BITS - PAGE_SHIFT - 3
290 config ARCH_MMAP_RND_BITS_MAX
291 default 19 if ARM64_VA_BITS=36
292 default 24 if ARM64_VA_BITS=39
293 default 27 if ARM64_VA_BITS=42
294 default 30 if ARM64_VA_BITS=47
295 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
296 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
297 default 33 if ARM64_VA_BITS=48
298 default 14 if ARM64_64K_PAGES
299 default 16 if ARM64_16K_PAGES
302 config ARCH_MMAP_RND_COMPAT_BITS_MIN
303 default 7 if ARM64_64K_PAGES
304 default 9 if ARM64_16K_PAGES
307 config ARCH_MMAP_RND_COMPAT_BITS_MAX
313 config STACKTRACE_SUPPORT
316 config ILLEGAL_POINTER_VALUE
318 default 0xdead000000000000
320 config LOCKDEP_SUPPORT
327 config GENERIC_BUG_RELATIVE_POINTERS
329 depends on GENERIC_BUG
331 config GENERIC_HWEIGHT
337 config GENERIC_CALIBRATE_DELAY
340 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
346 config KERNEL_MODE_NEON
349 config FIX_EARLYCON_MEM
352 config PGTABLE_LEVELS
354 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
355 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
356 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
357 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
358 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
359 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
361 config ARCH_SUPPORTS_UPROBES
364 config ARCH_PROC_KCORE_TEXT
367 config BROKEN_GAS_INST
368 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
370 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
372 # Clang's __builtin_return_adddress() strips the PAC since 12.0.0
373 # https://reviews.llvm.org/D75044
374 default y if CC_IS_CLANG && (CLANG_VERSION >= 120000)
375 # GCC's __builtin_return_address() strips the PAC since 11.1.0,
376 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
377 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
378 default y if CC_IS_GCC && (GCC_VERSION >= 110100)
379 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
380 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000)
381 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000)
384 config KASAN_SHADOW_OFFSET
386 depends on KASAN_GENERIC || KASAN_SW_TAGS
387 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
388 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
389 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
390 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
391 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
392 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
393 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
394 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
395 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
396 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
397 default 0xffffffffffffffff
402 source "arch/arm64/Kconfig.platforms"
404 menu "Kernel Features"
406 menu "ARM errata workarounds via the alternatives framework"
408 config ARM64_WORKAROUND_CLEAN_CACHE
411 config ARM64_ERRATUM_826319
412 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
414 select ARM64_WORKAROUND_CLEAN_CACHE
416 This option adds an alternative code sequence to work around ARM
417 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
418 AXI master interface and an L2 cache.
420 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
421 and is unable to accept a certain write via this interface, it will
422 not progress on read data presented on the read data channel and the
425 The workaround promotes data cache clean instructions to
426 data cache clean-and-invalidate.
427 Please note that this does not necessarily enable the workaround,
428 as it depends on the alternative framework, which will only patch
429 the kernel if an affected CPU is detected.
433 config ARM64_ERRATUM_827319
434 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
436 select ARM64_WORKAROUND_CLEAN_CACHE
438 This option adds an alternative code sequence to work around ARM
439 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
440 master interface and an L2 cache.
442 Under certain conditions this erratum can cause a clean line eviction
443 to occur at the same time as another transaction to the same address
444 on the AMBA 5 CHI interface, which can cause data corruption if the
445 interconnect reorders the two transactions.
447 The workaround promotes data cache clean instructions to
448 data cache clean-and-invalidate.
449 Please note that this does not necessarily enable the workaround,
450 as it depends on the alternative framework, which will only patch
451 the kernel if an affected CPU is detected.
455 config ARM64_ERRATUM_824069
456 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
458 select ARM64_WORKAROUND_CLEAN_CACHE
460 This option adds an alternative code sequence to work around ARM
461 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
462 to a coherent interconnect.
464 If a Cortex-A53 processor is executing a store or prefetch for
465 write instruction at the same time as a processor in another
466 cluster is executing a cache maintenance operation to the same
467 address, then this erratum might cause a clean cache line to be
468 incorrectly marked as dirty.
470 The workaround promotes data cache clean instructions to
471 data cache clean-and-invalidate.
472 Please note that this option does not necessarily enable the
473 workaround, as it depends on the alternative framework, which will
474 only patch the kernel if an affected CPU is detected.
478 config ARM64_ERRATUM_819472
479 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
481 select ARM64_WORKAROUND_CLEAN_CACHE
483 This option adds an alternative code sequence to work around ARM
484 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
485 present when it is connected to a coherent interconnect.
487 If the processor is executing a load and store exclusive sequence at
488 the same time as a processor in another cluster is executing a cache
489 maintenance operation to the same address, then this erratum might
490 cause data corruption.
492 The workaround promotes data cache clean instructions to
493 data cache clean-and-invalidate.
494 Please note that this does not necessarily enable the workaround,
495 as it depends on the alternative framework, which will only patch
496 the kernel if an affected CPU is detected.
500 config ARM64_ERRATUM_832075
501 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
504 This option adds an alternative code sequence to work around ARM
505 erratum 832075 on Cortex-A57 parts up to r1p2.
507 Affected Cortex-A57 parts might deadlock when exclusive load/store
508 instructions to Write-Back memory are mixed with Device loads.
510 The workaround is to promote device loads to use Load-Acquire
512 Please note that this does not necessarily enable the workaround,
513 as it depends on the alternative framework, which will only patch
514 the kernel if an affected CPU is detected.
518 config ARM64_ERRATUM_834220
519 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
523 This option adds an alternative code sequence to work around ARM
524 erratum 834220 on Cortex-A57 parts up to r1p2.
526 Affected Cortex-A57 parts might report a Stage 2 translation
527 fault as the result of a Stage 1 fault for load crossing a
528 page boundary when there is a permission or device memory
529 alignment fault at Stage 1 and a translation fault at Stage 2.
531 The workaround is to verify that the Stage 1 translation
532 doesn't generate a fault before handling the Stage 2 fault.
533 Please note that this does not necessarily enable the workaround,
534 as it depends on the alternative framework, which will only patch
535 the kernel if an affected CPU is detected.
539 config ARM64_ERRATUM_1742098
540 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
544 This option removes the AES hwcap for aarch32 user-space to
545 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
547 Affected parts may corrupt the AES state if an interrupt is
548 taken between a pair of AES instructions. These instructions
549 are only present if the cryptography extensions are present.
550 All software should have a fallback implementation for CPUs
551 that don't implement the cryptography extensions.
555 config ARM64_ERRATUM_845719
556 bool "Cortex-A53: 845719: a load might read incorrect data"
560 This option adds an alternative code sequence to work around ARM
561 erratum 845719 on Cortex-A53 parts up to r0p4.
563 When running a compat (AArch32) userspace on an affected Cortex-A53
564 part, a load at EL0 from a virtual address that matches the bottom 32
565 bits of the virtual address used by a recent load at (AArch64) EL1
566 might return incorrect data.
568 The workaround is to write the contextidr_el1 register on exception
569 return to a 32-bit task.
570 Please note that this does not necessarily enable the workaround,
571 as it depends on the alternative framework, which will only patch
572 the kernel if an affected CPU is detected.
576 config ARM64_ERRATUM_843419
577 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
579 select ARM64_MODULE_PLTS if MODULES
581 This option links the kernel with '--fix-cortex-a53-843419' and
582 enables PLT support to replace certain ADRP instructions, which can
583 cause subsequent memory accesses to use an incorrect address on
584 Cortex-A53 parts up to r0p4.
588 config ARM64_LD_HAS_FIX_ERRATUM_843419
589 def_bool $(ld-option,--fix-cortex-a53-843419)
591 config ARM64_ERRATUM_1024718
592 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
595 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
597 Affected Cortex-A55 cores (all revisions) could cause incorrect
598 update of the hardware dirty bit when the DBM/AP bits are updated
599 without a break-before-make. The workaround is to disable the usage
600 of hardware DBM locally on the affected cores. CPUs not affected by
601 this erratum will continue to use the feature.
605 config ARM64_ERRATUM_1418040
606 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
610 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
611 errata 1188873 and 1418040.
613 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
614 cause register corruption when accessing the timer registers
615 from AArch32 userspace.
619 config ARM64_WORKAROUND_SPECULATIVE_AT
622 config ARM64_ERRATUM_1165522
623 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
625 select ARM64_WORKAROUND_SPECULATIVE_AT
627 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
629 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
630 corrupted TLBs by speculating an AT instruction during a guest
635 config ARM64_ERRATUM_1319367
636 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
638 select ARM64_WORKAROUND_SPECULATIVE_AT
640 This option adds work arounds for ARM Cortex-A57 erratum 1319537
641 and A72 erratum 1319367
643 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
644 speculating an AT instruction during a guest context switch.
648 config ARM64_ERRATUM_1530923
649 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
651 select ARM64_WORKAROUND_SPECULATIVE_AT
653 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
655 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
656 corrupted TLBs by speculating an AT instruction during a guest
661 config ARM64_WORKAROUND_REPEAT_TLBI
664 config ARM64_ERRATUM_2441007
665 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
667 select ARM64_WORKAROUND_REPEAT_TLBI
669 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
671 Under very rare circumstances, affected Cortex-A55 CPUs
672 may not handle a race between a break-before-make sequence on one
673 CPU, and another CPU accessing the same page. This could allow a
674 store to a page that has been unmapped.
676 Work around this by adding the affected CPUs to the list that needs
677 TLB sequences to be done twice.
681 config ARM64_ERRATUM_1286807
682 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
684 select ARM64_WORKAROUND_REPEAT_TLBI
686 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
688 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
689 address for a cacheable mapping of a location is being
690 accessed by a core while another core is remapping the virtual
691 address to a new physical page using the recommended
692 break-before-make sequence, then under very rare circumstances
693 TLBI+DSB completes before a read using the translation being
694 invalidated has been observed by other observers. The
695 workaround repeats the TLBI+DSB operation.
697 config ARM64_ERRATUM_1463225
698 bool "Cortex-A76: Software Step might prevent interrupt recognition"
701 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
703 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
704 of a system call instruction (SVC) can prevent recognition of
705 subsequent interrupts when software stepping is disabled in the
706 exception handler of the system call and either kernel debugging
707 is enabled or VHE is in use.
709 Work around the erratum by triggering a dummy step exception
710 when handling a system call from a task that is being stepped
711 in a VHE configuration of the kernel.
715 config ARM64_ERRATUM_1542419
716 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
719 This option adds a workaround for ARM Neoverse-N1 erratum
722 Affected Neoverse-N1 cores could execute a stale instruction when
723 modified by another CPU. The workaround depends on a firmware
726 Workaround the issue by hiding the DIC feature from EL0. This
727 forces user-space to perform cache maintenance.
731 config ARM64_ERRATUM_1508412
732 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
735 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
737 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
738 of a store-exclusive or read of PAR_EL1 and a load with device or
739 non-cacheable memory attributes. The workaround depends on a firmware
742 KVM guests must also have the workaround implemented or they can
745 Work around the issue by inserting DMB SY barriers around PAR_EL1
746 register reads and warning KVM users. The DMB barrier is sufficient
747 to prevent a speculative PAR_EL1 read.
751 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
754 config ARM64_ERRATUM_2051678
755 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
758 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
759 Affected Cortex-A510 might not respect the ordering rules for
760 hardware update of the page table's dirty bit. The workaround
761 is to not enable the feature on affected CPUs.
765 config ARM64_ERRATUM_2077057
766 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
769 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
770 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
771 expected, but a Pointer Authentication trap is taken instead. The
772 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
773 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
775 This can only happen when EL2 is stepping EL1.
777 When these conditions occur, the SPSR_EL2 value is unchanged from the
778 previous guest entry, and can be restored from the in-memory copy.
782 config ARM64_ERRATUM_2658417
783 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
786 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
787 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
788 BFMMLA or VMMLA instructions in rare circumstances when a pair of
789 A510 CPUs are using shared neon hardware. As the sharing is not
790 discoverable by the kernel, hide the BF16 HWCAP to indicate that
791 user-space should not be using these instructions.
795 config ARM64_ERRATUM_2119858
796 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
798 depends on CORESIGHT_TRBE
799 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
801 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
803 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
804 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
805 the event of a WRAP event.
807 Work around the issue by always making sure we move the TRBPTR_EL1 by
808 256 bytes before enabling the buffer and filling the first 256 bytes of
809 the buffer with ETM ignore packets upon disabling.
813 config ARM64_ERRATUM_2139208
814 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
816 depends on CORESIGHT_TRBE
817 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
819 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
821 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
822 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
823 the event of a WRAP event.
825 Work around the issue by always making sure we move the TRBPTR_EL1 by
826 256 bytes before enabling the buffer and filling the first 256 bytes of
827 the buffer with ETM ignore packets upon disabling.
831 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
834 config ARM64_ERRATUM_2054223
835 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
837 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
839 Enable workaround for ARM Cortex-A710 erratum 2054223
841 Affected cores may fail to flush the trace data on a TSB instruction, when
842 the PE is in trace prohibited state. This will cause losing a few bytes
845 Workaround is to issue two TSB consecutively on affected cores.
849 config ARM64_ERRATUM_2067961
850 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
852 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
854 Enable workaround for ARM Neoverse-N2 erratum 2067961
856 Affected cores may fail to flush the trace data on a TSB instruction, when
857 the PE is in trace prohibited state. This will cause losing a few bytes
860 Workaround is to issue two TSB consecutively on affected cores.
864 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
867 config ARM64_ERRATUM_2253138
868 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
869 depends on CORESIGHT_TRBE
871 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
873 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
875 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
876 for TRBE. Under some conditions, the TRBE might generate a write to the next
877 virtually addressed page following the last page of the TRBE address space
878 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
880 Work around this in the driver by always making sure that there is a
881 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
885 config ARM64_ERRATUM_2224489
886 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
887 depends on CORESIGHT_TRBE
889 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
891 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
893 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
894 for TRBE. Under some conditions, the TRBE might generate a write to the next
895 virtually addressed page following the last page of the TRBE address space
896 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
898 Work around this in the driver by always making sure that there is a
899 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
903 config ARM64_ERRATUM_2441009
904 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
906 select ARM64_WORKAROUND_REPEAT_TLBI
908 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
910 Under very rare circumstances, affected Cortex-A510 CPUs
911 may not handle a race between a break-before-make sequence on one
912 CPU, and another CPU accessing the same page. This could allow a
913 store to a page that has been unmapped.
915 Work around this by adding the affected CPUs to the list that needs
916 TLB sequences to be done twice.
920 config ARM64_ERRATUM_2064142
921 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
922 depends on CORESIGHT_TRBE
925 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
927 Affected Cortex-A510 core might fail to write into system registers after the
928 TRBE has been disabled. Under some conditions after the TRBE has been disabled
929 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
930 and TRBTRG_EL1 will be ignored and will not be effected.
932 Work around this in the driver by executing TSB CSYNC and DSB after collection
933 is stopped and before performing a system register write to one of the affected
938 config ARM64_ERRATUM_2038923
939 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
940 depends on CORESIGHT_TRBE
943 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
945 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
946 prohibited within the CPU. As a result, the trace buffer or trace buffer state
947 might be corrupted. This happens after TRBE buffer has been enabled by setting
948 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
949 execution changes from a context, in which trace is prohibited to one where it
950 isn't, or vice versa. In these mentioned conditions, the view of whether trace
951 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
952 the trace buffer state might be corrupted.
954 Work around this in the driver by preventing an inconsistent view of whether the
955 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
956 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
957 two ISB instructions if no ERET is to take place.
961 config ARM64_ERRATUM_1902691
962 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
963 depends on CORESIGHT_TRBE
966 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
968 Affected Cortex-A510 core might cause trace data corruption, when being written
969 into the memory. Effectively TRBE is broken and hence cannot be used to capture
972 Work around this problem in the driver by just preventing TRBE initialization on
973 affected cpus. The firmware must have disabled the access to TRBE for the kernel
974 on such implementations. This will cover the kernel for any firmware that doesn't
979 config ARM64_ERRATUM_2457168
980 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
981 depends on ARM64_AMU_EXTN
984 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
986 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
987 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
988 incorrectly giving a significantly higher output value.
990 Work around this problem by returning 0 when reading the affected counter in
991 key locations that results in disabling all users of this counter. This effect
992 is the same to firmware disabling affected counters.
996 config ARM64_ERRATUM_2645198
997 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1000 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1002 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1003 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1004 next instruction abort caused by permission fault.
1006 Only user-space does executable to non-executable permission transition via
1007 mprotect() system call. Workaround the problem by doing a break-before-make
1008 TLB invalidation, for all changes to executable user space mappings.
1012 config CAVIUM_ERRATUM_22375
1013 bool "Cavium erratum 22375, 24313"
1016 Enable workaround for errata 22375 and 24313.
1018 This implements two gicv3-its errata workarounds for ThunderX. Both
1019 with a small impact affecting only ITS table allocation.
1021 erratum 22375: only alloc 8MB table size
1022 erratum 24313: ignore memory access type
1024 The fixes are in ITS initialization and basically ignore memory access
1025 type and table size provided by the TYPER and BASER registers.
1029 config CAVIUM_ERRATUM_23144
1030 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1034 ITS SYNC command hang for cross node io and collections/cpu mapping.
1038 config CAVIUM_ERRATUM_23154
1039 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1042 The ThunderX GICv3 implementation requires a modified version for
1043 reading the IAR status to ensure data synchronization
1044 (access to icc_iar1_el1 is not sync'ed before and after).
1046 It also suffers from erratum 38545 (also present on Marvell's
1047 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1048 spuriously presented to the CPU interface.
1052 config CAVIUM_ERRATUM_27456
1053 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1056 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1057 instructions may cause the icache to become corrupted if it
1058 contains data for a non-current ASID. The fix is to
1059 invalidate the icache when changing the mm context.
1063 config CAVIUM_ERRATUM_30115
1064 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1067 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1068 1.2, and T83 Pass 1.0, KVM guest execution may disable
1069 interrupts in host. Trapping both GICv3 group-0 and group-1
1070 accesses sidesteps the issue.
1074 config CAVIUM_TX2_ERRATUM_219
1075 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1078 On Cavium ThunderX2, a load, store or prefetch instruction between a
1079 TTBR update and the corresponding context synchronizing operation can
1080 cause a spurious Data Abort to be delivered to any hardware thread in
1083 Work around the issue by avoiding the problematic code sequence and
1084 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1085 trap handler performs the corresponding register access, skips the
1086 instruction and ensures context synchronization by virtue of the
1091 config FUJITSU_ERRATUM_010001
1092 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1095 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1096 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1097 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1098 This fault occurs under a specific hardware condition when a
1099 load/store instruction performs an address translation using:
1100 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1101 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1102 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1103 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1105 The workaround is to ensure these bits are clear in TCR_ELx.
1106 The workaround only affects the Fujitsu-A64FX.
1110 config HISILICON_ERRATUM_161600802
1111 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1114 The HiSilicon Hip07 SoC uses the wrong redistributor base
1115 when issued ITS commands such as VMOVP and VMAPP, and requires
1116 a 128kB offset to be applied to the target address in this commands.
1120 config QCOM_FALKOR_ERRATUM_1003
1121 bool "Falkor E1003: Incorrect translation due to ASID change"
1124 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1125 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1126 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1127 then only for entries in the walk cache, since the leaf translation
1128 is unchanged. Work around the erratum by invalidating the walk cache
1129 entries for the trampoline before entering the kernel proper.
1131 config QCOM_FALKOR_ERRATUM_1009
1132 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1134 select ARM64_WORKAROUND_REPEAT_TLBI
1136 On Falkor v1, the CPU may prematurely complete a DSB following a
1137 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1138 one more time to fix the issue.
1142 config QCOM_QDF2400_ERRATUM_0065
1143 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1146 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1147 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1148 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1152 config QCOM_FALKOR_ERRATUM_E1041
1153 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1156 Falkor CPU may speculatively fetch instructions from an improper
1157 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1158 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1162 config NVIDIA_CARMEL_CNP_ERRATUM
1163 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1166 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1167 invalidate shared TLB entries installed by a different core, as it would
1168 on standard ARM cores.
1172 config ROCKCHIP_ERRATUM_3588001
1173 bool "Rockchip 3588001: GIC600 can not support shareability attributes"
1176 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1177 This means, that its sharability feature may not be used, even though it
1178 is supported by the IP itself.
1182 config SOCIONEXT_SYNQUACER_PREITS
1183 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1186 Socionext Synquacer SoCs implement a separate h/w block to generate
1187 MSI doorbell writes with non-zero values for the device ID.
1191 endmenu # "ARM errata workarounds via the alternatives framework"
1195 default ARM64_4K_PAGES
1197 Page size (translation granule) configuration.
1199 config ARM64_4K_PAGES
1202 This feature enables 4KB pages support.
1204 config ARM64_16K_PAGES
1207 The system will use 16KB pages support. AArch32 emulation
1208 requires applications compiled with 16K (or a multiple of 16K)
1211 config ARM64_64K_PAGES
1214 This feature enables 64KB pages support (4KB by default)
1215 allowing only two levels of page tables and faster TLB
1216 look-up. AArch32 emulation requires applications compiled
1217 with 64K aligned segments.
1222 prompt "Virtual address space size"
1223 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1224 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1225 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1227 Allows choosing one of multiple possible virtual address
1228 space sizes. The level of translation table is determined by
1229 a combination of page size and virtual address space size.
1231 config ARM64_VA_BITS_36
1232 bool "36-bit" if EXPERT
1233 depends on ARM64_16K_PAGES
1235 config ARM64_VA_BITS_39
1237 depends on ARM64_4K_PAGES
1239 config ARM64_VA_BITS_42
1241 depends on ARM64_64K_PAGES
1243 config ARM64_VA_BITS_47
1245 depends on ARM64_16K_PAGES
1247 config ARM64_VA_BITS_48
1250 config ARM64_VA_BITS_52
1252 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1254 Enable 52-bit virtual addressing for userspace when explicitly
1255 requested via a hint to mmap(). The kernel will also use 52-bit
1256 virtual addresses for its own mappings (provided HW support for
1257 this feature is available, otherwise it reverts to 48-bit).
1259 NOTE: Enabling 52-bit virtual addressing in conjunction with
1260 ARMv8.3 Pointer Authentication will result in the PAC being
1261 reduced from 7 bits to 3 bits, which may have a significant
1262 impact on its susceptibility to brute-force attacks.
1264 If unsure, select 48-bit virtual addressing instead.
1268 config ARM64_FORCE_52BIT
1269 bool "Force 52-bit virtual addresses for userspace"
1270 depends on ARM64_VA_BITS_52 && EXPERT
1272 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1273 to maintain compatibility with older software by providing 48-bit VAs
1274 unless a hint is supplied to mmap.
1276 This configuration option disables the 48-bit compatibility logic, and
1277 forces all userspace addresses to be 52-bit on HW that supports it. One
1278 should only enable this configuration option for stress testing userspace
1279 memory management code. If unsure say N here.
1281 config ARM64_VA_BITS
1283 default 36 if ARM64_VA_BITS_36
1284 default 39 if ARM64_VA_BITS_39
1285 default 42 if ARM64_VA_BITS_42
1286 default 47 if ARM64_VA_BITS_47
1287 default 48 if ARM64_VA_BITS_48
1288 default 52 if ARM64_VA_BITS_52
1291 prompt "Physical address space size"
1292 default ARM64_PA_BITS_48
1294 Choose the maximum physical address range that the kernel will
1297 config ARM64_PA_BITS_48
1300 config ARM64_PA_BITS_52
1301 bool "52-bit (ARMv8.2)"
1302 depends on ARM64_64K_PAGES
1303 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1305 Enable support for a 52-bit physical address space, introduced as
1306 part of the ARMv8.2-LPA extension.
1308 With this enabled, the kernel will also continue to work on CPUs that
1309 do not support ARMv8.2-LPA, but with some added memory overhead (and
1310 minor performance overhead).
1314 config ARM64_PA_BITS
1316 default 48 if ARM64_PA_BITS_48
1317 default 52 if ARM64_PA_BITS_52
1321 default CPU_LITTLE_ENDIAN
1323 Select the endianness of data accesses performed by the CPU. Userspace
1324 applications will need to be compiled and linked for the endianness
1325 that is selected here.
1327 config CPU_BIG_ENDIAN
1328 bool "Build big-endian kernel"
1329 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1331 Say Y if you plan on running a kernel with a big-endian userspace.
1333 config CPU_LITTLE_ENDIAN
1334 bool "Build little-endian kernel"
1336 Say Y if you plan on running a kernel with a little-endian userspace.
1337 This is usually the case for distributions targeting arm64.
1342 bool "Multi-core scheduler support"
1344 Multi-core scheduler support improves the CPU scheduler's decision
1345 making when dealing with multi-core CPU chips at a cost of slightly
1346 increased overhead in some places. If unsure say N here.
1348 config SCHED_CLUSTER
1349 bool "Cluster scheduler support"
1351 Cluster scheduler support improves the CPU scheduler's decision
1352 making when dealing with machines that have clusters of CPUs.
1353 Cluster usually means a couple of CPUs which are placed closely
1354 by sharing mid-level caches, last-level cache tags or internal
1358 bool "SMT scheduler support"
1360 Improves the CPU scheduler's decision making when dealing with
1361 MultiThreading at a cost of slightly increased overhead in some
1362 places. If unsure say N here.
1365 int "Maximum number of CPUs (2-4096)"
1370 bool "Support for hot-pluggable CPUs"
1371 select GENERIC_IRQ_MIGRATION
1373 Say Y here to experiment with turning CPUs off and on. CPUs
1374 can be controlled through /sys/devices/system/cpu.
1376 # Common NUMA Features
1378 bool "NUMA Memory Allocation and Scheduler Support"
1379 select GENERIC_ARCH_NUMA
1380 select ACPI_NUMA if ACPI
1382 select HAVE_SETUP_PER_CPU_AREA
1383 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1384 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1385 select USE_PERCPU_NUMA_NODE_ID
1387 Enable NUMA (Non-Uniform Memory Access) support.
1389 The kernel will try to allocate memory used by a CPU on the
1390 local memory of the CPU and add some more
1391 NUMA awareness to the kernel.
1394 int "Maximum NUMA Nodes (as a power of 2)"
1399 Specify the maximum number of NUMA Nodes available on the target
1400 system. Increases memory reserved to accommodate various tables.
1402 source "kernel/Kconfig.hz"
1404 config ARCH_SPARSEMEM_ENABLE
1406 select SPARSEMEM_VMEMMAP_ENABLE
1407 select SPARSEMEM_VMEMMAP
1409 config HW_PERF_EVENTS
1413 # Supported by clang >= 7.0 or GCC >= 12.0.0
1414 config CC_HAVE_SHADOW_CALL_STACK
1415 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1418 bool "Enable paravirtualization code"
1420 This changes the kernel so it can modify itself when it is run
1421 under a hypervisor, potentially improving performance significantly
1422 over full virtualization.
1424 config PARAVIRT_TIME_ACCOUNTING
1425 bool "Paravirtual steal time accounting"
1428 Select this option to enable fine granularity task steal time
1429 accounting. Time spent executing other tasks in parallel with
1430 the current vCPU is discounted from the vCPU power. To account for
1431 that, there can be a small performance impact.
1433 If in doubt, say N here.
1436 depends on PM_SLEEP_SMP
1438 bool "kexec system call"
1440 kexec is a system call that implements the ability to shutdown your
1441 current kernel, and to start another kernel. It is like a reboot
1442 but it is independent of the system firmware. And like a reboot
1443 you can start any kernel with it, not just Linux.
1446 bool "kexec file based system call"
1448 select HAVE_IMA_KEXEC if IMA
1450 This is new version of kexec system call. This system call is
1451 file based and takes file descriptors as system call argument
1452 for kernel and initramfs as opposed to list of segments as
1453 accepted by previous system call.
1456 bool "Verify kernel signature during kexec_file_load() syscall"
1457 depends on KEXEC_FILE
1459 Select this option to verify a signature with loaded kernel
1460 image. If configured, any attempt of loading a image without
1461 valid signature will fail.
1463 In addition to that option, you need to enable signature
1464 verification for the corresponding kernel image type being
1465 loaded in order for this to work.
1467 config KEXEC_IMAGE_VERIFY_SIG
1468 bool "Enable Image signature verification support"
1470 depends on KEXEC_SIG
1471 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1473 Enable Image signature verification support.
1475 comment "Support for PE file signature verification disabled"
1476 depends on KEXEC_SIG
1477 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1480 bool "Build kdump crash kernel"
1482 Generate crash dump after being started by kexec. This should
1483 be normally only set in special crash dump kernels which are
1484 loaded in the main kernel with kexec-tools into a specially
1485 reserved region and then later executed after a crash by
1488 For more details see Documentation/admin-guide/kdump/kdump.rst
1492 depends on HIBERNATION || KEXEC_CORE
1499 bool "Xen guest support on ARM64"
1500 depends on ARM64 && OF
1504 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1506 # include/linux/mmzone.h requires the following to be true:
1508 # MAX_ORDER - 1 + PAGE_SHIFT <= SECTION_SIZE_BITS
1510 # so the maximum value of MAX_ORDER is SECTION_SIZE_BITS + 1 - PAGE_SHIFT:
1512 # | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_ORDER | default MAX_ORDER |
1513 # ----+-------------------+--------------+-----------------+--------------------+
1514 # 4K | 27 | 12 | 16 | 11 |
1515 # 16K | 27 | 14 | 14 | 12 |
1516 # 64K | 29 | 16 | 14 | 14 |
1517 config ARCH_FORCE_MAX_ORDER
1518 int "Maximum zone order" if ARM64_4K_PAGES || ARM64_16K_PAGES
1519 default "14" if ARM64_64K_PAGES
1520 range 12 14 if ARM64_16K_PAGES
1521 default "12" if ARM64_16K_PAGES
1522 range 11 16 if ARM64_4K_PAGES
1525 The kernel memory allocator divides physically contiguous memory
1526 blocks into "zones", where each zone is a power of two number of
1527 pages. This option selects the largest power of two that the kernel
1528 keeps in the memory allocator. If you need to allocate very large
1529 blocks of physically contiguous memory, then you may need to
1530 increase this value.
1532 This config option is actually maximum order plus one. For example,
1533 a value of 11 means that the largest free memory block is 2^10 pages.
1535 We make sure that we can allocate up to a HugePage size for each configuration.
1537 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1539 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1540 4M allocations matching the default size used by generic code.
1542 config UNMAP_KERNEL_AT_EL0
1543 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1546 Speculation attacks against some high-performance processors can
1547 be used to bypass MMU permission checks and leak kernel data to
1548 userspace. This can be defended against by unmapping the kernel
1549 when running in userspace, mapping it back in on exception entry
1550 via a trampoline page in the vector table.
1554 config MITIGATE_SPECTRE_BRANCH_HISTORY
1555 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1558 Speculation attacks against some high-performance processors can
1559 make use of branch history to influence future speculation.
1560 When taking an exception from user-space, a sequence of branches
1561 or a firmware call overwrites the branch history.
1563 config RODATA_FULL_DEFAULT_ENABLED
1564 bool "Apply r/o permissions of VM areas also to their linear aliases"
1567 Apply read-only attributes of VM areas to the linear alias of
1568 the backing pages as well. This prevents code or read-only data
1569 from being modified (inadvertently or intentionally) via another
1570 mapping of the same memory page. This additional enhancement can
1571 be turned off at runtime by passing rodata=[off|on] (and turned on
1572 with rodata=full if this option is set to 'n')
1574 This requires the linear region to be mapped down to pages,
1575 which may adversely affect performance in some cases.
1577 config ARM64_SW_TTBR0_PAN
1578 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1580 Enabling this option prevents the kernel from accessing
1581 user-space memory directly by pointing TTBR0_EL1 to a reserved
1582 zeroed area and reserved ASID. The user access routines
1583 restore the valid TTBR0_EL1 temporarily.
1585 config ARM64_TAGGED_ADDR_ABI
1586 bool "Enable the tagged user addresses syscall ABI"
1589 When this option is enabled, user applications can opt in to a
1590 relaxed ABI via prctl() allowing tagged addresses to be passed
1591 to system calls as pointer arguments. For details, see
1592 Documentation/arm64/tagged-address-abi.rst.
1595 bool "Kernel support for 32-bit EL0"
1596 depends on ARM64_4K_PAGES || EXPERT
1598 select OLD_SIGSUSPEND3
1599 select COMPAT_OLD_SIGACTION
1601 This option enables support for a 32-bit EL0 running under a 64-bit
1602 kernel at EL1. AArch32-specific components such as system calls,
1603 the user helper functions, VFP support and the ptrace interface are
1604 handled appropriately by the kernel.
1606 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1607 that you will only be able to execute AArch32 binaries that were compiled
1608 with page size aligned segments.
1610 If you want to execute 32-bit userspace applications, say Y.
1614 config KUSER_HELPERS
1615 bool "Enable kuser helpers page for 32-bit applications"
1618 Warning: disabling this option may break 32-bit user programs.
1620 Provide kuser helpers to compat tasks. The kernel provides
1621 helper code to userspace in read only form at a fixed location
1622 to allow userspace to be independent of the CPU type fitted to
1623 the system. This permits binaries to be run on ARMv4 through
1624 to ARMv8 without modification.
1626 See Documentation/arm/kernel_user_helpers.rst for details.
1628 However, the fixed address nature of these helpers can be used
1629 by ROP (return orientated programming) authors when creating
1632 If all of the binaries and libraries which run on your platform
1633 are built specifically for your platform, and make no use of
1634 these helpers, then you can turn this option off to hinder
1635 such exploits. However, in that case, if a binary or library
1636 relying on those helpers is run, it will not function correctly.
1638 Say N here only if you are absolutely certain that you do not
1639 need these helpers; otherwise, the safe option is to say Y.
1642 bool "Enable vDSO for 32-bit applications"
1643 depends on !CPU_BIG_ENDIAN
1644 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1645 select GENERIC_COMPAT_VDSO
1648 Place in the process address space of 32-bit applications an
1649 ELF shared object providing fast implementations of gettimeofday
1652 You must have a 32-bit build of glibc 2.22 or later for programs
1653 to seamlessly take advantage of this.
1655 config THUMB2_COMPAT_VDSO
1656 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1657 depends on COMPAT_VDSO
1660 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1661 otherwise with '-marm'.
1663 config COMPAT_ALIGNMENT_FIXUPS
1664 bool "Fix up misaligned multi-word loads and stores in user space"
1666 menuconfig ARMV8_DEPRECATED
1667 bool "Emulate deprecated/obsolete ARMv8 instructions"
1670 Legacy software support may require certain instructions
1671 that have been deprecated or obsoleted in the architecture.
1673 Enable this config to enable selective emulation of these
1680 config SWP_EMULATION
1681 bool "Emulate SWP/SWPB instructions"
1683 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1684 they are always undefined. Say Y here to enable software
1685 emulation of these instructions for userspace using LDXR/STXR.
1686 This feature can be controlled at runtime with the abi.swp
1687 sysctl which is disabled by default.
1689 In some older versions of glibc [<=2.8] SWP is used during futex
1690 trylock() operations with the assumption that the code will not
1691 be preempted. This invalid assumption may be more likely to fail
1692 with SWP emulation enabled, leading to deadlock of the user
1695 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1696 on an external transaction monitoring block called a global
1697 monitor to maintain update atomicity. If your system does not
1698 implement a global monitor, this option can cause programs that
1699 perform SWP operations to uncached memory to deadlock.
1703 config CP15_BARRIER_EMULATION
1704 bool "Emulate CP15 Barrier instructions"
1706 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1707 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1708 strongly recommended to use the ISB, DSB, and DMB
1709 instructions instead.
1711 Say Y here to enable software emulation of these
1712 instructions for AArch32 userspace code. When this option is
1713 enabled, CP15 barrier usage is traced which can help
1714 identify software that needs updating. This feature can be
1715 controlled at runtime with the abi.cp15_barrier sysctl.
1719 config SETEND_EMULATION
1720 bool "Emulate SETEND instruction"
1722 The SETEND instruction alters the data-endianness of the
1723 AArch32 EL0, and is deprecated in ARMv8.
1725 Say Y here to enable software emulation of the instruction
1726 for AArch32 userspace code. This feature can be controlled
1727 at runtime with the abi.setend sysctl.
1729 Note: All the cpus on the system must have mixed endian support at EL0
1730 for this feature to be enabled. If a new CPU - which doesn't support mixed
1731 endian - is hotplugged in after this feature has been enabled, there could
1732 be unexpected results in the applications.
1735 endif # ARMV8_DEPRECATED
1739 menu "ARMv8.1 architectural features"
1741 config ARM64_HW_AFDBM
1742 bool "Support for hardware updates of the Access and Dirty page flags"
1745 The ARMv8.1 architecture extensions introduce support for
1746 hardware updates of the access and dirty information in page
1747 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1748 capable processors, accesses to pages with PTE_AF cleared will
1749 set this bit instead of raising an access flag fault.
1750 Similarly, writes to read-only pages with the DBM bit set will
1751 clear the read-only bit (AP[2]) instead of raising a
1754 Kernels built with this configuration option enabled continue
1755 to work on pre-ARMv8.1 hardware and the performance impact is
1756 minimal. If unsure, say Y.
1759 bool "Enable support for Privileged Access Never (PAN)"
1762 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1763 prevents the kernel or hypervisor from accessing user-space (EL0)
1766 Choosing this option will cause any unprotected (not using
1767 copy_to_user et al) memory access to fail with a permission fault.
1769 The feature is detected at runtime, and will remain as a 'nop'
1770 instruction if the cpu does not implement the feature.
1773 def_bool $(as-instr,.arch_extension rcpc)
1775 config AS_HAS_LSE_ATOMICS
1776 def_bool $(as-instr,.arch_extension lse)
1778 config ARM64_LSE_ATOMICS
1780 default ARM64_USE_LSE_ATOMICS
1781 depends on AS_HAS_LSE_ATOMICS
1783 config ARM64_USE_LSE_ATOMICS
1784 bool "Atomic instructions"
1787 As part of the Large System Extensions, ARMv8.1 introduces new
1788 atomic instructions that are designed specifically to scale in
1791 Say Y here to make use of these instructions for the in-kernel
1792 atomic routines. This incurs a small overhead on CPUs that do
1793 not support these instructions and requires the kernel to be
1794 built with binutils >= 2.25 in order for the new instructions
1797 endmenu # "ARMv8.1 architectural features"
1799 menu "ARMv8.2 architectural features"
1801 config AS_HAS_ARMV8_2
1802 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1805 def_bool $(as-instr,.arch armv8.2-a+sha3)
1808 bool "Enable support for persistent memory"
1809 select ARCH_HAS_PMEM_API
1810 select ARCH_HAS_UACCESS_FLUSHCACHE
1812 Say Y to enable support for the persistent memory API based on the
1813 ARMv8.2 DCPoP feature.
1815 The feature is detected at runtime, and the kernel will use DC CVAC
1816 operations if DC CVAP is not supported (following the behaviour of
1817 DC CVAP itself if the system does not define a point of persistence).
1819 config ARM64_RAS_EXTN
1820 bool "Enable support for RAS CPU Extensions"
1823 CPUs that support the Reliability, Availability and Serviceability
1824 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1825 errors, classify them and report them to software.
1827 On CPUs with these extensions system software can use additional
1828 barriers to determine if faults are pending and read the
1829 classification from a new set of registers.
1831 Selecting this feature will allow the kernel to use these barriers
1832 and access the new registers if the system supports the extension.
1833 Platform RAS features may additionally depend on firmware support.
1836 bool "Enable support for Common Not Private (CNP) translations"
1838 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1840 Common Not Private (CNP) allows translation table entries to
1841 be shared between different PEs in the same inner shareable
1842 domain, so the hardware can use this fact to optimise the
1843 caching of such entries in the TLB.
1845 Selecting this option allows the CNP feature to be detected
1846 at runtime, and does not affect PEs that do not implement
1849 endmenu # "ARMv8.2 architectural features"
1851 menu "ARMv8.3 architectural features"
1853 config ARM64_PTR_AUTH
1854 bool "Enable support for pointer authentication"
1857 Pointer authentication (part of the ARMv8.3 Extensions) provides
1858 instructions for signing and authenticating pointers against secret
1859 keys, which can be used to mitigate Return Oriented Programming (ROP)
1862 This option enables these instructions at EL0 (i.e. for userspace).
1863 Choosing this option will cause the kernel to initialise secret keys
1864 for each process at exec() time, with these keys being
1865 context-switched along with the process.
1867 The feature is detected at runtime. If the feature is not present in
1868 hardware it will not be advertised to userspace/KVM guest nor will it
1871 If the feature is present on the boot CPU but not on a late CPU, then
1872 the late CPU will be parked. Also, if the boot CPU does not have
1873 address auth and the late CPU has then the late CPU will still boot
1874 but with the feature disabled. On such a system, this option should
1877 config ARM64_PTR_AUTH_KERNEL
1878 bool "Use pointer authentication for kernel"
1880 depends on ARM64_PTR_AUTH
1881 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1882 # Modern compilers insert a .note.gnu.property section note for PAC
1883 # which is only understood by binutils starting with version 2.33.1.
1884 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1885 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1886 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1888 If the compiler supports the -mbranch-protection or
1889 -msign-return-address flag (e.g. GCC 7 or later), then this option
1890 will cause the kernel itself to be compiled with return address
1891 protection. In this case, and if the target hardware is known to
1892 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1893 disabled with minimal loss of protection.
1895 This feature works with FUNCTION_GRAPH_TRACER option only if
1896 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1898 config CC_HAS_BRANCH_PROT_PAC_RET
1899 # GCC 9 or later, clang 8 or later
1900 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1902 config CC_HAS_SIGN_RETURN_ADDRESS
1904 def_bool $(cc-option,-msign-return-address=all)
1906 config AS_HAS_ARMV8_3
1907 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1909 config AS_HAS_CFI_NEGATE_RA_STATE
1910 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1912 endmenu # "ARMv8.3 architectural features"
1914 menu "ARMv8.4 architectural features"
1916 config ARM64_AMU_EXTN
1917 bool "Enable support for the Activity Monitors Unit CPU extension"
1920 The activity monitors extension is an optional extension introduced
1921 by the ARMv8.4 CPU architecture. This enables support for version 1
1922 of the activity monitors architecture, AMUv1.
1924 To enable the use of this extension on CPUs that implement it, say Y.
1926 Note that for architectural reasons, firmware _must_ implement AMU
1927 support when running on CPUs that present the activity monitors
1928 extension. The required support is present in:
1929 * Version 1.5 and later of the ARM Trusted Firmware
1931 For kernels that have this configuration enabled but boot with broken
1932 firmware, you may need to say N here until the firmware is fixed.
1933 Otherwise you may experience firmware panics or lockups when
1934 accessing the counter registers. Even if you are not observing these
1935 symptoms, the values returned by the register reads might not
1936 correctly reflect reality. Most commonly, the value read will be 0,
1937 indicating that the counter is not enabled.
1939 config AS_HAS_ARMV8_4
1940 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1942 config ARM64_TLB_RANGE
1943 bool "Enable support for tlbi range feature"
1945 depends on AS_HAS_ARMV8_4
1947 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1948 range of input addresses.
1950 The feature introduces new assembly instructions, and they were
1951 support when binutils >= 2.30.
1953 endmenu # "ARMv8.4 architectural features"
1955 menu "ARMv8.5 architectural features"
1957 config AS_HAS_ARMV8_5
1958 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1961 bool "Branch Target Identification support"
1964 Branch Target Identification (part of the ARMv8.5 Extensions)
1965 provides a mechanism to limit the set of locations to which computed
1966 branch instructions such as BR or BLR can jump.
1968 To make use of BTI on CPUs that support it, say Y.
1970 BTI is intended to provide complementary protection to other control
1971 flow integrity protection mechanisms, such as the Pointer
1972 authentication mechanism provided as part of the ARMv8.3 Extensions.
1973 For this reason, it does not make sense to enable this option without
1974 also enabling support for pointer authentication. Thus, when
1975 enabling this option you should also select ARM64_PTR_AUTH=y.
1977 Userspace binaries must also be specifically compiled to make use of
1978 this mechanism. If you say N here or the hardware does not support
1979 BTI, such binaries can still run, but you get no additional
1980 enforcement of branch destinations.
1982 config ARM64_BTI_KERNEL
1983 bool "Use Branch Target Identification for kernel"
1985 depends on ARM64_BTI
1986 depends on ARM64_PTR_AUTH_KERNEL
1987 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1988 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1989 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1990 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1991 depends on !CC_IS_GCC
1992 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1993 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1994 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1996 Build the kernel with Branch Target Identification annotations
1997 and enable enforcement of this for kernel code. When this option
1998 is enabled and the system supports BTI all kernel code including
1999 modular code must have BTI enabled.
2001 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
2002 # GCC 9 or later, clang 8 or later
2003 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2006 bool "Enable support for E0PD"
2009 E0PD (part of the ARMv8.5 extensions) allows us to ensure
2010 that EL0 accesses made via TTBR1 always fault in constant time,
2011 providing similar benefits to KASLR as those provided by KPTI, but
2012 with lower overhead and without disrupting legitimate access to
2013 kernel memory such as SPE.
2015 This option enables E0PD for TTBR1 where available.
2017 config ARM64_AS_HAS_MTE
2018 # Initial support for MTE went in binutils 2.32.0, checked with
2019 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2020 # as a late addition to the final architecture spec (LDGM/STGM)
2021 # is only supported in the newer 2.32.x and 2.33 binutils
2022 # versions, hence the extra "stgm" instruction check below.
2023 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2026 bool "Memory Tagging Extension support"
2028 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2029 depends on AS_HAS_ARMV8_5
2030 depends on AS_HAS_LSE_ATOMICS
2031 # Required for tag checking in the uaccess routines
2032 depends on ARM64_PAN
2033 select ARCH_HAS_SUBPAGE_FAULTS
2034 select ARCH_USES_HIGH_VMA_FLAGS
2035 select ARCH_USES_PG_ARCH_X
2037 Memory Tagging (part of the ARMv8.5 Extensions) provides
2038 architectural support for run-time, always-on detection of
2039 various classes of memory error to aid with software debugging
2040 to eliminate vulnerabilities arising from memory-unsafe
2043 This option enables the support for the Memory Tagging
2044 Extension at EL0 (i.e. for userspace).
2046 Selecting this option allows the feature to be detected at
2047 runtime. Any secondary CPU not implementing this feature will
2048 not be allowed a late bring-up.
2050 Userspace binaries that want to use this feature must
2051 explicitly opt in. The mechanism for the userspace is
2054 Documentation/arm64/memory-tagging-extension.rst.
2056 endmenu # "ARMv8.5 architectural features"
2058 menu "ARMv8.7 architectural features"
2061 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2063 depends on ARM64_PAN
2065 Enhanced Privileged Access Never (EPAN) allows Privileged
2066 Access Never to be used with Execute-only mappings.
2068 The feature is detected at runtime, and will remain disabled
2069 if the cpu does not implement the feature.
2070 endmenu # "ARMv8.7 architectural features"
2073 bool "ARM Scalable Vector Extension support"
2076 The Scalable Vector Extension (SVE) is an extension to the AArch64
2077 execution state which complements and extends the SIMD functionality
2078 of the base architecture to support much larger vectors and to enable
2079 additional vectorisation opportunities.
2081 To enable use of this extension on CPUs that implement it, say Y.
2083 On CPUs that support the SVE2 extensions, this option will enable
2086 Note that for architectural reasons, firmware _must_ implement SVE
2087 support when running on SVE capable hardware. The required support
2090 * version 1.5 and later of the ARM Trusted Firmware
2091 * the AArch64 boot wrapper since commit 5e1261e08abf
2092 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2094 For other firmware implementations, consult the firmware documentation
2097 If you need the kernel to boot on SVE-capable hardware with broken
2098 firmware, you may need to say N here until you get your firmware
2099 fixed. Otherwise, you may experience firmware panics or lockups when
2100 booting the kernel. If unsure and you are not observing these
2101 symptoms, you should assume that it is safe to say Y.
2104 bool "ARM Scalable Matrix Extension support"
2106 depends on ARM64_SVE
2108 The Scalable Matrix Extension (SME) is an extension to the AArch64
2109 execution state which utilises a substantial subset of the SVE
2110 instruction set, together with the addition of new architectural
2111 register state capable of holding two dimensional matrix tiles to
2112 enable various matrix operations.
2114 config ARM64_MODULE_PLTS
2115 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2117 select HAVE_MOD_ARCH_SPECIFIC
2119 Allocate PLTs when loading modules so that jumps and calls whose
2120 targets are too far away for their relative offsets to be encoded
2121 in the instructions themselves can be bounced via veneers in the
2122 module's PLT. This allows modules to be allocated in the generic
2123 vmalloc area after the dedicated module memory area has been
2126 When running with address space randomization (KASLR), the module
2127 region itself may be too far away for ordinary relative jumps and
2128 calls, and so in that case, module PLTs are required and cannot be
2131 Specific errata workaround(s) might also force module PLTs to be
2132 enabled (ARM64_ERRATUM_843419).
2134 config ARM64_PSEUDO_NMI
2135 bool "Support for NMI-like interrupts"
2138 Adds support for mimicking Non-Maskable Interrupts through the use of
2139 GIC interrupt priority. This support requires version 3 or later of
2142 This high priority configuration for interrupts needs to be
2143 explicitly enabled by setting the kernel parameter
2144 "irqchip.gicv3_pseudo_nmi" to 1.
2149 config ARM64_DEBUG_PRIORITY_MASKING
2150 bool "Debug interrupt priority masking"
2152 This adds runtime checks to functions enabling/disabling
2153 interrupts when using priority masking. The additional checks verify
2154 the validity of ICC_PMR_EL1 when calling concerned functions.
2157 endif # ARM64_PSEUDO_NMI
2160 bool "Build a relocatable kernel image" if EXPERT
2161 select ARCH_HAS_RELR
2164 This builds the kernel as a Position Independent Executable (PIE),
2165 which retains all relocation metadata required to relocate the
2166 kernel binary at runtime to a different virtual address than the
2167 address it was linked at.
2168 Since AArch64 uses the RELA relocation format, this requires a
2169 relocation pass at runtime even if the kernel is loaded at the
2170 same address it was linked at.
2172 config RANDOMIZE_BASE
2173 bool "Randomize the address of the kernel image"
2174 select ARM64_MODULE_PLTS if MODULES
2177 Randomizes the virtual address at which the kernel image is
2178 loaded, as a security feature that deters exploit attempts
2179 relying on knowledge of the location of kernel internals.
2181 It is the bootloader's job to provide entropy, by passing a
2182 random u64 value in /chosen/kaslr-seed at kernel entry.
2184 When booting via the UEFI stub, it will invoke the firmware's
2185 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2186 to the kernel proper. In addition, it will randomise the physical
2187 location of the kernel Image as well.
2191 config RANDOMIZE_MODULE_REGION_FULL
2192 bool "Randomize the module region over a 2 GB range"
2193 depends on RANDOMIZE_BASE
2196 Randomizes the location of the module region inside a 2 GB window
2197 covering the core kernel. This way, it is less likely for modules
2198 to leak information about the location of core kernel data structures
2199 but it does imply that function calls between modules and the core
2200 kernel will need to be resolved via veneers in the module PLT.
2202 When this option is not set, the module region will be randomized over
2203 a limited range that contains the [_stext, _etext] interval of the
2204 core kernel, so branch relocations are almost always in range unless
2205 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2206 particular case of region exhaustion, modules might be able to fall
2207 back to a larger 2GB area.
2209 config CC_HAVE_STACKPROTECTOR_SYSREG
2210 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2212 config STACKPROTECTOR_PER_TASK
2214 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2216 config UNWIND_PATCH_PAC_INTO_SCS
2217 bool "Enable shadow call stack dynamically using code patching"
2218 # needs Clang with https://reviews.llvm.org/D111780 incorporated
2219 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2220 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2221 depends on SHADOW_CALL_STACK
2222 select UNWIND_TABLES
2225 endmenu # "Kernel Features"
2229 config ARM64_ACPI_PARKING_PROTOCOL
2230 bool "Enable support for the ARM64 ACPI parking protocol"
2233 Enable support for the ARM64 ACPI parking protocol. If disabled
2234 the kernel will not allow booting through the ARM64 ACPI parking
2235 protocol even if the corresponding data is present in the ACPI
2239 string "Default kernel command string"
2242 Provide a set of default command-line options at build time by
2243 entering them here. As a minimum, you should specify the the
2244 root device (e.g. root=/dev/nfs).
2247 prompt "Kernel command line type" if CMDLINE != ""
2248 default CMDLINE_FROM_BOOTLOADER
2250 Choose how the kernel will handle the provided default kernel
2251 command line string.
2253 config CMDLINE_FROM_BOOTLOADER
2254 bool "Use bootloader kernel arguments if available"
2256 Uses the command-line options passed by the boot loader. If
2257 the boot loader doesn't provide any, the default kernel command
2258 string provided in CMDLINE will be used.
2260 config CMDLINE_FORCE
2261 bool "Always use the default kernel command string"
2263 Always use the default kernel command string, even if the boot
2264 loader passes other arguments to the kernel.
2265 This is useful if you cannot or don't want to change the
2266 command-line options your boot loader passes to the kernel.
2274 bool "UEFI runtime support"
2275 depends on OF && !CPU_BIG_ENDIAN
2276 depends on KERNEL_MODE_NEON
2277 select ARCH_SUPPORTS_ACPI
2280 select EFI_PARAMS_FROM_FDT
2281 select EFI_RUNTIME_WRAPPERS
2283 select EFI_GENERIC_STUB
2284 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2287 This option provides support for runtime services provided
2288 by UEFI firmware (such as non-volatile variables, realtime
2289 clock, and platform reset). A UEFI stub is also provided to
2290 allow the kernel to be booted as an EFI application. This
2291 is only useful on systems that have UEFI firmware.
2294 bool "Enable support for SMBIOS (DMI) tables"
2298 This enables SMBIOS/DMI feature for systems.
2300 This option is only useful on systems that have UEFI firmware.
2301 However, even with this option, the resultant kernel should
2302 continue to boot on existing non-UEFI platforms.
2304 endmenu # "Boot options"
2306 menu "Power management options"
2308 source "kernel/power/Kconfig"
2310 config ARCH_HIBERNATION_POSSIBLE
2314 config ARCH_HIBERNATION_HEADER
2316 depends on HIBERNATION
2318 config ARCH_SUSPEND_POSSIBLE
2321 endmenu # "Power management options"
2323 menu "CPU Power Management"
2325 source "drivers/cpuidle/Kconfig"
2327 source "drivers/cpufreq/Kconfig"
2329 endmenu # "CPU Power Management"
2331 source "drivers/acpi/Kconfig"
2333 source "arch/arm64/kvm/Kconfig"