3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
8 select ARCH_HAS_ELF_RANDOMIZE
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_HAS_SG_CHAIN
11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_SUPPORTS_ATOMIC_RMW
14 select ARCH_WANT_OPTIONAL_GPIOLIB
15 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
16 select ARCH_WANT_FRAME_POINTERS
17 select ARCH_HAS_UBSAN_SANITIZE_ALL
21 select AUDIT_ARCH_COMPAT_GENERIC
22 select ARM_GIC_V2M if PCI_MSI
24 select ARM_GIC_V3_ITS if PCI_MSI
26 select BUILDTIME_EXTABLE_SORT
27 select CLONE_BACKWARDS
29 select CPU_PM if (SUSPEND || CPU_IDLE)
30 select DCACHE_WORD_ACCESS
33 select GENERIC_ALLOCATOR
34 select GENERIC_CLOCKEVENTS
35 select GENERIC_CLOCKEVENTS_BROADCAST
36 select GENERIC_CPU_AUTOPROBE
37 select GENERIC_EARLY_IOREMAP
38 select GENERIC_IDLE_POLL_SETUP
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select GENERIC_IRQ_SHOW_LEVEL
42 select GENERIC_PCI_IOMAP
43 select GENERIC_SCHED_CLOCK
44 select GENERIC_SMP_IDLE_THREAD
45 select GENERIC_STRNCPY_FROM_USER
46 select GENERIC_STRNLEN_USER
47 select GENERIC_TIME_VSYSCALL
48 select HANDLE_DOMAIN_IRQ
49 select HARDIRQS_SW_RESEND
50 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
51 select HAVE_ARCH_AUDITSYSCALL
52 select HAVE_ARCH_BITREVERSE
53 select HAVE_ARCH_HUGE_VMAP
54 select HAVE_ARCH_JUMP_LABEL
55 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
57 select HAVE_ARCH_MMAP_RND_BITS
58 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
59 select HAVE_ARCH_SECCOMP_FILTER
60 select HAVE_ARCH_TRACEHOOK
62 select HAVE_C_RECORDMCOUNT
63 select HAVE_CC_STACKPROTECTOR
64 select HAVE_CMPXCHG_DOUBLE
65 select HAVE_CMPXCHG_LOCAL
66 select HAVE_DEBUG_BUGVERBOSE
67 select HAVE_DEBUG_KMEMLEAK
68 select HAVE_DMA_API_DEBUG
69 select HAVE_DMA_CONTIGUOUS
70 select HAVE_DYNAMIC_FTRACE
71 select HAVE_EFFICIENT_UNALIGNED_ACCESS
72 select HAVE_FTRACE_MCOUNT_RECORD
73 select HAVE_FUNCTION_TRACER
74 select HAVE_FUNCTION_GRAPH_TRACER
75 select HAVE_GENERIC_DMA_COHERENT
76 select HAVE_HW_BREAKPOINT if PERF_EVENTS
77 select HAVE_IRQ_TIME_ACCOUNTING
79 select HAVE_MEMBLOCK_NODE_MAP if NUMA
80 select HAVE_PATA_PLATFORM
81 select HAVE_PERF_EVENTS
83 select HAVE_PERF_USER_STACK_DUMP
84 select HAVE_RCU_TABLE_FREE
85 select HAVE_SYSCALL_TRACEPOINTS
86 select IOMMU_DMA if IOMMU_SUPPORT
88 select IRQ_FORCED_THREADING
89 select MODULES_USE_ELF_RELA
92 select OF_EARLY_FLATTREE
93 select OF_RESERVED_MEM
94 select PERF_USE_VMALLOC
99 select SYSCTL_EXCEPTION_TRACE
100 select HAVE_CONTEXT_TRACKING
101 select HAVE_ARM_SMCCC
102 select OF_NUMA if NUMA && OF
104 ARM 64-bit (AArch64) Linux support.
109 config ARCH_PHYS_ADDR_T_64BIT
115 config ARCH_MMAP_RND_BITS_MIN
116 default 14 if ARM64_64K_PAGES
117 default 16 if ARM64_16K_PAGES
120 # max bits determined by the following formula:
121 # VA_BITS - PAGE_SHIFT - 3
122 config ARCH_MMAP_RND_BITS_MAX
123 default 19 if ARM64_VA_BITS=36
124 default 24 if ARM64_VA_BITS=39
125 default 27 if ARM64_VA_BITS=42
126 default 30 if ARM64_VA_BITS=47
127 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
128 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
129 default 33 if ARM64_VA_BITS=48
130 default 14 if ARM64_64K_PAGES
131 default 16 if ARM64_16K_PAGES
134 config ARCH_MMAP_RND_COMPAT_BITS_MIN
135 default 7 if ARM64_64K_PAGES
136 default 9 if ARM64_16K_PAGES
139 config ARCH_MMAP_RND_COMPAT_BITS_MAX
145 config STACKTRACE_SUPPORT
148 config ILLEGAL_POINTER_VALUE
150 default 0xdead000000000000
152 config LOCKDEP_SUPPORT
155 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_XCHGADD_ALGORITHM
165 config GENERIC_BUG_RELATIVE_POINTERS
167 depends on GENERIC_BUG
169 config GENERIC_HWEIGHT
175 config GENERIC_CALIBRATE_DELAY
181 config HAVE_GENERIC_RCU_GUP
184 config ARCH_DMA_ADDR_T_64BIT
187 config NEED_DMA_MAP_STATE
190 config NEED_SG_DMA_LENGTH
202 config KERNEL_MODE_NEON
205 config FIX_EARLYCON_MEM
208 config PGTABLE_LEVELS
210 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
211 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
212 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
213 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
214 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
215 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
217 source "init/Kconfig"
219 source "kernel/Kconfig.freezer"
221 source "arch/arm64/Kconfig.platforms"
228 This feature enables support for PCI bus system. If you say Y
229 here, the kernel will include drivers and infrastructure code
230 to support PCI bus devices.
235 config PCI_DOMAINS_GENERIC
241 source "drivers/pci/Kconfig"
245 menu "Kernel Features"
247 menu "ARM errata workarounds via the alternatives framework"
249 config ARM64_ERRATUM_826319
250 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
253 This option adds an alternative code sequence to work around ARM
254 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
255 AXI master interface and an L2 cache.
257 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
258 and is unable to accept a certain write via this interface, it will
259 not progress on read data presented on the read data channel and the
262 The workaround promotes data cache clean instructions to
263 data cache clean-and-invalidate.
264 Please note that this does not necessarily enable the workaround,
265 as it depends on the alternative framework, which will only patch
266 the kernel if an affected CPU is detected.
270 config ARM64_ERRATUM_827319
271 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
274 This option adds an alternative code sequence to work around ARM
275 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
276 master interface and an L2 cache.
278 Under certain conditions this erratum can cause a clean line eviction
279 to occur at the same time as another transaction to the same address
280 on the AMBA 5 CHI interface, which can cause data corruption if the
281 interconnect reorders the two transactions.
283 The workaround promotes data cache clean instructions to
284 data cache clean-and-invalidate.
285 Please note that this does not necessarily enable the workaround,
286 as it depends on the alternative framework, which will only patch
287 the kernel if an affected CPU is detected.
291 config ARM64_ERRATUM_824069
292 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
295 This option adds an alternative code sequence to work around ARM
296 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
297 to a coherent interconnect.
299 If a Cortex-A53 processor is executing a store or prefetch for
300 write instruction at the same time as a processor in another
301 cluster is executing a cache maintenance operation to the same
302 address, then this erratum might cause a clean cache line to be
303 incorrectly marked as dirty.
305 The workaround promotes data cache clean instructions to
306 data cache clean-and-invalidate.
307 Please note that this option does not necessarily enable the
308 workaround, as it depends on the alternative framework, which will
309 only patch the kernel if an affected CPU is detected.
313 config ARM64_ERRATUM_819472
314 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
317 This option adds an alternative code sequence to work around ARM
318 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
319 present when it is connected to a coherent interconnect.
321 If the processor is executing a load and store exclusive sequence at
322 the same time as a processor in another cluster is executing a cache
323 maintenance operation to the same address, then this erratum might
324 cause data corruption.
326 The workaround promotes data cache clean instructions to
327 data cache clean-and-invalidate.
328 Please note that this does not necessarily enable the workaround,
329 as it depends on the alternative framework, which will only patch
330 the kernel if an affected CPU is detected.
334 config ARM64_ERRATUM_832075
335 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
338 This option adds an alternative code sequence to work around ARM
339 erratum 832075 on Cortex-A57 parts up to r1p2.
341 Affected Cortex-A57 parts might deadlock when exclusive load/store
342 instructions to Write-Back memory are mixed with Device loads.
344 The workaround is to promote device loads to use Load-Acquire
346 Please note that this does not necessarily enable the workaround,
347 as it depends on the alternative framework, which will only patch
348 the kernel if an affected CPU is detected.
352 config ARM64_ERRATUM_834220
353 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
357 This option adds an alternative code sequence to work around ARM
358 erratum 834220 on Cortex-A57 parts up to r1p2.
360 Affected Cortex-A57 parts might report a Stage 2 translation
361 fault as the result of a Stage 1 fault for load crossing a
362 page boundary when there is a permission or device memory
363 alignment fault at Stage 1 and a translation fault at Stage 2.
365 The workaround is to verify that the Stage 1 translation
366 doesn't generate a fault before handling the Stage 2 fault.
367 Please note that this does not necessarily enable the workaround,
368 as it depends on the alternative framework, which will only patch
369 the kernel if an affected CPU is detected.
373 config ARM64_ERRATUM_845719
374 bool "Cortex-A53: 845719: a load might read incorrect data"
378 This option adds an alternative code sequence to work around ARM
379 erratum 845719 on Cortex-A53 parts up to r0p4.
381 When running a compat (AArch32) userspace on an affected Cortex-A53
382 part, a load at EL0 from a virtual address that matches the bottom 32
383 bits of the virtual address used by a recent load at (AArch64) EL1
384 might return incorrect data.
386 The workaround is to write the contextidr_el1 register on exception
387 return to a 32-bit task.
388 Please note that this does not necessarily enable the workaround,
389 as it depends on the alternative framework, which will only patch
390 the kernel if an affected CPU is detected.
394 config ARM64_ERRATUM_843419
395 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
398 select ARM64_MODULE_CMODEL_LARGE
400 This option builds kernel modules using the large memory model in
401 order to avoid the use of the ADRP instruction, which can cause
402 a subsequent memory access to use an incorrect address on Cortex-A53
405 Note that the kernel itself must be linked with a version of ld
406 which fixes potentially affected ADRP instructions through the
411 config CAVIUM_ERRATUM_22375
412 bool "Cavium erratum 22375, 24313"
415 Enable workaround for erratum 22375, 24313.
417 This implements two gicv3-its errata workarounds for ThunderX. Both
418 with small impact affecting only ITS table allocation.
420 erratum 22375: only alloc 8MB table size
421 erratum 24313: ignore memory access type
423 The fixes are in ITS initialization and basically ignore memory access
424 type and table size provided by the TYPER and BASER registers.
428 config CAVIUM_ERRATUM_23154
429 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
432 The gicv3 of ThunderX requires a modified version for
433 reading the IAR status to ensure data synchronization
434 (access to icc_iar1_el1 is not sync'ed before and after).
438 config CAVIUM_ERRATUM_27456
439 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
442 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
443 instructions may cause the icache to become corrupted if it
444 contains data for a non-current ASID. The fix is to
445 invalidate the icache when changing the mm context.
454 default ARM64_4K_PAGES
456 Page size (translation granule) configuration.
458 config ARM64_4K_PAGES
461 This feature enables 4KB pages support.
463 config ARM64_16K_PAGES
466 The system will use 16KB pages support. AArch32 emulation
467 requires applications compiled with 16K (or a multiple of 16K)
470 config ARM64_64K_PAGES
473 This feature enables 64KB pages support (4KB by default)
474 allowing only two levels of page tables and faster TLB
475 look-up. AArch32 emulation requires applications compiled
476 with 64K aligned segments.
481 prompt "Virtual address space size"
482 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
483 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
484 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
486 Allows choosing one of multiple possible virtual address
487 space sizes. The level of translation table is determined by
488 a combination of page size and virtual address space size.
490 config ARM64_VA_BITS_36
491 bool "36-bit" if EXPERT
492 depends on ARM64_16K_PAGES
494 config ARM64_VA_BITS_39
496 depends on ARM64_4K_PAGES
498 config ARM64_VA_BITS_42
500 depends on ARM64_64K_PAGES
502 config ARM64_VA_BITS_47
504 depends on ARM64_16K_PAGES
506 config ARM64_VA_BITS_48
513 default 36 if ARM64_VA_BITS_36
514 default 39 if ARM64_VA_BITS_39
515 default 42 if ARM64_VA_BITS_42
516 default 47 if ARM64_VA_BITS_47
517 default 48 if ARM64_VA_BITS_48
519 config CPU_BIG_ENDIAN
520 bool "Build big-endian kernel"
522 Say Y if you plan on running a kernel in big-endian mode.
525 bool "Multi-core scheduler support"
527 Multi-core scheduler support improves the CPU scheduler's decision
528 making when dealing with multi-core CPU chips at a cost of slightly
529 increased overhead in some places. If unsure say N here.
532 bool "SMT scheduler support"
534 Improves the CPU scheduler's decision making when dealing with
535 MultiThreading at a cost of slightly increased overhead in some
536 places. If unsure say N here.
539 int "Maximum number of CPUs (2-4096)"
541 # These have to remain sorted largest to smallest
545 bool "Support for hot-pluggable CPUs"
546 select GENERIC_IRQ_MIGRATION
548 Say Y here to experiment with turning CPUs off and on. CPUs
549 can be controlled through /sys/devices/system/cpu.
551 # Common NUMA Features
553 bool "Numa Memory Allocation and Scheduler Support"
556 Enable NUMA (Non Uniform Memory Access) support.
558 The kernel will try to allocate memory used by a CPU on the
559 local memory of the CPU and add some more
560 NUMA awareness to the kernel.
563 int "Maximum NUMA Nodes (as a power of 2)"
566 depends on NEED_MULTIPLE_NODES
568 Specify the maximum number of NUMA Nodes available on the target
569 system. Increases memory reserved to accommodate various tables.
571 config USE_PERCPU_NUMA_NODE_ID
575 source kernel/Kconfig.preempt
576 source kernel/Kconfig.hz
578 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
581 config ARCH_HAS_HOLES_MEMORYMODEL
582 def_bool y if SPARSEMEM
584 config ARCH_SPARSEMEM_ENABLE
586 select SPARSEMEM_VMEMMAP_ENABLE
588 config ARCH_SPARSEMEM_DEFAULT
589 def_bool ARCH_SPARSEMEM_ENABLE
591 config ARCH_SELECT_MEMORY_MODEL
592 def_bool ARCH_SPARSEMEM_ENABLE
594 config HAVE_ARCH_PFN_VALID
595 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
597 config HW_PERF_EVENTS
601 config SYS_SUPPORTS_HUGETLBFS
604 config ARCH_WANT_HUGE_PMD_SHARE
605 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
607 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
610 config ARCH_HAS_CACHE_LINE_SIZE
616 bool "Enable seccomp to safely compute untrusted bytecode"
618 This kernel feature is useful for number crunching applications
619 that may need to compute untrusted bytecode during their
620 execution. By using pipes or other transports made available to
621 the process as file descriptors supporting the read/write
622 syscalls, it's possible to isolate those applications in
623 their own address space using seccomp. Once seccomp is
624 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
625 and the task is only allowed to execute a few safe syscalls
626 defined by each seccomp mode.
629 bool "Enable paravirtualization code"
631 This changes the kernel so it can modify itself when it is run
632 under a hypervisor, potentially improving performance significantly
633 over full virtualization.
635 config PARAVIRT_TIME_ACCOUNTING
636 bool "Paravirtual steal time accounting"
640 Select this option to enable fine granularity task steal time
641 accounting. Time spent executing other tasks in parallel with
642 the current vCPU is discounted from the vCPU power. To account for
643 that, there can be a small performance impact.
645 If in doubt, say N here.
652 bool "Xen guest support on ARM64"
653 depends on ARM64 && OF
657 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
659 config FORCE_MAX_ZONEORDER
661 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
662 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
665 The kernel memory allocator divides physically contiguous memory
666 blocks into "zones", where each zone is a power of two number of
667 pages. This option selects the largest power of two that the kernel
668 keeps in the memory allocator. If you need to allocate very large
669 blocks of physically contiguous memory, then you may need to
672 This config option is actually maximum order plus one. For example,
673 a value of 11 means that the largest free memory block is 2^10 pages.
675 We make sure that we can allocate upto a HugePage size for each configuration.
677 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
679 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
680 4M allocations matching the default size used by generic code.
682 menuconfig ARMV8_DEPRECATED
683 bool "Emulate deprecated/obsolete ARMv8 instructions"
686 Legacy software support may require certain instructions
687 that have been deprecated or obsoleted in the architecture.
689 Enable this config to enable selective emulation of these
697 bool "Emulate SWP/SWPB instructions"
699 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
700 they are always undefined. Say Y here to enable software
701 emulation of these instructions for userspace using LDXR/STXR.
703 In some older versions of glibc [<=2.8] SWP is used during futex
704 trylock() operations with the assumption that the code will not
705 be preempted. This invalid assumption may be more likely to fail
706 with SWP emulation enabled, leading to deadlock of the user
709 NOTE: when accessing uncached shared regions, LDXR/STXR rely
710 on an external transaction monitoring block called a global
711 monitor to maintain update atomicity. If your system does not
712 implement a global monitor, this option can cause programs that
713 perform SWP operations to uncached memory to deadlock.
717 config CP15_BARRIER_EMULATION
718 bool "Emulate CP15 Barrier instructions"
720 The CP15 barrier instructions - CP15ISB, CP15DSB, and
721 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
722 strongly recommended to use the ISB, DSB, and DMB
723 instructions instead.
725 Say Y here to enable software emulation of these
726 instructions for AArch32 userspace code. When this option is
727 enabled, CP15 barrier usage is traced which can help
728 identify software that needs updating.
732 config SETEND_EMULATION
733 bool "Emulate SETEND instruction"
735 The SETEND instruction alters the data-endianness of the
736 AArch32 EL0, and is deprecated in ARMv8.
738 Say Y here to enable software emulation of the instruction
739 for AArch32 userspace code.
741 Note: All the cpus on the system must have mixed endian support at EL0
742 for this feature to be enabled. If a new CPU - which doesn't support mixed
743 endian - is hotplugged in after this feature has been enabled, there could
744 be unexpected results in the applications.
749 menu "ARMv8.1 architectural features"
751 config ARM64_HW_AFDBM
752 bool "Support for hardware updates of the Access and Dirty page flags"
755 The ARMv8.1 architecture extensions introduce support for
756 hardware updates of the access and dirty information in page
757 table entries. When enabled in TCR_EL1 (HA and HD bits) on
758 capable processors, accesses to pages with PTE_AF cleared will
759 set this bit instead of raising an access flag fault.
760 Similarly, writes to read-only pages with the DBM bit set will
761 clear the read-only bit (AP[2]) instead of raising a
764 Kernels built with this configuration option enabled continue
765 to work on pre-ARMv8.1 hardware and the performance impact is
766 minimal. If unsure, say Y.
769 bool "Enable support for Privileged Access Never (PAN)"
772 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
773 prevents the kernel or hypervisor from accessing user-space (EL0)
776 Choosing this option will cause any unprotected (not using
777 copy_to_user et al) memory access to fail with a permission fault.
779 The feature is detected at runtime, and will remain as a 'nop'
780 instruction if the cpu does not implement the feature.
782 config ARM64_LSE_ATOMICS
783 bool "Atomic instructions"
785 As part of the Large System Extensions, ARMv8.1 introduces new
786 atomic instructions that are designed specifically to scale in
789 Say Y here to make use of these instructions for the in-kernel
790 atomic routines. This incurs a small overhead on CPUs that do
791 not support these instructions and requires the kernel to be
792 built with binutils >= 2.25.
795 bool "Enable support for Virtualization Host Extensions (VHE)"
798 Virtualization Host Extensions (VHE) allow the kernel to run
799 directly at EL2 (instead of EL1) on processors that support
800 it. This leads to better performance for KVM, as they reduce
801 the cost of the world switch.
803 Selecting this option allows the VHE feature to be detected
804 at runtime, and does not affect processors that do not
805 implement this feature.
809 menu "ARMv8.2 architectural features"
812 bool "Enable support for User Access Override (UAO)"
815 User Access Override (UAO; part of the ARMv8.2 Extensions)
816 causes the 'unprivileged' variant of the load/store instructions to
817 be overriden to be privileged.
819 This option changes get_user() and friends to use the 'unprivileged'
820 variant of the load/store instructions. This ensures that user-space
821 really did have access to the supplied memory. When addr_limit is
822 set to kernel memory the UAO bit will be set, allowing privileged
823 access to kernel memory.
825 Choosing this option will cause copy_to_user() et al to use user-space
828 The feature is detected at runtime, the kernel will use the
829 regular load/store instructions if the cpu does not implement the
834 config ARM64_MODULE_CMODEL_LARGE
837 config ARM64_MODULE_PLTS
839 select ARM64_MODULE_CMODEL_LARGE
840 select HAVE_MOD_ARCH_SPECIFIC
845 This builds the kernel as a Position Independent Executable (PIE),
846 which retains all relocation metadata required to relocate the
847 kernel binary at runtime to a different virtual address than the
848 address it was linked at.
849 Since AArch64 uses the RELA relocation format, this requires a
850 relocation pass at runtime even if the kernel is loaded at the
851 same address it was linked at.
853 config RANDOMIZE_BASE
854 bool "Randomize the address of the kernel image"
855 select ARM64_MODULE_PLTS
858 Randomizes the virtual address at which the kernel image is
859 loaded, as a security feature that deters exploit attempts
860 relying on knowledge of the location of kernel internals.
862 It is the bootloader's job to provide entropy, by passing a
863 random u64 value in /chosen/kaslr-seed at kernel entry.
865 When booting via the UEFI stub, it will invoke the firmware's
866 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
867 to the kernel proper. In addition, it will randomise the physical
868 location of the kernel Image as well.
872 config RANDOMIZE_MODULE_REGION_FULL
873 bool "Randomize the module region independently from the core kernel"
874 depends on RANDOMIZE_BASE
877 Randomizes the location of the module region without considering the
878 location of the core kernel. This way, it is impossible for modules
879 to leak information about the location of core kernel data structures
880 but it does imply that function calls between modules and the core
881 kernel will need to be resolved via veneers in the module PLT.
883 When this option is not set, the module region will be randomized over
884 a limited range that contains the [_stext, _etext] interval of the
885 core kernel, so branch relocations are always in range.
891 config ARM64_ACPI_PARKING_PROTOCOL
892 bool "Enable support for the ARM64 ACPI parking protocol"
895 Enable support for the ARM64 ACPI parking protocol. If disabled
896 the kernel will not allow booting through the ARM64 ACPI parking
897 protocol even if the corresponding data is present in the ACPI
901 string "Default kernel command string"
904 Provide a set of default command-line options at build time by
905 entering them here. As a minimum, you should specify the the
906 root device (e.g. root=/dev/nfs).
909 bool "Always use the default kernel command string"
911 Always use the default kernel command string, even if the boot
912 loader passes other arguments to the kernel.
913 This is useful if you cannot or don't want to change the
914 command-line options your boot loader passes to the kernel.
920 bool "UEFI runtime support"
921 depends on OF && !CPU_BIG_ENDIAN
924 select EFI_PARAMS_FROM_FDT
925 select EFI_RUNTIME_WRAPPERS
930 This option provides support for runtime services provided
931 by UEFI firmware (such as non-volatile variables, realtime
932 clock, and platform reset). A UEFI stub is also provided to
933 allow the kernel to be booted as an EFI application. This
934 is only useful on systems that have UEFI firmware.
937 bool "Enable support for SMBIOS (DMI) tables"
941 This enables SMBIOS/DMI feature for systems.
943 This option is only useful on systems that have UEFI firmware.
944 However, even with this option, the resultant kernel should
945 continue to boot on existing non-UEFI platforms.
949 menu "Userspace binary formats"
951 source "fs/Kconfig.binfmt"
954 bool "Kernel support for 32-bit EL0"
955 depends on ARM64_4K_PAGES || EXPERT
956 select COMPAT_BINFMT_ELF
958 select OLD_SIGSUSPEND3
959 select COMPAT_OLD_SIGACTION
961 This option enables support for a 32-bit EL0 running under a 64-bit
962 kernel at EL1. AArch32-specific components such as system calls,
963 the user helper functions, VFP support and the ptrace interface are
964 handled appropriately by the kernel.
966 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
967 that you will only be able to execute AArch32 binaries that were compiled
968 with page size aligned segments.
970 If you want to execute 32-bit userspace applications, say Y.
972 config SYSVIPC_COMPAT
974 depends on COMPAT && SYSVIPC
978 menu "Power management options"
980 source "kernel/power/Kconfig"
982 config ARCH_SUSPEND_POSSIBLE
987 menu "CPU Power Management"
989 source "drivers/cpuidle/Kconfig"
991 source "drivers/cpufreq/Kconfig"
997 source "drivers/Kconfig"
999 source "drivers/firmware/Kconfig"
1001 source "drivers/acpi/Kconfig"
1005 source "arch/arm64/kvm/Kconfig"
1007 source "arch/arm64/Kconfig.debug"
1009 source "security/Kconfig"
1011 source "crypto/Kconfig"
1013 source "arch/arm64/crypto/Kconfig"
1016 source "lib/Kconfig"