3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_SG_CHAIN
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_USE_CMPXCHG_LOCKREF
8 select ARCH_SUPPORTS_ATOMIC_RMW
9 select ARCH_WANT_OPTIONAL_GPIOLIB
10 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
11 select ARCH_WANT_FRAME_POINTERS
15 select AUDIT_ARCH_COMPAT_GENERIC
17 select BUILDTIME_EXTABLE_SORT
18 select CLONE_BACKWARDS
20 select CPU_PM if (SUSPEND || CPU_IDLE)
21 select DCACHE_WORD_ACCESS
22 select GENERIC_ALLOCATOR
23 select GENERIC_CLOCKEVENTS
24 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
25 select GENERIC_CPU_AUTOPROBE
26 select GENERIC_EARLY_IOREMAP
28 select GENERIC_IRQ_PROBE
29 select GENERIC_IRQ_SHOW
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select GENERIC_TIME_VSYSCALL
35 select HANDLE_DOMAIN_IRQ
36 select HARDIRQS_SW_RESEND
37 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
38 select HAVE_ARCH_AUDITSYSCALL
39 select HAVE_ARCH_JUMP_LABEL
41 select HAVE_ARCH_TRACEHOOK
43 select HAVE_C_RECORDMCOUNT
44 select HAVE_CC_STACKPROTECTOR
45 select HAVE_CMPXCHG_DOUBLE
46 select HAVE_DEBUG_BUGVERBOSE
47 select HAVE_DEBUG_KMEMLEAK
48 select HAVE_DMA_API_DEBUG
50 select HAVE_DMA_CONTIGUOUS
51 select HAVE_DYNAMIC_FTRACE
52 select HAVE_EFFICIENT_UNALIGNED_ACCESS
53 select HAVE_FTRACE_MCOUNT_RECORD
54 select HAVE_FUNCTION_TRACER
55 select HAVE_FUNCTION_GRAPH_TRACER
56 select HAVE_GENERIC_DMA_COHERENT
57 select HAVE_HW_BREAKPOINT if PERF_EVENTS
59 select HAVE_PATA_PLATFORM
60 select HAVE_PERF_EVENTS
62 select HAVE_PERF_USER_STACK_DUMP
63 select HAVE_RCU_TABLE_FREE
64 select HAVE_SYSCALL_TRACEPOINTS
66 select MODULES_USE_ELF_RELA
69 select OF_EARLY_FLATTREE
70 select OF_RESERVED_MEM
71 select PERF_USE_VMALLOC
76 select SYSCTL_EXCEPTION_TRACE
77 select HAVE_CONTEXT_TRACKING
79 ARM 64-bit (AArch64) Linux support.
84 config ARCH_PHYS_ADDR_T_64BIT
93 config STACKTRACE_SUPPORT
96 config LOCKDEP_SUPPORT
99 config TRACE_IRQFLAGS_SUPPORT
102 config RWSEM_XCHGADD_ALGORITHM
105 config GENERIC_HWEIGHT
111 config GENERIC_CALIBRATE_DELAY
117 config HAVE_GENERIC_RCU_GUP
120 config ARCH_DMA_ADDR_T_64BIT
123 config NEED_DMA_MAP_STATE
126 config NEED_SG_DMA_LENGTH
135 config KERNEL_MODE_NEON
138 config FIX_EARLYCON_MEM
141 source "init/Kconfig"
143 source "kernel/Kconfig.freezer"
145 menu "Platform selection"
148 bool "Cavium Inc. Thunder SoC Family"
150 This enables support for Cavium's Thunder Family of SoCs.
153 bool "ARMv8 software model (Versatile Express)"
154 select ARCH_REQUIRE_GPIOLIB
155 select COMMON_CLK_VERSATILE
156 select POWER_RESET_VEXPRESS
157 select VEXPRESS_CONFIG
159 This enables support for the ARMv8 software model (Versatile
163 bool "AppliedMicro X-Gene SOC Family"
165 This enables support for AppliedMicro X-Gene SOC Family
177 This feature enables support for PCI bus system. If you say Y
178 here, the kernel will include drivers and infrastructure code
179 to support PCI bus devices.
184 config PCI_DOMAINS_GENERIC
190 source "drivers/pci/Kconfig"
191 source "drivers/pci/pcie/Kconfig"
192 source "drivers/pci/hotplug/Kconfig"
196 menu "Kernel Features"
198 menu "ARM errata workarounds via the alternatives framework"
200 config ARM64_ERRATUM_826319
201 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
204 This option adds an alternative code sequence to work around ARM
205 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
206 AXI master interface and an L2 cache.
208 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
209 and is unable to accept a certain write via this interface, it will
210 not progress on read data presented on the read data channel and the
213 The workaround promotes data cache clean instructions to
214 data cache clean-and-invalidate.
215 Please note that this does not necessarily enable the workaround,
216 as it depends on the alternative framework, which will only patch
217 the kernel if an affected CPU is detected.
221 config ARM64_ERRATUM_827319
222 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
225 This option adds an alternative code sequence to work around ARM
226 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
227 master interface and an L2 cache.
229 Under certain conditions this erratum can cause a clean line eviction
230 to occur at the same time as another transaction to the same address
231 on the AMBA 5 CHI interface, which can cause data corruption if the
232 interconnect reorders the two transactions.
234 The workaround promotes data cache clean instructions to
235 data cache clean-and-invalidate.
236 Please note that this does not necessarily enable the workaround,
237 as it depends on the alternative framework, which will only patch
238 the kernel if an affected CPU is detected.
242 config ARM64_ERRATUM_824069
243 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
246 This option adds an alternative code sequence to work around ARM
247 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
248 to a coherent interconnect.
250 If a Cortex-A53 processor is executing a store or prefetch for
251 write instruction at the same time as a processor in another
252 cluster is executing a cache maintenance operation to the same
253 address, then this erratum might cause a clean cache line to be
254 incorrectly marked as dirty.
256 The workaround promotes data cache clean instructions to
257 data cache clean-and-invalidate.
258 Please note that this option does not necessarily enable the
259 workaround, as it depends on the alternative framework, which will
260 only patch the kernel if an affected CPU is detected.
264 config ARM64_ERRATUM_819472
265 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
268 This option adds an alternative code sequence to work around ARM
269 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
270 present when it is connected to a coherent interconnect.
272 If the processor is executing a load and store exclusive sequence at
273 the same time as a processor in another cluster is executing a cache
274 maintenance operation to the same address, then this erratum might
275 cause data corruption.
277 The workaround promotes data cache clean instructions to
278 data cache clean-and-invalidate.
279 Please note that this does not necessarily enable the workaround,
280 as it depends on the alternative framework, which will only patch
281 the kernel if an affected CPU is detected.
285 config ARM64_ERRATUM_832075
286 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
289 This option adds an alternative code sequence to work around ARM
290 erratum 832075 on Cortex-A57 parts up to r1p2.
292 Affected Cortex-A57 parts might deadlock when exclusive load/store
293 instructions to Write-Back memory are mixed with Device loads.
295 The workaround is to promote device loads to use Load-Acquire
297 Please note that this does not necessarily enable the workaround,
298 as it depends on the alternative framework, which will only patch
299 the kernel if an affected CPU is detected.
308 default ARM64_4K_PAGES
310 Page size (translation granule) configuration.
312 config ARM64_4K_PAGES
315 This feature enables 4KB pages support.
317 config ARM64_64K_PAGES
320 This feature enables 64KB pages support (4KB by default)
321 allowing only two levels of page tables and faster TLB
322 look-up. AArch32 emulation is not available when this feature
328 prompt "Virtual address space size"
329 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
330 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
332 Allows choosing one of multiple possible virtual address
333 space sizes. The level of translation table is determined by
334 a combination of page size and virtual address space size.
336 config ARM64_VA_BITS_39
338 depends on ARM64_4K_PAGES
340 config ARM64_VA_BITS_42
342 depends on ARM64_64K_PAGES
344 config ARM64_VA_BITS_48
352 default 39 if ARM64_VA_BITS_39
353 default 42 if ARM64_VA_BITS_42
354 default 48 if ARM64_VA_BITS_48
356 config ARM64_PGTABLE_LEVELS
358 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
359 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
360 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
361 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
363 config CPU_BIG_ENDIAN
364 bool "Build big-endian kernel"
366 Say Y if you plan on running a kernel in big-endian mode.
369 bool "Symmetric Multi-Processing"
371 This enables support for systems with more than one CPU. If
372 you say N here, the kernel will run on single and
373 multiprocessor machines, but will use only one CPU of a
374 multiprocessor machine. If you say Y here, the kernel will run
375 on many, but not all, single processor machines. On a single
376 processor machine, the kernel will run faster if you say N
379 If you don't know what to do here, say N.
382 bool "Multi-core scheduler support"
385 Multi-core scheduler support improves the CPU scheduler's decision
386 making when dealing with multi-core CPU chips at a cost of slightly
387 increased overhead in some places. If unsure say N here.
390 bool "SMT scheduler support"
393 Improves the CPU scheduler's decision making when dealing with
394 MultiThreading at a cost of slightly increased overhead in some
395 places. If unsure say N here.
398 int "Maximum number of CPUs (2-64)"
401 # These have to remain sorted largest to smallest
405 bool "Support for hot-pluggable CPUs"
408 Say Y here to experiment with turning CPUs off and on. CPUs
409 can be controlled through /sys/devices/system/cpu.
411 source kernel/Kconfig.preempt
417 config ARCH_HAS_HOLES_MEMORYMODEL
418 def_bool y if SPARSEMEM
420 config ARCH_SPARSEMEM_ENABLE
422 select SPARSEMEM_VMEMMAP_ENABLE
424 config ARCH_SPARSEMEM_DEFAULT
425 def_bool ARCH_SPARSEMEM_ENABLE
427 config ARCH_SELECT_MEMORY_MODEL
428 def_bool ARCH_SPARSEMEM_ENABLE
430 config HAVE_ARCH_PFN_VALID
431 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
433 config HW_PERF_EVENTS
434 bool "Enable hardware performance counter support for perf events"
435 depends on PERF_EVENTS
438 Enable hardware performance counter support for perf events. If
439 disabled, perf events will use software events only.
441 config SYS_SUPPORTS_HUGETLBFS
444 config ARCH_WANT_GENERAL_HUGETLB
447 config ARCH_WANT_HUGE_PMD_SHARE
448 def_bool y if !ARM64_64K_PAGES
450 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
453 config ARCH_HAS_CACHE_LINE_SIZE
463 bool "Xen guest support on ARM64"
464 depends on ARM64 && OF
467 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
469 config FORCE_MAX_ZONEORDER
471 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
474 menuconfig ARMV8_DEPRECATED
475 bool "Emulate deprecated/obsolete ARMv8 instructions"
478 Legacy software support may require certain instructions
479 that have been deprecated or obsoleted in the architecture.
481 Enable this config to enable selective emulation of these
489 bool "Emulate SWP/SWPB instructions"
491 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
492 they are always undefined. Say Y here to enable software
493 emulation of these instructions for userspace using LDXR/STXR.
495 In some older versions of glibc [<=2.8] SWP is used during futex
496 trylock() operations with the assumption that the code will not
497 be preempted. This invalid assumption may be more likely to fail
498 with SWP emulation enabled, leading to deadlock of the user
501 NOTE: when accessing uncached shared regions, LDXR/STXR rely
502 on an external transaction monitoring block called a global
503 monitor to maintain update atomicity. If your system does not
504 implement a global monitor, this option can cause programs that
505 perform SWP operations to uncached memory to deadlock.
509 config CP15_BARRIER_EMULATION
510 bool "Emulate CP15 Barrier instructions"
512 The CP15 barrier instructions - CP15ISB, CP15DSB, and
513 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
514 strongly recommended to use the ISB, DSB, and DMB
515 instructions instead.
517 Say Y here to enable software emulation of these
518 instructions for AArch32 userspace code. When this option is
519 enabled, CP15 barrier usage is traced which can help
520 identify software that needs updating.
531 string "Default kernel command string"
534 Provide a set of default command-line options at build time by
535 entering them here. As a minimum, you should specify the the
536 root device (e.g. root=/dev/nfs).
539 bool "Always use the default kernel command string"
541 Always use the default kernel command string, even if the boot
542 loader passes other arguments to the kernel.
543 This is useful if you cannot or don't want to change the
544 command-line options your boot loader passes to the kernel.
550 bool "UEFI runtime support"
551 depends on OF && !CPU_BIG_ENDIAN
554 select EFI_PARAMS_FROM_FDT
555 select EFI_RUNTIME_WRAPPERS
560 This option provides support for runtime services provided
561 by UEFI firmware (such as non-volatile variables, realtime
562 clock, and platform reset). A UEFI stub is also provided to
563 allow the kernel to be booted as an EFI application. This
564 is only useful on systems that have UEFI firmware.
567 bool "Enable support for SMBIOS (DMI) tables"
571 This enables SMBIOS/DMI feature for systems.
573 This option is only useful on systems that have UEFI firmware.
574 However, even with this option, the resultant kernel should
575 continue to boot on existing non-UEFI platforms.
579 menu "Userspace binary formats"
581 source "fs/Kconfig.binfmt"
584 bool "Kernel support for 32-bit EL0"
585 depends on !ARM64_64K_PAGES
586 select COMPAT_BINFMT_ELF
588 select OLD_SIGSUSPEND3
589 select COMPAT_OLD_SIGACTION
591 This option enables support for a 32-bit EL0 running under a 64-bit
592 kernel at EL1. AArch32-specific components such as system calls,
593 the user helper functions, VFP support and the ptrace interface are
594 handled appropriately by the kernel.
596 If you want to execute 32-bit userspace applications, say Y.
598 config SYSVIPC_COMPAT
600 depends on COMPAT && SYSVIPC
604 menu "Power management options"
606 source "kernel/power/Kconfig"
608 config ARCH_SUSPEND_POSSIBLE
611 config ARM64_CPU_SUSPEND
616 menu "CPU Power Management"
618 source "drivers/cpuidle/Kconfig"
620 source "drivers/cpufreq/Kconfig"
626 source "drivers/Kconfig"
628 source "drivers/firmware/Kconfig"
632 source "arch/arm64/kvm/Kconfig"
634 source "arch/arm64/Kconfig.debug"
636 source "security/Kconfig"
638 source "crypto/Kconfig"
640 source "arch/arm64/crypto/Kconfig"