3 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_GCOV_PROFILE_ALL
7 select ARCH_HAS_SG_CHAIN
8 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
9 select ARCH_USE_CMPXCHG_LOCKREF
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_WANT_OPTIONAL_GPIOLIB
12 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
13 select ARCH_WANT_FRAME_POINTERS
17 select AUDIT_ARCH_COMPAT_GENERIC
18 select ARM_GIC_V2M if PCI_MSI
20 select ARM_GIC_V3_ITS if PCI_MSI
21 select BUILDTIME_EXTABLE_SORT
22 select CLONE_BACKWARDS
24 select CPU_PM if (SUSPEND || CPU_IDLE)
25 select DCACHE_WORD_ACCESS
26 select GENERIC_ALLOCATOR
27 select GENERIC_CLOCKEVENTS
28 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
29 select GENERIC_CPU_AUTOPROBE
30 select GENERIC_EARLY_IOREMAP
31 select GENERIC_IRQ_PROBE
32 select GENERIC_IRQ_SHOW
33 select GENERIC_PCI_IOMAP
34 select GENERIC_SCHED_CLOCK
35 select GENERIC_SMP_IDLE_THREAD
36 select GENERIC_STRNCPY_FROM_USER
37 select GENERIC_STRNLEN_USER
38 select GENERIC_TIME_VSYSCALL
39 select HANDLE_DOMAIN_IRQ
40 select HARDIRQS_SW_RESEND
41 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
42 select HAVE_ARCH_AUDITSYSCALL
43 select HAVE_ARCH_BITREVERSE
44 select HAVE_ARCH_JUMP_LABEL
46 select HAVE_ARCH_SECCOMP_FILTER
47 select HAVE_ARCH_TRACEHOOK
49 select HAVE_C_RECORDMCOUNT
50 select HAVE_CC_STACKPROTECTOR
51 select HAVE_CMPXCHG_DOUBLE
52 select HAVE_DEBUG_BUGVERBOSE
53 select HAVE_DEBUG_KMEMLEAK
54 select HAVE_DMA_API_DEBUG
56 select HAVE_DMA_CONTIGUOUS
57 select HAVE_DYNAMIC_FTRACE
58 select HAVE_EFFICIENT_UNALIGNED_ACCESS
59 select HAVE_FTRACE_MCOUNT_RECORD
60 select HAVE_FUNCTION_TRACER
61 select HAVE_FUNCTION_GRAPH_TRACER
62 select HAVE_GENERIC_DMA_COHERENT
63 select HAVE_HW_BREAKPOINT if PERF_EVENTS
65 select HAVE_PATA_PLATFORM
66 select HAVE_PERF_EVENTS
68 select HAVE_PERF_USER_STACK_DUMP
69 select HAVE_RCU_TABLE_FREE
70 select HAVE_SYSCALL_TRACEPOINTS
72 select MODULES_USE_ELF_RELA
75 select OF_EARLY_FLATTREE
76 select OF_RESERVED_MEM
77 select PERF_USE_VMALLOC
82 select SYSCTL_EXCEPTION_TRACE
83 select HAVE_CONTEXT_TRACKING
85 ARM 64-bit (AArch64) Linux support.
90 config ARCH_PHYS_ADDR_T_64BIT
99 config STACKTRACE_SUPPORT
102 config LOCKDEP_SUPPORT
105 config TRACE_IRQFLAGS_SUPPORT
108 config RWSEM_XCHGADD_ALGORITHM
111 config GENERIC_HWEIGHT
117 config GENERIC_CALIBRATE_DELAY
123 config HAVE_GENERIC_RCU_GUP
126 config ARCH_DMA_ADDR_T_64BIT
129 config NEED_DMA_MAP_STATE
132 config NEED_SG_DMA_LENGTH
141 config KERNEL_MODE_NEON
144 config FIX_EARLYCON_MEM
147 source "init/Kconfig"
149 source "kernel/Kconfig.freezer"
151 menu "Platform selection"
156 This enables support for Samsung Exynos SoC family
159 bool "ARMv8 based Samsung Exynos7"
161 select COMMON_CLK_SAMSUNG
162 select HAVE_S3C2410_WATCHDOG if WATCHDOG
163 select HAVE_S3C_RTC if RTC_CLASS
165 select PINCTRL_EXYNOS
168 This enables support for Samsung Exynos7 SoC family
170 config ARCH_FSL_LS2085A
171 bool "Freescale LS2085A SOC"
173 This enables support for Freescale LS2085A SOC.
176 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
179 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
182 bool "AMD Seattle SoC Family"
184 This enables support for AMD Seattle SOC Family
187 bool "NVIDIA Tegra SoC Family"
188 select ARCH_HAS_RESET_CONTROLLER
189 select ARCH_REQUIRE_GPIOLIB
193 select GENERIC_CLOCKEVENTS
196 select RESET_CONTROLLER
198 This enables support for the NVIDIA Tegra SoC family.
200 config ARCH_TEGRA_132_SOC
201 bool "NVIDIA Tegra132 SoC"
202 depends on ARCH_TEGRA
203 select PINCTRL_TEGRA124
204 select USB_ULPI if USB_PHY
205 select USB_ULPI_VIEWPORT if USB_PHY
207 Enable support for NVIDIA Tegra132 SoC, based on the Denver
208 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
209 but contains an NVIDIA Denver CPU complex in place of
210 Tegra124's "4+1" Cortex-A15 CPU complex.
213 bool "Cavium Inc. Thunder SoC Family"
215 This enables support for Cavium's Thunder Family of SoCs.
218 bool "ARMv8 software model (Versatile Express)"
219 select ARCH_REQUIRE_GPIOLIB
220 select COMMON_CLK_VERSATILE
221 select POWER_RESET_VEXPRESS
222 select VEXPRESS_CONFIG
224 This enables support for the ARMv8 software model (Versatile
228 bool "AppliedMicro X-Gene SOC Family"
230 This enables support for AppliedMicro X-Gene SOC Family
239 This feature enables support for PCI bus system. If you say Y
240 here, the kernel will include drivers and infrastructure code
241 to support PCI bus devices.
246 config PCI_DOMAINS_GENERIC
252 source "drivers/pci/Kconfig"
253 source "drivers/pci/pcie/Kconfig"
254 source "drivers/pci/hotplug/Kconfig"
258 menu "Kernel Features"
260 menu "ARM errata workarounds via the alternatives framework"
262 config ARM64_ERRATUM_826319
263 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
266 This option adds an alternative code sequence to work around ARM
267 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
268 AXI master interface and an L2 cache.
270 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
271 and is unable to accept a certain write via this interface, it will
272 not progress on read data presented on the read data channel and the
275 The workaround promotes data cache clean instructions to
276 data cache clean-and-invalidate.
277 Please note that this does not necessarily enable the workaround,
278 as it depends on the alternative framework, which will only patch
279 the kernel if an affected CPU is detected.
283 config ARM64_ERRATUM_827319
284 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
287 This option adds an alternative code sequence to work around ARM
288 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
289 master interface and an L2 cache.
291 Under certain conditions this erratum can cause a clean line eviction
292 to occur at the same time as another transaction to the same address
293 on the AMBA 5 CHI interface, which can cause data corruption if the
294 interconnect reorders the two transactions.
296 The workaround promotes data cache clean instructions to
297 data cache clean-and-invalidate.
298 Please note that this does not necessarily enable the workaround,
299 as it depends on the alternative framework, which will only patch
300 the kernel if an affected CPU is detected.
304 config ARM64_ERRATUM_824069
305 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
308 This option adds an alternative code sequence to work around ARM
309 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
310 to a coherent interconnect.
312 If a Cortex-A53 processor is executing a store or prefetch for
313 write instruction at the same time as a processor in another
314 cluster is executing a cache maintenance operation to the same
315 address, then this erratum might cause a clean cache line to be
316 incorrectly marked as dirty.
318 The workaround promotes data cache clean instructions to
319 data cache clean-and-invalidate.
320 Please note that this option does not necessarily enable the
321 workaround, as it depends on the alternative framework, which will
322 only patch the kernel if an affected CPU is detected.
326 config ARM64_ERRATUM_819472
327 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
330 This option adds an alternative code sequence to work around ARM
331 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
332 present when it is connected to a coherent interconnect.
334 If the processor is executing a load and store exclusive sequence at
335 the same time as a processor in another cluster is executing a cache
336 maintenance operation to the same address, then this erratum might
337 cause data corruption.
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
347 config ARM64_ERRATUM_832075
348 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
351 This option adds an alternative code sequence to work around ARM
352 erratum 832075 on Cortex-A57 parts up to r1p2.
354 Affected Cortex-A57 parts might deadlock when exclusive load/store
355 instructions to Write-Back memory are mixed with Device loads.
357 The workaround is to promote device loads to use Load-Acquire
359 Please note that this does not necessarily enable the workaround,
360 as it depends on the alternative framework, which will only patch
361 the kernel if an affected CPU is detected.
370 default ARM64_4K_PAGES
372 Page size (translation granule) configuration.
374 config ARM64_4K_PAGES
377 This feature enables 4KB pages support.
379 config ARM64_64K_PAGES
382 This feature enables 64KB pages support (4KB by default)
383 allowing only two levels of page tables and faster TLB
384 look-up. AArch32 emulation is not available when this feature
390 prompt "Virtual address space size"
391 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
392 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
394 Allows choosing one of multiple possible virtual address
395 space sizes. The level of translation table is determined by
396 a combination of page size and virtual address space size.
398 config ARM64_VA_BITS_39
400 depends on ARM64_4K_PAGES
402 config ARM64_VA_BITS_42
404 depends on ARM64_64K_PAGES
406 config ARM64_VA_BITS_48
413 default 39 if ARM64_VA_BITS_39
414 default 42 if ARM64_VA_BITS_42
415 default 48 if ARM64_VA_BITS_48
417 config ARM64_PGTABLE_LEVELS
419 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
420 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
421 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
422 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
424 config CPU_BIG_ENDIAN
425 bool "Build big-endian kernel"
427 Say Y if you plan on running a kernel in big-endian mode.
430 bool "Symmetric Multi-Processing"
432 This enables support for systems with more than one CPU. If
433 you say N here, the kernel will run on single and
434 multiprocessor machines, but will use only one CPU of a
435 multiprocessor machine. If you say Y here, the kernel will run
436 on many, but not all, single processor machines. On a single
437 processor machine, the kernel will run faster if you say N
440 If you don't know what to do here, say N.
443 bool "Multi-core scheduler support"
446 Multi-core scheduler support improves the CPU scheduler's decision
447 making when dealing with multi-core CPU chips at a cost of slightly
448 increased overhead in some places. If unsure say N here.
451 bool "SMT scheduler support"
454 Improves the CPU scheduler's decision making when dealing with
455 MultiThreading at a cost of slightly increased overhead in some
456 places. If unsure say N here.
459 int "Maximum number of CPUs (2-64)"
462 # These have to remain sorted largest to smallest
466 bool "Support for hot-pluggable CPUs"
469 Say Y here to experiment with turning CPUs off and on. CPUs
470 can be controlled through /sys/devices/system/cpu.
472 source kernel/Kconfig.preempt
478 config ARCH_HAS_HOLES_MEMORYMODEL
479 def_bool y if SPARSEMEM
481 config ARCH_SPARSEMEM_ENABLE
483 select SPARSEMEM_VMEMMAP_ENABLE
485 config ARCH_SPARSEMEM_DEFAULT
486 def_bool ARCH_SPARSEMEM_ENABLE
488 config ARCH_SELECT_MEMORY_MODEL
489 def_bool ARCH_SPARSEMEM_ENABLE
491 config HAVE_ARCH_PFN_VALID
492 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
494 config HW_PERF_EVENTS
495 bool "Enable hardware performance counter support for perf events"
496 depends on PERF_EVENTS
499 Enable hardware performance counter support for perf events. If
500 disabled, perf events will use software events only.
502 config SYS_SUPPORTS_HUGETLBFS
505 config ARCH_WANT_GENERAL_HUGETLB
508 config ARCH_WANT_HUGE_PMD_SHARE
509 def_bool y if !ARM64_64K_PAGES
511 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
514 config ARCH_HAS_CACHE_LINE_SIZE
520 bool "Enable seccomp to safely compute untrusted bytecode"
522 This kernel feature is useful for number crunching applications
523 that may need to compute untrusted bytecode during their
524 execution. By using pipes or other transports made available to
525 the process as file descriptors supporting the read/write
526 syscalls, it's possible to isolate those applications in
527 their own address space using seccomp. Once seccomp is
528 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
529 and the task is only allowed to execute a few safe syscalls
530 defined by each seccomp mode.
537 bool "Xen guest support on ARM64"
538 depends on ARM64 && OF
541 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
543 config FORCE_MAX_ZONEORDER
545 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
548 menuconfig ARMV8_DEPRECATED
549 bool "Emulate deprecated/obsolete ARMv8 instructions"
552 Legacy software support may require certain instructions
553 that have been deprecated or obsoleted in the architecture.
555 Enable this config to enable selective emulation of these
563 bool "Emulate SWP/SWPB instructions"
565 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
566 they are always undefined. Say Y here to enable software
567 emulation of these instructions for userspace using LDXR/STXR.
569 In some older versions of glibc [<=2.8] SWP is used during futex
570 trylock() operations with the assumption that the code will not
571 be preempted. This invalid assumption may be more likely to fail
572 with SWP emulation enabled, leading to deadlock of the user
575 NOTE: when accessing uncached shared regions, LDXR/STXR rely
576 on an external transaction monitoring block called a global
577 monitor to maintain update atomicity. If your system does not
578 implement a global monitor, this option can cause programs that
579 perform SWP operations to uncached memory to deadlock.
583 config CP15_BARRIER_EMULATION
584 bool "Emulate CP15 Barrier instructions"
586 The CP15 barrier instructions - CP15ISB, CP15DSB, and
587 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
588 strongly recommended to use the ISB, DSB, and DMB
589 instructions instead.
591 Say Y here to enable software emulation of these
592 instructions for AArch32 userspace code. When this option is
593 enabled, CP15 barrier usage is traced which can help
594 identify software that needs updating.
598 config SETEND_EMULATION
599 bool "Emulate SETEND instruction"
601 The SETEND instruction alters the data-endianness of the
602 AArch32 EL0, and is deprecated in ARMv8.
604 Say Y here to enable software emulation of the instruction
605 for AArch32 userspace code.
607 Note: All the cpus on the system must have mixed endian support at EL0
608 for this feature to be enabled. If a new CPU - which doesn't support mixed
609 endian - is hotplugged in after this feature has been enabled, there could
610 be unexpected results in the applications.
620 string "Default kernel command string"
623 Provide a set of default command-line options at build time by
624 entering them here. As a minimum, you should specify the the
625 root device (e.g. root=/dev/nfs).
628 bool "Always use the default kernel command string"
630 Always use the default kernel command string, even if the boot
631 loader passes other arguments to the kernel.
632 This is useful if you cannot or don't want to change the
633 command-line options your boot loader passes to the kernel.
639 bool "UEFI runtime support"
640 depends on OF && !CPU_BIG_ENDIAN
643 select EFI_PARAMS_FROM_FDT
644 select EFI_RUNTIME_WRAPPERS
649 This option provides support for runtime services provided
650 by UEFI firmware (such as non-volatile variables, realtime
651 clock, and platform reset). A UEFI stub is also provided to
652 allow the kernel to be booted as an EFI application. This
653 is only useful on systems that have UEFI firmware.
656 bool "Enable support for SMBIOS (DMI) tables"
660 This enables SMBIOS/DMI feature for systems.
662 This option is only useful on systems that have UEFI firmware.
663 However, even with this option, the resultant kernel should
664 continue to boot on existing non-UEFI platforms.
668 menu "Userspace binary formats"
670 source "fs/Kconfig.binfmt"
673 bool "Kernel support for 32-bit EL0"
674 depends on !ARM64_64K_PAGES
675 select COMPAT_BINFMT_ELF
677 select OLD_SIGSUSPEND3
678 select COMPAT_OLD_SIGACTION
680 This option enables support for a 32-bit EL0 running under a 64-bit
681 kernel at EL1. AArch32-specific components such as system calls,
682 the user helper functions, VFP support and the ptrace interface are
683 handled appropriately by the kernel.
685 If you want to execute 32-bit userspace applications, say Y.
687 config SYSVIPC_COMPAT
689 depends on COMPAT && SYSVIPC
693 menu "Power management options"
695 source "kernel/power/Kconfig"
697 config ARCH_SUSPEND_POSSIBLE
702 menu "CPU Power Management"
704 source "drivers/cpuidle/Kconfig"
706 source "drivers/cpufreq/Kconfig"
712 source "drivers/Kconfig"
714 source "drivers/firmware/Kconfig"
718 source "arch/arm64/kvm/Kconfig"
720 source "arch/arm64/Kconfig.debug"
722 source "security/Kconfig"
724 source "crypto/Kconfig"
726 source "arch/arm64/crypto/Kconfig"