1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI
9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10 select ACPI_MCFG if (ACPI && PCI)
11 select ACPI_SPCR_TABLE if ACPI
12 select ACPI_PPTT if ACPI
13 select ARCH_HAS_DEBUG_WX
14 select ARCH_BINFMT_ELF_EXTRA_PHDRS
15 select ARCH_BINFMT_ELF_STATE
16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CURRENT_STACK_POINTER
24 select ARCH_HAS_DEBUG_VIRTUAL
25 select ARCH_HAS_DEBUG_VM_PGTABLE
26 select ARCH_HAS_DMA_PREP_COHERENT
27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28 select ARCH_HAS_FAST_MULTIPLIER
29 select ARCH_HAS_FORTIFY_SOURCE
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_HAS_GIGANTIC_PAGE
33 select ARCH_HAS_KEEPINITRD
34 select ARCH_HAS_MEMBARRIER_SYNC_CORE
35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37 select ARCH_HAS_PTE_DEVMAP
38 select ARCH_HAS_PTE_SPECIAL
39 select ARCH_HAS_SETUP_DMA_OPS
40 select ARCH_HAS_SET_DIRECT_MAP
41 select ARCH_HAS_SET_MEMORY
43 select ARCH_HAS_STRICT_KERNEL_RWX
44 select ARCH_HAS_STRICT_MODULE_RWX
45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
46 select ARCH_HAS_SYNC_DMA_FOR_CPU
47 select ARCH_HAS_SYSCALL_WRAPPER
48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
50 select ARCH_HAS_ZONE_DMA_SET if EXPERT
51 select ARCH_HAVE_ELF_PROT
52 select ARCH_HAVE_NMI_SAFE_CMPXCHG
53 select ARCH_HAVE_TRACE_MMIO_ACCESS
54 select ARCH_INLINE_READ_LOCK if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
80 select ARCH_KEEP_MEMBLOCK
81 select ARCH_USE_CMPXCHG_LOCKREF
82 select ARCH_USE_GNU_PROPERTY
83 select ARCH_USE_MEMTEST
84 select ARCH_USE_QUEUED_RWLOCKS
85 select ARCH_USE_QUEUED_SPINLOCKS
86 select ARCH_USE_SYM_ANNOTATIONS
87 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
88 select ARCH_SUPPORTS_HUGETLBFS
89 select ARCH_SUPPORTS_MEMORY_FAILURE
90 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
91 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
92 select ARCH_SUPPORTS_LTO_CLANG_THIN
93 select ARCH_SUPPORTS_CFI_CLANG
94 select ARCH_SUPPORTS_ATOMIC_RMW
95 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
96 select ARCH_SUPPORTS_NUMA_BALANCING
97 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
98 select ARCH_SUPPORTS_PER_VMA_LOCK
99 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
100 select ARCH_WANT_DEFAULT_BPF_JIT
101 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
102 select ARCH_WANT_FRAME_POINTERS
103 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
104 select ARCH_WANT_LD_ORPHAN_WARN
105 select ARCH_WANTS_NO_INSTR
106 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
107 select ARCH_HAS_UBSAN_SANITIZE_ALL
109 select ARM_ARCH_TIMER
111 select AUDIT_ARCH_COMPAT_GENERIC
112 select ARM_GIC_V2M if PCI
114 select ARM_GIC_V3_ITS if PCI
116 select BUILDTIME_TABLE_SORT
117 select CLONE_BACKWARDS
119 select CPU_PM if (SUSPEND || CPU_IDLE)
121 select DCACHE_WORD_ACCESS
122 select DYNAMIC_FTRACE if FUNCTION_TRACER
123 select DMA_DIRECT_REMAP
126 select FUNCTION_ALIGNMENT_4B
127 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
128 select GENERIC_ALLOCATOR
129 select GENERIC_ARCH_TOPOLOGY
130 select GENERIC_CLOCKEVENTS_BROADCAST
131 select GENERIC_CPU_AUTOPROBE
132 select GENERIC_CPU_VULNERABILITIES
133 select GENERIC_EARLY_IOREMAP
134 select GENERIC_IDLE_POLL_SETUP
135 select GENERIC_IOREMAP
136 select GENERIC_IRQ_IPI
137 select GENERIC_IRQ_PROBE
138 select GENERIC_IRQ_SHOW
139 select GENERIC_IRQ_SHOW_LEVEL
140 select GENERIC_LIB_DEVMEM_IS_ALLOWED
141 select GENERIC_PCI_IOMAP
142 select GENERIC_PTDUMP
143 select GENERIC_SCHED_CLOCK
144 select GENERIC_SMP_IDLE_THREAD
145 select GENERIC_TIME_VSYSCALL
146 select GENERIC_GETTIMEOFDAY
147 select GENERIC_VDSO_TIME_NS
148 select HARDIRQS_SW_RESEND
153 select HAVE_ACPI_APEI if (ACPI && EFI)
154 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
155 select HAVE_ARCH_AUDITSYSCALL
156 select HAVE_ARCH_BITREVERSE
157 select HAVE_ARCH_COMPILER_H
158 select HAVE_ARCH_HUGE_VMALLOC
159 select HAVE_ARCH_HUGE_VMAP
160 select HAVE_ARCH_JUMP_LABEL
161 select HAVE_ARCH_JUMP_LABEL_RELATIVE
162 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
163 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
164 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
165 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
166 # Some instrumentation may be unsound, hence EXPERT
167 select HAVE_ARCH_KCSAN if EXPERT
168 select HAVE_ARCH_KFENCE
169 select HAVE_ARCH_KGDB
170 select HAVE_ARCH_MMAP_RND_BITS
171 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
172 select HAVE_ARCH_PREL32_RELOCATIONS
173 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
174 select HAVE_ARCH_SECCOMP_FILTER
175 select HAVE_ARCH_STACKLEAK
176 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
177 select HAVE_ARCH_TRACEHOOK
178 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
179 select HAVE_ARCH_VMAP_STACK
180 select HAVE_ARM_SMCCC
181 select HAVE_ASM_MODVERSIONS
183 select HAVE_C_RECORDMCOUNT
184 select HAVE_CMPXCHG_DOUBLE
185 select HAVE_CMPXCHG_LOCAL
186 select HAVE_CONTEXT_TRACKING_USER
187 select HAVE_DEBUG_KMEMLEAK
188 select HAVE_DMA_CONTIGUOUS
189 select HAVE_DYNAMIC_FTRACE
190 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
191 if $(cc-option,-fpatchable-function-entry=2)
192 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
193 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
194 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
195 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
196 !CC_OPTIMIZE_FOR_SIZE)
197 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
198 if DYNAMIC_FTRACE_WITH_ARGS
199 select HAVE_EFFICIENT_UNALIGNED_ACCESS
201 select HAVE_FTRACE_MCOUNT_RECORD
202 select HAVE_FUNCTION_TRACER
203 select HAVE_FUNCTION_ERROR_INJECTION
204 select HAVE_FUNCTION_GRAPH_TRACER
205 select HAVE_GCC_PLUGINS
206 select HAVE_HW_BREAKPOINT if PERF_EVENTS
207 select HAVE_IOREMAP_PROT
208 select HAVE_IRQ_TIME_ACCOUNTING
211 select HAVE_PERF_EVENTS
212 select HAVE_PERF_REGS
213 select HAVE_PERF_USER_STACK_DUMP
214 select HAVE_PREEMPT_DYNAMIC_KEY
215 select HAVE_REGS_AND_STACK_ACCESS_API
216 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
217 select HAVE_FUNCTION_ARG_ACCESS_API
218 select MMU_GATHER_RCU_TABLE_FREE
220 select HAVE_STACKPROTECTOR
221 select HAVE_SYSCALL_TRACEPOINTS
223 select HAVE_KRETPROBES
224 select HAVE_GENERIC_VDSO
226 select IRQ_FORCED_THREADING
227 select KASAN_VMALLOC if KASAN
228 select MODULES_USE_ELF_RELA
229 select NEED_DMA_MAP_STATE
230 select NEED_SG_DMA_LENGTH
232 select OF_EARLY_FLATTREE
233 select PCI_DOMAINS_GENERIC if PCI
234 select PCI_ECAM if (ACPI && PCI)
235 select PCI_SYSCALL if PCI
240 select SYSCTL_EXCEPTION_TRACE
241 select THREAD_INFO_IN_TASK
242 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
243 select TRACE_IRQFLAGS_SUPPORT
244 select TRACE_IRQFLAGS_NMI_SUPPORT
245 select HAVE_SOFTIRQ_ON_OWN_STACK
247 ARM 64-bit (AArch64) Linux support.
249 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
251 # https://github.com/ClangBuiltLinux/linux/issues/1507
252 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
253 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
255 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
257 depends on $(cc-option,-fpatchable-function-entry=2)
258 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
266 config ARM64_PAGE_SHIFT
268 default 16 if ARM64_64K_PAGES
269 default 14 if ARM64_16K_PAGES
272 config ARM64_CONT_PTE_SHIFT
274 default 5 if ARM64_64K_PAGES
275 default 7 if ARM64_16K_PAGES
278 config ARM64_CONT_PMD_SHIFT
280 default 5 if ARM64_64K_PAGES
281 default 5 if ARM64_16K_PAGES
284 config ARCH_MMAP_RND_BITS_MIN
285 default 14 if ARM64_64K_PAGES
286 default 16 if ARM64_16K_PAGES
289 # max bits determined by the following formula:
290 # VA_BITS - PAGE_SHIFT - 3
291 config ARCH_MMAP_RND_BITS_MAX
292 default 19 if ARM64_VA_BITS=36
293 default 24 if ARM64_VA_BITS=39
294 default 27 if ARM64_VA_BITS=42
295 default 30 if ARM64_VA_BITS=47
296 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
297 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
298 default 33 if ARM64_VA_BITS=48
299 default 14 if ARM64_64K_PAGES
300 default 16 if ARM64_16K_PAGES
303 config ARCH_MMAP_RND_COMPAT_BITS_MIN
304 default 7 if ARM64_64K_PAGES
305 default 9 if ARM64_16K_PAGES
308 config ARCH_MMAP_RND_COMPAT_BITS_MAX
314 config STACKTRACE_SUPPORT
317 config ILLEGAL_POINTER_VALUE
319 default 0xdead000000000000
321 config LOCKDEP_SUPPORT
328 config GENERIC_BUG_RELATIVE_POINTERS
330 depends on GENERIC_BUG
332 config GENERIC_HWEIGHT
338 config GENERIC_CALIBRATE_DELAY
341 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
347 config KERNEL_MODE_NEON
350 config FIX_EARLYCON_MEM
353 config PGTABLE_LEVELS
355 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
356 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
357 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
358 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
359 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
360 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
362 config ARCH_SUPPORTS_UPROBES
365 config ARCH_PROC_KCORE_TEXT
368 config BROKEN_GAS_INST
369 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
371 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
373 # Clang's __builtin_return_adddress() strips the PAC since 12.0.0
374 # https://reviews.llvm.org/D75044
375 default y if CC_IS_CLANG && (CLANG_VERSION >= 120000)
376 # GCC's __builtin_return_address() strips the PAC since 11.1.0,
377 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
378 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
379 default y if CC_IS_GCC && (GCC_VERSION >= 110100)
380 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
381 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000)
382 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000)
385 config KASAN_SHADOW_OFFSET
387 depends on KASAN_GENERIC || KASAN_SW_TAGS
388 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
389 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
390 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
391 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
392 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
393 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
394 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
395 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
396 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
397 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
398 default 0xffffffffffffffff
403 source "arch/arm64/Kconfig.platforms"
405 menu "Kernel Features"
407 menu "ARM errata workarounds via the alternatives framework"
409 config ARM64_WORKAROUND_CLEAN_CACHE
412 config ARM64_ERRATUM_826319
413 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
415 select ARM64_WORKAROUND_CLEAN_CACHE
417 This option adds an alternative code sequence to work around ARM
418 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
419 AXI master interface and an L2 cache.
421 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
422 and is unable to accept a certain write via this interface, it will
423 not progress on read data presented on the read data channel and the
426 The workaround promotes data cache clean instructions to
427 data cache clean-and-invalidate.
428 Please note that this does not necessarily enable the workaround,
429 as it depends on the alternative framework, which will only patch
430 the kernel if an affected CPU is detected.
434 config ARM64_ERRATUM_827319
435 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
437 select ARM64_WORKAROUND_CLEAN_CACHE
439 This option adds an alternative code sequence to work around ARM
440 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
441 master interface and an L2 cache.
443 Under certain conditions this erratum can cause a clean line eviction
444 to occur at the same time as another transaction to the same address
445 on the AMBA 5 CHI interface, which can cause data corruption if the
446 interconnect reorders the two transactions.
448 The workaround promotes data cache clean instructions to
449 data cache clean-and-invalidate.
450 Please note that this does not necessarily enable the workaround,
451 as it depends on the alternative framework, which will only patch
452 the kernel if an affected CPU is detected.
456 config ARM64_ERRATUM_824069
457 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
459 select ARM64_WORKAROUND_CLEAN_CACHE
461 This option adds an alternative code sequence to work around ARM
462 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
463 to a coherent interconnect.
465 If a Cortex-A53 processor is executing a store or prefetch for
466 write instruction at the same time as a processor in another
467 cluster is executing a cache maintenance operation to the same
468 address, then this erratum might cause a clean cache line to be
469 incorrectly marked as dirty.
471 The workaround promotes data cache clean instructions to
472 data cache clean-and-invalidate.
473 Please note that this option does not necessarily enable the
474 workaround, as it depends on the alternative framework, which will
475 only patch the kernel if an affected CPU is detected.
479 config ARM64_ERRATUM_819472
480 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
482 select ARM64_WORKAROUND_CLEAN_CACHE
484 This option adds an alternative code sequence to work around ARM
485 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
486 present when it is connected to a coherent interconnect.
488 If the processor is executing a load and store exclusive sequence at
489 the same time as a processor in another cluster is executing a cache
490 maintenance operation to the same address, then this erratum might
491 cause data corruption.
493 The workaround promotes data cache clean instructions to
494 data cache clean-and-invalidate.
495 Please note that this does not necessarily enable the workaround,
496 as it depends on the alternative framework, which will only patch
497 the kernel if an affected CPU is detected.
501 config ARM64_ERRATUM_832075
502 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
505 This option adds an alternative code sequence to work around ARM
506 erratum 832075 on Cortex-A57 parts up to r1p2.
508 Affected Cortex-A57 parts might deadlock when exclusive load/store
509 instructions to Write-Back memory are mixed with Device loads.
511 The workaround is to promote device loads to use Load-Acquire
513 Please note that this does not necessarily enable the workaround,
514 as it depends on the alternative framework, which will only patch
515 the kernel if an affected CPU is detected.
519 config ARM64_ERRATUM_834220
520 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
524 This option adds an alternative code sequence to work around ARM
525 erratum 834220 on Cortex-A57 parts up to r1p2.
527 Affected Cortex-A57 parts might report a Stage 2 translation
528 fault as the result of a Stage 1 fault for load crossing a
529 page boundary when there is a permission or device memory
530 alignment fault at Stage 1 and a translation fault at Stage 2.
532 The workaround is to verify that the Stage 1 translation
533 doesn't generate a fault before handling the Stage 2 fault.
534 Please note that this does not necessarily enable the workaround,
535 as it depends on the alternative framework, which will only patch
536 the kernel if an affected CPU is detected.
540 config ARM64_ERRATUM_1742098
541 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
545 This option removes the AES hwcap for aarch32 user-space to
546 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
548 Affected parts may corrupt the AES state if an interrupt is
549 taken between a pair of AES instructions. These instructions
550 are only present if the cryptography extensions are present.
551 All software should have a fallback implementation for CPUs
552 that don't implement the cryptography extensions.
556 config ARM64_ERRATUM_845719
557 bool "Cortex-A53: 845719: a load might read incorrect data"
561 This option adds an alternative code sequence to work around ARM
562 erratum 845719 on Cortex-A53 parts up to r0p4.
564 When running a compat (AArch32) userspace on an affected Cortex-A53
565 part, a load at EL0 from a virtual address that matches the bottom 32
566 bits of the virtual address used by a recent load at (AArch64) EL1
567 might return incorrect data.
569 The workaround is to write the contextidr_el1 register on exception
570 return to a 32-bit task.
571 Please note that this does not necessarily enable the workaround,
572 as it depends on the alternative framework, which will only patch
573 the kernel if an affected CPU is detected.
577 config ARM64_ERRATUM_843419
578 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
580 select ARM64_MODULE_PLTS if MODULES
582 This option links the kernel with '--fix-cortex-a53-843419' and
583 enables PLT support to replace certain ADRP instructions, which can
584 cause subsequent memory accesses to use an incorrect address on
585 Cortex-A53 parts up to r0p4.
589 config ARM64_LD_HAS_FIX_ERRATUM_843419
590 def_bool $(ld-option,--fix-cortex-a53-843419)
592 config ARM64_ERRATUM_1024718
593 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
596 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
598 Affected Cortex-A55 cores (all revisions) could cause incorrect
599 update of the hardware dirty bit when the DBM/AP bits are updated
600 without a break-before-make. The workaround is to disable the usage
601 of hardware DBM locally on the affected cores. CPUs not affected by
602 this erratum will continue to use the feature.
606 config ARM64_ERRATUM_1418040
607 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
611 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
612 errata 1188873 and 1418040.
614 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
615 cause register corruption when accessing the timer registers
616 from AArch32 userspace.
620 config ARM64_WORKAROUND_SPECULATIVE_AT
623 config ARM64_ERRATUM_1165522
624 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
626 select ARM64_WORKAROUND_SPECULATIVE_AT
628 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
630 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
631 corrupted TLBs by speculating an AT instruction during a guest
636 config ARM64_ERRATUM_1319367
637 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
639 select ARM64_WORKAROUND_SPECULATIVE_AT
641 This option adds work arounds for ARM Cortex-A57 erratum 1319537
642 and A72 erratum 1319367
644 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
645 speculating an AT instruction during a guest context switch.
649 config ARM64_ERRATUM_1530923
650 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
652 select ARM64_WORKAROUND_SPECULATIVE_AT
654 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
656 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
657 corrupted TLBs by speculating an AT instruction during a guest
662 config ARM64_WORKAROUND_REPEAT_TLBI
665 config ARM64_ERRATUM_2441007
666 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
668 select ARM64_WORKAROUND_REPEAT_TLBI
670 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
672 Under very rare circumstances, affected Cortex-A55 CPUs
673 may not handle a race between a break-before-make sequence on one
674 CPU, and another CPU accessing the same page. This could allow a
675 store to a page that has been unmapped.
677 Work around this by adding the affected CPUs to the list that needs
678 TLB sequences to be done twice.
682 config ARM64_ERRATUM_1286807
683 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
685 select ARM64_WORKAROUND_REPEAT_TLBI
687 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
689 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
690 address for a cacheable mapping of a location is being
691 accessed by a core while another core is remapping the virtual
692 address to a new physical page using the recommended
693 break-before-make sequence, then under very rare circumstances
694 TLBI+DSB completes before a read using the translation being
695 invalidated has been observed by other observers. The
696 workaround repeats the TLBI+DSB operation.
698 config ARM64_ERRATUM_1463225
699 bool "Cortex-A76: Software Step might prevent interrupt recognition"
702 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
704 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
705 of a system call instruction (SVC) can prevent recognition of
706 subsequent interrupts when software stepping is disabled in the
707 exception handler of the system call and either kernel debugging
708 is enabled or VHE is in use.
710 Work around the erratum by triggering a dummy step exception
711 when handling a system call from a task that is being stepped
712 in a VHE configuration of the kernel.
716 config ARM64_ERRATUM_1542419
717 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
720 This option adds a workaround for ARM Neoverse-N1 erratum
723 Affected Neoverse-N1 cores could execute a stale instruction when
724 modified by another CPU. The workaround depends on a firmware
727 Workaround the issue by hiding the DIC feature from EL0. This
728 forces user-space to perform cache maintenance.
732 config ARM64_ERRATUM_1508412
733 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
736 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
738 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
739 of a store-exclusive or read of PAR_EL1 and a load with device or
740 non-cacheable memory attributes. The workaround depends on a firmware
743 KVM guests must also have the workaround implemented or they can
746 Work around the issue by inserting DMB SY barriers around PAR_EL1
747 register reads and warning KVM users. The DMB barrier is sufficient
748 to prevent a speculative PAR_EL1 read.
752 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
755 config ARM64_ERRATUM_2051678
756 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
759 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
760 Affected Cortex-A510 might not respect the ordering rules for
761 hardware update of the page table's dirty bit. The workaround
762 is to not enable the feature on affected CPUs.
766 config ARM64_ERRATUM_2077057
767 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
770 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
771 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
772 expected, but a Pointer Authentication trap is taken instead. The
773 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
774 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
776 This can only happen when EL2 is stepping EL1.
778 When these conditions occur, the SPSR_EL2 value is unchanged from the
779 previous guest entry, and can be restored from the in-memory copy.
783 config ARM64_ERRATUM_2658417
784 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
787 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
788 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
789 BFMMLA or VMMLA instructions in rare circumstances when a pair of
790 A510 CPUs are using shared neon hardware. As the sharing is not
791 discoverable by the kernel, hide the BF16 HWCAP to indicate that
792 user-space should not be using these instructions.
796 config ARM64_ERRATUM_2119858
797 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
799 depends on CORESIGHT_TRBE
800 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
802 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
804 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
805 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
806 the event of a WRAP event.
808 Work around the issue by always making sure we move the TRBPTR_EL1 by
809 256 bytes before enabling the buffer and filling the first 256 bytes of
810 the buffer with ETM ignore packets upon disabling.
814 config ARM64_ERRATUM_2139208
815 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
817 depends on CORESIGHT_TRBE
818 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
820 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
822 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
823 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
824 the event of a WRAP event.
826 Work around the issue by always making sure we move the TRBPTR_EL1 by
827 256 bytes before enabling the buffer and filling the first 256 bytes of
828 the buffer with ETM ignore packets upon disabling.
832 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
835 config ARM64_ERRATUM_2054223
836 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
838 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
840 Enable workaround for ARM Cortex-A710 erratum 2054223
842 Affected cores may fail to flush the trace data on a TSB instruction, when
843 the PE is in trace prohibited state. This will cause losing a few bytes
846 Workaround is to issue two TSB consecutively on affected cores.
850 config ARM64_ERRATUM_2067961
851 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
853 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
855 Enable workaround for ARM Neoverse-N2 erratum 2067961
857 Affected cores may fail to flush the trace data on a TSB instruction, when
858 the PE is in trace prohibited state. This will cause losing a few bytes
861 Workaround is to issue two TSB consecutively on affected cores.
865 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
868 config ARM64_ERRATUM_2253138
869 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
870 depends on CORESIGHT_TRBE
872 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
874 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
876 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
877 for TRBE. Under some conditions, the TRBE might generate a write to the next
878 virtually addressed page following the last page of the TRBE address space
879 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
881 Work around this in the driver by always making sure that there is a
882 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
886 config ARM64_ERRATUM_2224489
887 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
888 depends on CORESIGHT_TRBE
890 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
892 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
894 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
895 for TRBE. Under some conditions, the TRBE might generate a write to the next
896 virtually addressed page following the last page of the TRBE address space
897 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
899 Work around this in the driver by always making sure that there is a
900 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
904 config ARM64_ERRATUM_2441009
905 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
907 select ARM64_WORKAROUND_REPEAT_TLBI
909 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
911 Under very rare circumstances, affected Cortex-A510 CPUs
912 may not handle a race between a break-before-make sequence on one
913 CPU, and another CPU accessing the same page. This could allow a
914 store to a page that has been unmapped.
916 Work around this by adding the affected CPUs to the list that needs
917 TLB sequences to be done twice.
921 config ARM64_ERRATUM_2064142
922 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
923 depends on CORESIGHT_TRBE
926 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
928 Affected Cortex-A510 core might fail to write into system registers after the
929 TRBE has been disabled. Under some conditions after the TRBE has been disabled
930 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
931 and TRBTRG_EL1 will be ignored and will not be effected.
933 Work around this in the driver by executing TSB CSYNC and DSB after collection
934 is stopped and before performing a system register write to one of the affected
939 config ARM64_ERRATUM_2038923
940 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
941 depends on CORESIGHT_TRBE
944 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
946 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
947 prohibited within the CPU. As a result, the trace buffer or trace buffer state
948 might be corrupted. This happens after TRBE buffer has been enabled by setting
949 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
950 execution changes from a context, in which trace is prohibited to one where it
951 isn't, or vice versa. In these mentioned conditions, the view of whether trace
952 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
953 the trace buffer state might be corrupted.
955 Work around this in the driver by preventing an inconsistent view of whether the
956 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
957 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
958 two ISB instructions if no ERET is to take place.
962 config ARM64_ERRATUM_1902691
963 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
964 depends on CORESIGHT_TRBE
967 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
969 Affected Cortex-A510 core might cause trace data corruption, when being written
970 into the memory. Effectively TRBE is broken and hence cannot be used to capture
973 Work around this problem in the driver by just preventing TRBE initialization on
974 affected cpus. The firmware must have disabled the access to TRBE for the kernel
975 on such implementations. This will cover the kernel for any firmware that doesn't
980 config ARM64_ERRATUM_2457168
981 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
982 depends on ARM64_AMU_EXTN
985 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
987 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
988 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
989 incorrectly giving a significantly higher output value.
991 Work around this problem by returning 0 when reading the affected counter in
992 key locations that results in disabling all users of this counter. This effect
993 is the same to firmware disabling affected counters.
997 config ARM64_ERRATUM_2645198
998 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1001 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1003 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1004 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1005 next instruction abort caused by permission fault.
1007 Only user-space does executable to non-executable permission transition via
1008 mprotect() system call. Workaround the problem by doing a break-before-make
1009 TLB invalidation, for all changes to executable user space mappings.
1013 config CAVIUM_ERRATUM_22375
1014 bool "Cavium erratum 22375, 24313"
1017 Enable workaround for errata 22375 and 24313.
1019 This implements two gicv3-its errata workarounds for ThunderX. Both
1020 with a small impact affecting only ITS table allocation.
1022 erratum 22375: only alloc 8MB table size
1023 erratum 24313: ignore memory access type
1025 The fixes are in ITS initialization and basically ignore memory access
1026 type and table size provided by the TYPER and BASER registers.
1030 config CAVIUM_ERRATUM_23144
1031 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1035 ITS SYNC command hang for cross node io and collections/cpu mapping.
1039 config CAVIUM_ERRATUM_23154
1040 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1043 The ThunderX GICv3 implementation requires a modified version for
1044 reading the IAR status to ensure data synchronization
1045 (access to icc_iar1_el1 is not sync'ed before and after).
1047 It also suffers from erratum 38545 (also present on Marvell's
1048 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1049 spuriously presented to the CPU interface.
1053 config CAVIUM_ERRATUM_27456
1054 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1057 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1058 instructions may cause the icache to become corrupted if it
1059 contains data for a non-current ASID. The fix is to
1060 invalidate the icache when changing the mm context.
1064 config CAVIUM_ERRATUM_30115
1065 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1068 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1069 1.2, and T83 Pass 1.0, KVM guest execution may disable
1070 interrupts in host. Trapping both GICv3 group-0 and group-1
1071 accesses sidesteps the issue.
1075 config CAVIUM_TX2_ERRATUM_219
1076 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1079 On Cavium ThunderX2, a load, store or prefetch instruction between a
1080 TTBR update and the corresponding context synchronizing operation can
1081 cause a spurious Data Abort to be delivered to any hardware thread in
1084 Work around the issue by avoiding the problematic code sequence and
1085 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1086 trap handler performs the corresponding register access, skips the
1087 instruction and ensures context synchronization by virtue of the
1092 config FUJITSU_ERRATUM_010001
1093 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1096 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1097 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1098 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1099 This fault occurs under a specific hardware condition when a
1100 load/store instruction performs an address translation using:
1101 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1102 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1103 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1104 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1106 The workaround is to ensure these bits are clear in TCR_ELx.
1107 The workaround only affects the Fujitsu-A64FX.
1111 config HISILICON_ERRATUM_161600802
1112 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1115 The HiSilicon Hip07 SoC uses the wrong redistributor base
1116 when issued ITS commands such as VMOVP and VMAPP, and requires
1117 a 128kB offset to be applied to the target address in this commands.
1121 config QCOM_FALKOR_ERRATUM_1003
1122 bool "Falkor E1003: Incorrect translation due to ASID change"
1125 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1126 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1127 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1128 then only for entries in the walk cache, since the leaf translation
1129 is unchanged. Work around the erratum by invalidating the walk cache
1130 entries for the trampoline before entering the kernel proper.
1132 config QCOM_FALKOR_ERRATUM_1009
1133 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1135 select ARM64_WORKAROUND_REPEAT_TLBI
1137 On Falkor v1, the CPU may prematurely complete a DSB following a
1138 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1139 one more time to fix the issue.
1143 config QCOM_QDF2400_ERRATUM_0065
1144 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1147 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1148 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1149 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1153 config QCOM_FALKOR_ERRATUM_E1041
1154 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1157 Falkor CPU may speculatively fetch instructions from an improper
1158 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1159 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1163 config NVIDIA_CARMEL_CNP_ERRATUM
1164 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1167 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1168 invalidate shared TLB entries installed by a different core, as it would
1169 on standard ARM cores.
1173 config ROCKCHIP_ERRATUM_3588001
1174 bool "Rockchip 3588001: GIC600 can not support shareability attributes"
1177 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1178 This means, that its sharability feature may not be used, even though it
1179 is supported by the IP itself.
1183 config SOCIONEXT_SYNQUACER_PREITS
1184 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1187 Socionext Synquacer SoCs implement a separate h/w block to generate
1188 MSI doorbell writes with non-zero values for the device ID.
1192 endmenu # "ARM errata workarounds via the alternatives framework"
1196 default ARM64_4K_PAGES
1198 Page size (translation granule) configuration.
1200 config ARM64_4K_PAGES
1203 This feature enables 4KB pages support.
1205 config ARM64_16K_PAGES
1208 The system will use 16KB pages support. AArch32 emulation
1209 requires applications compiled with 16K (or a multiple of 16K)
1212 config ARM64_64K_PAGES
1215 This feature enables 64KB pages support (4KB by default)
1216 allowing only two levels of page tables and faster TLB
1217 look-up. AArch32 emulation requires applications compiled
1218 with 64K aligned segments.
1223 prompt "Virtual address space size"
1224 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1225 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1226 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1228 Allows choosing one of multiple possible virtual address
1229 space sizes. The level of translation table is determined by
1230 a combination of page size and virtual address space size.
1232 config ARM64_VA_BITS_36
1233 bool "36-bit" if EXPERT
1234 depends on ARM64_16K_PAGES
1236 config ARM64_VA_BITS_39
1238 depends on ARM64_4K_PAGES
1240 config ARM64_VA_BITS_42
1242 depends on ARM64_64K_PAGES
1244 config ARM64_VA_BITS_47
1246 depends on ARM64_16K_PAGES
1248 config ARM64_VA_BITS_48
1251 config ARM64_VA_BITS_52
1253 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1255 Enable 52-bit virtual addressing for userspace when explicitly
1256 requested via a hint to mmap(). The kernel will also use 52-bit
1257 virtual addresses for its own mappings (provided HW support for
1258 this feature is available, otherwise it reverts to 48-bit).
1260 NOTE: Enabling 52-bit virtual addressing in conjunction with
1261 ARMv8.3 Pointer Authentication will result in the PAC being
1262 reduced from 7 bits to 3 bits, which may have a significant
1263 impact on its susceptibility to brute-force attacks.
1265 If unsure, select 48-bit virtual addressing instead.
1269 config ARM64_FORCE_52BIT
1270 bool "Force 52-bit virtual addresses for userspace"
1271 depends on ARM64_VA_BITS_52 && EXPERT
1273 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1274 to maintain compatibility with older software by providing 48-bit VAs
1275 unless a hint is supplied to mmap.
1277 This configuration option disables the 48-bit compatibility logic, and
1278 forces all userspace addresses to be 52-bit on HW that supports it. One
1279 should only enable this configuration option for stress testing userspace
1280 memory management code. If unsure say N here.
1282 config ARM64_VA_BITS
1284 default 36 if ARM64_VA_BITS_36
1285 default 39 if ARM64_VA_BITS_39
1286 default 42 if ARM64_VA_BITS_42
1287 default 47 if ARM64_VA_BITS_47
1288 default 48 if ARM64_VA_BITS_48
1289 default 52 if ARM64_VA_BITS_52
1292 prompt "Physical address space size"
1293 default ARM64_PA_BITS_48
1295 Choose the maximum physical address range that the kernel will
1298 config ARM64_PA_BITS_48
1301 config ARM64_PA_BITS_52
1302 bool "52-bit (ARMv8.2)"
1303 depends on ARM64_64K_PAGES
1304 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1306 Enable support for a 52-bit physical address space, introduced as
1307 part of the ARMv8.2-LPA extension.
1309 With this enabled, the kernel will also continue to work on CPUs that
1310 do not support ARMv8.2-LPA, but with some added memory overhead (and
1311 minor performance overhead).
1315 config ARM64_PA_BITS
1317 default 48 if ARM64_PA_BITS_48
1318 default 52 if ARM64_PA_BITS_52
1322 default CPU_LITTLE_ENDIAN
1324 Select the endianness of data accesses performed by the CPU. Userspace
1325 applications will need to be compiled and linked for the endianness
1326 that is selected here.
1328 config CPU_BIG_ENDIAN
1329 bool "Build big-endian kernel"
1330 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1332 Say Y if you plan on running a kernel with a big-endian userspace.
1334 config CPU_LITTLE_ENDIAN
1335 bool "Build little-endian kernel"
1337 Say Y if you plan on running a kernel with a little-endian userspace.
1338 This is usually the case for distributions targeting arm64.
1343 bool "Multi-core scheduler support"
1345 Multi-core scheduler support improves the CPU scheduler's decision
1346 making when dealing with multi-core CPU chips at a cost of slightly
1347 increased overhead in some places. If unsure say N here.
1349 config SCHED_CLUSTER
1350 bool "Cluster scheduler support"
1352 Cluster scheduler support improves the CPU scheduler's decision
1353 making when dealing with machines that have clusters of CPUs.
1354 Cluster usually means a couple of CPUs which are placed closely
1355 by sharing mid-level caches, last-level cache tags or internal
1359 bool "SMT scheduler support"
1361 Improves the CPU scheduler's decision making when dealing with
1362 MultiThreading at a cost of slightly increased overhead in some
1363 places. If unsure say N here.
1366 int "Maximum number of CPUs (2-4096)"
1371 bool "Support for hot-pluggable CPUs"
1372 select GENERIC_IRQ_MIGRATION
1374 Say Y here to experiment with turning CPUs off and on. CPUs
1375 can be controlled through /sys/devices/system/cpu.
1377 # Common NUMA Features
1379 bool "NUMA Memory Allocation and Scheduler Support"
1380 select GENERIC_ARCH_NUMA
1381 select ACPI_NUMA if ACPI
1383 select HAVE_SETUP_PER_CPU_AREA
1384 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1385 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1386 select USE_PERCPU_NUMA_NODE_ID
1388 Enable NUMA (Non-Uniform Memory Access) support.
1390 The kernel will try to allocate memory used by a CPU on the
1391 local memory of the CPU and add some more
1392 NUMA awareness to the kernel.
1395 int "Maximum NUMA Nodes (as a power of 2)"
1400 Specify the maximum number of NUMA Nodes available on the target
1401 system. Increases memory reserved to accommodate various tables.
1403 source "kernel/Kconfig.hz"
1405 config ARCH_SPARSEMEM_ENABLE
1407 select SPARSEMEM_VMEMMAP_ENABLE
1408 select SPARSEMEM_VMEMMAP
1410 config HW_PERF_EVENTS
1414 # Supported by clang >= 7.0 or GCC >= 12.0.0
1415 config CC_HAVE_SHADOW_CALL_STACK
1416 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1419 bool "Enable paravirtualization code"
1421 This changes the kernel so it can modify itself when it is run
1422 under a hypervisor, potentially improving performance significantly
1423 over full virtualization.
1425 config PARAVIRT_TIME_ACCOUNTING
1426 bool "Paravirtual steal time accounting"
1429 Select this option to enable fine granularity task steal time
1430 accounting. Time spent executing other tasks in parallel with
1431 the current vCPU is discounted from the vCPU power. To account for
1432 that, there can be a small performance impact.
1434 If in doubt, say N here.
1437 depends on PM_SLEEP_SMP
1439 bool "kexec system call"
1441 kexec is a system call that implements the ability to shutdown your
1442 current kernel, and to start another kernel. It is like a reboot
1443 but it is independent of the system firmware. And like a reboot
1444 you can start any kernel with it, not just Linux.
1447 bool "kexec file based system call"
1449 select HAVE_IMA_KEXEC if IMA
1451 This is new version of kexec system call. This system call is
1452 file based and takes file descriptors as system call argument
1453 for kernel and initramfs as opposed to list of segments as
1454 accepted by previous system call.
1457 bool "Verify kernel signature during kexec_file_load() syscall"
1458 depends on KEXEC_FILE
1460 Select this option to verify a signature with loaded kernel
1461 image. If configured, any attempt of loading a image without
1462 valid signature will fail.
1464 In addition to that option, you need to enable signature
1465 verification for the corresponding kernel image type being
1466 loaded in order for this to work.
1468 config KEXEC_IMAGE_VERIFY_SIG
1469 bool "Enable Image signature verification support"
1471 depends on KEXEC_SIG
1472 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1474 Enable Image signature verification support.
1476 comment "Support for PE file signature verification disabled"
1477 depends on KEXEC_SIG
1478 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1481 bool "Build kdump crash kernel"
1483 Generate crash dump after being started by kexec. This should
1484 be normally only set in special crash dump kernels which are
1485 loaded in the main kernel with kexec-tools into a specially
1486 reserved region and then later executed after a crash by
1489 For more details see Documentation/admin-guide/kdump/kdump.rst
1493 depends on HIBERNATION || KEXEC_CORE
1500 bool "Xen guest support on ARM64"
1501 depends on ARM64 && OF
1505 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1507 # include/linux/mmzone.h requires the following to be true:
1509 # MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1511 # so the maximum value of MAX_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1513 # | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_ORDER | default MAX_ORDER |
1514 # ----+-------------------+--------------+-----------------+--------------------+
1515 # 4K | 27 | 12 | 15 | 10 |
1516 # 16K | 27 | 14 | 13 | 11 |
1517 # 64K | 29 | 16 | 13 | 13 |
1518 config ARCH_FORCE_MAX_ORDER
1519 int "Order of maximal physically contiguous allocations" if EXPERT && (ARM64_4K_PAGES || ARM64_16K_PAGES)
1520 default "13" if ARM64_64K_PAGES
1521 default "11" if ARM64_16K_PAGES
1524 The kernel page allocator limits the size of maximal physically
1525 contiguous allocations. The limit is called MAX_ORDER and it
1526 defines the maximal power of two of number of pages that can be
1527 allocated as a single contiguous block. This option allows
1528 overriding the default setting when ability to allocate very
1529 large blocks of physically contiguous memory is required.
1531 The maximal size of allocation cannot exceed the size of the
1532 section, so the value of MAX_ORDER should satisfy
1534 MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1536 Don't change if unsure.
1538 config UNMAP_KERNEL_AT_EL0
1539 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1542 Speculation attacks against some high-performance processors can
1543 be used to bypass MMU permission checks and leak kernel data to
1544 userspace. This can be defended against by unmapping the kernel
1545 when running in userspace, mapping it back in on exception entry
1546 via a trampoline page in the vector table.
1550 config MITIGATE_SPECTRE_BRANCH_HISTORY
1551 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1554 Speculation attacks against some high-performance processors can
1555 make use of branch history to influence future speculation.
1556 When taking an exception from user-space, a sequence of branches
1557 or a firmware call overwrites the branch history.
1559 config RODATA_FULL_DEFAULT_ENABLED
1560 bool "Apply r/o permissions of VM areas also to their linear aliases"
1563 Apply read-only attributes of VM areas to the linear alias of
1564 the backing pages as well. This prevents code or read-only data
1565 from being modified (inadvertently or intentionally) via another
1566 mapping of the same memory page. This additional enhancement can
1567 be turned off at runtime by passing rodata=[off|on] (and turned on
1568 with rodata=full if this option is set to 'n')
1570 This requires the linear region to be mapped down to pages,
1571 which may adversely affect performance in some cases.
1573 config ARM64_SW_TTBR0_PAN
1574 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1576 Enabling this option prevents the kernel from accessing
1577 user-space memory directly by pointing TTBR0_EL1 to a reserved
1578 zeroed area and reserved ASID. The user access routines
1579 restore the valid TTBR0_EL1 temporarily.
1581 config ARM64_TAGGED_ADDR_ABI
1582 bool "Enable the tagged user addresses syscall ABI"
1585 When this option is enabled, user applications can opt in to a
1586 relaxed ABI via prctl() allowing tagged addresses to be passed
1587 to system calls as pointer arguments. For details, see
1588 Documentation/arm64/tagged-address-abi.rst.
1591 bool "Kernel support for 32-bit EL0"
1592 depends on ARM64_4K_PAGES || EXPERT
1594 select OLD_SIGSUSPEND3
1595 select COMPAT_OLD_SIGACTION
1597 This option enables support for a 32-bit EL0 running under a 64-bit
1598 kernel at EL1. AArch32-specific components such as system calls,
1599 the user helper functions, VFP support and the ptrace interface are
1600 handled appropriately by the kernel.
1602 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1603 that you will only be able to execute AArch32 binaries that were compiled
1604 with page size aligned segments.
1606 If you want to execute 32-bit userspace applications, say Y.
1610 config KUSER_HELPERS
1611 bool "Enable kuser helpers page for 32-bit applications"
1614 Warning: disabling this option may break 32-bit user programs.
1616 Provide kuser helpers to compat tasks. The kernel provides
1617 helper code to userspace in read only form at a fixed location
1618 to allow userspace to be independent of the CPU type fitted to
1619 the system. This permits binaries to be run on ARMv4 through
1620 to ARMv8 without modification.
1622 See Documentation/arm/kernel_user_helpers.rst for details.
1624 However, the fixed address nature of these helpers can be used
1625 by ROP (return orientated programming) authors when creating
1628 If all of the binaries and libraries which run on your platform
1629 are built specifically for your platform, and make no use of
1630 these helpers, then you can turn this option off to hinder
1631 such exploits. However, in that case, if a binary or library
1632 relying on those helpers is run, it will not function correctly.
1634 Say N here only if you are absolutely certain that you do not
1635 need these helpers; otherwise, the safe option is to say Y.
1638 bool "Enable vDSO for 32-bit applications"
1639 depends on !CPU_BIG_ENDIAN
1640 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1641 select GENERIC_COMPAT_VDSO
1644 Place in the process address space of 32-bit applications an
1645 ELF shared object providing fast implementations of gettimeofday
1648 You must have a 32-bit build of glibc 2.22 or later for programs
1649 to seamlessly take advantage of this.
1651 config THUMB2_COMPAT_VDSO
1652 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1653 depends on COMPAT_VDSO
1656 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1657 otherwise with '-marm'.
1659 config COMPAT_ALIGNMENT_FIXUPS
1660 bool "Fix up misaligned multi-word loads and stores in user space"
1662 menuconfig ARMV8_DEPRECATED
1663 bool "Emulate deprecated/obsolete ARMv8 instructions"
1666 Legacy software support may require certain instructions
1667 that have been deprecated or obsoleted in the architecture.
1669 Enable this config to enable selective emulation of these
1676 config SWP_EMULATION
1677 bool "Emulate SWP/SWPB instructions"
1679 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1680 they are always undefined. Say Y here to enable software
1681 emulation of these instructions for userspace using LDXR/STXR.
1682 This feature can be controlled at runtime with the abi.swp
1683 sysctl which is disabled by default.
1685 In some older versions of glibc [<=2.8] SWP is used during futex
1686 trylock() operations with the assumption that the code will not
1687 be preempted. This invalid assumption may be more likely to fail
1688 with SWP emulation enabled, leading to deadlock of the user
1691 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1692 on an external transaction monitoring block called a global
1693 monitor to maintain update atomicity. If your system does not
1694 implement a global monitor, this option can cause programs that
1695 perform SWP operations to uncached memory to deadlock.
1699 config CP15_BARRIER_EMULATION
1700 bool "Emulate CP15 Barrier instructions"
1702 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1703 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1704 strongly recommended to use the ISB, DSB, and DMB
1705 instructions instead.
1707 Say Y here to enable software emulation of these
1708 instructions for AArch32 userspace code. When this option is
1709 enabled, CP15 barrier usage is traced which can help
1710 identify software that needs updating. This feature can be
1711 controlled at runtime with the abi.cp15_barrier sysctl.
1715 config SETEND_EMULATION
1716 bool "Emulate SETEND instruction"
1718 The SETEND instruction alters the data-endianness of the
1719 AArch32 EL0, and is deprecated in ARMv8.
1721 Say Y here to enable software emulation of the instruction
1722 for AArch32 userspace code. This feature can be controlled
1723 at runtime with the abi.setend sysctl.
1725 Note: All the cpus on the system must have mixed endian support at EL0
1726 for this feature to be enabled. If a new CPU - which doesn't support mixed
1727 endian - is hotplugged in after this feature has been enabled, there could
1728 be unexpected results in the applications.
1731 endif # ARMV8_DEPRECATED
1735 menu "ARMv8.1 architectural features"
1737 config ARM64_HW_AFDBM
1738 bool "Support for hardware updates of the Access and Dirty page flags"
1741 The ARMv8.1 architecture extensions introduce support for
1742 hardware updates of the access and dirty information in page
1743 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1744 capable processors, accesses to pages with PTE_AF cleared will
1745 set this bit instead of raising an access flag fault.
1746 Similarly, writes to read-only pages with the DBM bit set will
1747 clear the read-only bit (AP[2]) instead of raising a
1750 Kernels built with this configuration option enabled continue
1751 to work on pre-ARMv8.1 hardware and the performance impact is
1752 minimal. If unsure, say Y.
1755 bool "Enable support for Privileged Access Never (PAN)"
1758 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1759 prevents the kernel or hypervisor from accessing user-space (EL0)
1762 Choosing this option will cause any unprotected (not using
1763 copy_to_user et al) memory access to fail with a permission fault.
1765 The feature is detected at runtime, and will remain as a 'nop'
1766 instruction if the cpu does not implement the feature.
1769 def_bool $(as-instr,.arch_extension rcpc)
1771 config AS_HAS_LSE_ATOMICS
1772 def_bool $(as-instr,.arch_extension lse)
1774 config ARM64_LSE_ATOMICS
1776 default ARM64_USE_LSE_ATOMICS
1777 depends on AS_HAS_LSE_ATOMICS
1779 config ARM64_USE_LSE_ATOMICS
1780 bool "Atomic instructions"
1783 As part of the Large System Extensions, ARMv8.1 introduces new
1784 atomic instructions that are designed specifically to scale in
1787 Say Y here to make use of these instructions for the in-kernel
1788 atomic routines. This incurs a small overhead on CPUs that do
1789 not support these instructions and requires the kernel to be
1790 built with binutils >= 2.25 in order for the new instructions
1793 endmenu # "ARMv8.1 architectural features"
1795 menu "ARMv8.2 architectural features"
1797 config AS_HAS_ARMV8_2
1798 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1801 def_bool $(as-instr,.arch armv8.2-a+sha3)
1804 bool "Enable support for persistent memory"
1805 select ARCH_HAS_PMEM_API
1806 select ARCH_HAS_UACCESS_FLUSHCACHE
1808 Say Y to enable support for the persistent memory API based on the
1809 ARMv8.2 DCPoP feature.
1811 The feature is detected at runtime, and the kernel will use DC CVAC
1812 operations if DC CVAP is not supported (following the behaviour of
1813 DC CVAP itself if the system does not define a point of persistence).
1815 config ARM64_RAS_EXTN
1816 bool "Enable support for RAS CPU Extensions"
1819 CPUs that support the Reliability, Availability and Serviceability
1820 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1821 errors, classify them and report them to software.
1823 On CPUs with these extensions system software can use additional
1824 barriers to determine if faults are pending and read the
1825 classification from a new set of registers.
1827 Selecting this feature will allow the kernel to use these barriers
1828 and access the new registers if the system supports the extension.
1829 Platform RAS features may additionally depend on firmware support.
1832 bool "Enable support for Common Not Private (CNP) translations"
1834 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1836 Common Not Private (CNP) allows translation table entries to
1837 be shared between different PEs in the same inner shareable
1838 domain, so the hardware can use this fact to optimise the
1839 caching of such entries in the TLB.
1841 Selecting this option allows the CNP feature to be detected
1842 at runtime, and does not affect PEs that do not implement
1845 endmenu # "ARMv8.2 architectural features"
1847 menu "ARMv8.3 architectural features"
1849 config ARM64_PTR_AUTH
1850 bool "Enable support for pointer authentication"
1853 Pointer authentication (part of the ARMv8.3 Extensions) provides
1854 instructions for signing and authenticating pointers against secret
1855 keys, which can be used to mitigate Return Oriented Programming (ROP)
1858 This option enables these instructions at EL0 (i.e. for userspace).
1859 Choosing this option will cause the kernel to initialise secret keys
1860 for each process at exec() time, with these keys being
1861 context-switched along with the process.
1863 The feature is detected at runtime. If the feature is not present in
1864 hardware it will not be advertised to userspace/KVM guest nor will it
1867 If the feature is present on the boot CPU but not on a late CPU, then
1868 the late CPU will be parked. Also, if the boot CPU does not have
1869 address auth and the late CPU has then the late CPU will still boot
1870 but with the feature disabled. On such a system, this option should
1873 config ARM64_PTR_AUTH_KERNEL
1874 bool "Use pointer authentication for kernel"
1876 depends on ARM64_PTR_AUTH
1877 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1878 # Modern compilers insert a .note.gnu.property section note for PAC
1879 # which is only understood by binutils starting with version 2.33.1.
1880 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1881 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1882 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1884 If the compiler supports the -mbranch-protection or
1885 -msign-return-address flag (e.g. GCC 7 or later), then this option
1886 will cause the kernel itself to be compiled with return address
1887 protection. In this case, and if the target hardware is known to
1888 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1889 disabled with minimal loss of protection.
1891 This feature works with FUNCTION_GRAPH_TRACER option only if
1892 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1894 config CC_HAS_BRANCH_PROT_PAC_RET
1895 # GCC 9 or later, clang 8 or later
1896 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1898 config CC_HAS_SIGN_RETURN_ADDRESS
1900 def_bool $(cc-option,-msign-return-address=all)
1902 config AS_HAS_ARMV8_3
1903 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1905 config AS_HAS_CFI_NEGATE_RA_STATE
1906 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1908 endmenu # "ARMv8.3 architectural features"
1910 menu "ARMv8.4 architectural features"
1912 config ARM64_AMU_EXTN
1913 bool "Enable support for the Activity Monitors Unit CPU extension"
1916 The activity monitors extension is an optional extension introduced
1917 by the ARMv8.4 CPU architecture. This enables support for version 1
1918 of the activity monitors architecture, AMUv1.
1920 To enable the use of this extension on CPUs that implement it, say Y.
1922 Note that for architectural reasons, firmware _must_ implement AMU
1923 support when running on CPUs that present the activity monitors
1924 extension. The required support is present in:
1925 * Version 1.5 and later of the ARM Trusted Firmware
1927 For kernels that have this configuration enabled but boot with broken
1928 firmware, you may need to say N here until the firmware is fixed.
1929 Otherwise you may experience firmware panics or lockups when
1930 accessing the counter registers. Even if you are not observing these
1931 symptoms, the values returned by the register reads might not
1932 correctly reflect reality. Most commonly, the value read will be 0,
1933 indicating that the counter is not enabled.
1935 config AS_HAS_ARMV8_4
1936 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1938 config ARM64_TLB_RANGE
1939 bool "Enable support for tlbi range feature"
1941 depends on AS_HAS_ARMV8_4
1943 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1944 range of input addresses.
1946 The feature introduces new assembly instructions, and they were
1947 support when binutils >= 2.30.
1949 endmenu # "ARMv8.4 architectural features"
1951 menu "ARMv8.5 architectural features"
1953 config AS_HAS_ARMV8_5
1954 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1957 bool "Branch Target Identification support"
1960 Branch Target Identification (part of the ARMv8.5 Extensions)
1961 provides a mechanism to limit the set of locations to which computed
1962 branch instructions such as BR or BLR can jump.
1964 To make use of BTI on CPUs that support it, say Y.
1966 BTI is intended to provide complementary protection to other control
1967 flow integrity protection mechanisms, such as the Pointer
1968 authentication mechanism provided as part of the ARMv8.3 Extensions.
1969 For this reason, it does not make sense to enable this option without
1970 also enabling support for pointer authentication. Thus, when
1971 enabling this option you should also select ARM64_PTR_AUTH=y.
1973 Userspace binaries must also be specifically compiled to make use of
1974 this mechanism. If you say N here or the hardware does not support
1975 BTI, such binaries can still run, but you get no additional
1976 enforcement of branch destinations.
1978 config ARM64_BTI_KERNEL
1979 bool "Use Branch Target Identification for kernel"
1981 depends on ARM64_BTI
1982 depends on ARM64_PTR_AUTH_KERNEL
1983 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1984 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1985 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1986 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1987 depends on !CC_IS_GCC
1988 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1989 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1990 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1992 Build the kernel with Branch Target Identification annotations
1993 and enable enforcement of this for kernel code. When this option
1994 is enabled and the system supports BTI all kernel code including
1995 modular code must have BTI enabled.
1997 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1998 # GCC 9 or later, clang 8 or later
1999 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2002 bool "Enable support for E0PD"
2005 E0PD (part of the ARMv8.5 extensions) allows us to ensure
2006 that EL0 accesses made via TTBR1 always fault in constant time,
2007 providing similar benefits to KASLR as those provided by KPTI, but
2008 with lower overhead and without disrupting legitimate access to
2009 kernel memory such as SPE.
2011 This option enables E0PD for TTBR1 where available.
2013 config ARM64_AS_HAS_MTE
2014 # Initial support for MTE went in binutils 2.32.0, checked with
2015 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2016 # as a late addition to the final architecture spec (LDGM/STGM)
2017 # is only supported in the newer 2.32.x and 2.33 binutils
2018 # versions, hence the extra "stgm" instruction check below.
2019 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2022 bool "Memory Tagging Extension support"
2024 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2025 depends on AS_HAS_ARMV8_5
2026 depends on AS_HAS_LSE_ATOMICS
2027 # Required for tag checking in the uaccess routines
2028 depends on ARM64_PAN
2029 select ARCH_HAS_SUBPAGE_FAULTS
2030 select ARCH_USES_HIGH_VMA_FLAGS
2031 select ARCH_USES_PG_ARCH_X
2033 Memory Tagging (part of the ARMv8.5 Extensions) provides
2034 architectural support for run-time, always-on detection of
2035 various classes of memory error to aid with software debugging
2036 to eliminate vulnerabilities arising from memory-unsafe
2039 This option enables the support for the Memory Tagging
2040 Extension at EL0 (i.e. for userspace).
2042 Selecting this option allows the feature to be detected at
2043 runtime. Any secondary CPU not implementing this feature will
2044 not be allowed a late bring-up.
2046 Userspace binaries that want to use this feature must
2047 explicitly opt in. The mechanism for the userspace is
2050 Documentation/arm64/memory-tagging-extension.rst.
2052 endmenu # "ARMv8.5 architectural features"
2054 menu "ARMv8.7 architectural features"
2057 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2059 depends on ARM64_PAN
2061 Enhanced Privileged Access Never (EPAN) allows Privileged
2062 Access Never to be used with Execute-only mappings.
2064 The feature is detected at runtime, and will remain disabled
2065 if the cpu does not implement the feature.
2066 endmenu # "ARMv8.7 architectural features"
2069 bool "ARM Scalable Vector Extension support"
2072 The Scalable Vector Extension (SVE) is an extension to the AArch64
2073 execution state which complements and extends the SIMD functionality
2074 of the base architecture to support much larger vectors and to enable
2075 additional vectorisation opportunities.
2077 To enable use of this extension on CPUs that implement it, say Y.
2079 On CPUs that support the SVE2 extensions, this option will enable
2082 Note that for architectural reasons, firmware _must_ implement SVE
2083 support when running on SVE capable hardware. The required support
2086 * version 1.5 and later of the ARM Trusted Firmware
2087 * the AArch64 boot wrapper since commit 5e1261e08abf
2088 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2090 For other firmware implementations, consult the firmware documentation
2093 If you need the kernel to boot on SVE-capable hardware with broken
2094 firmware, you may need to say N here until you get your firmware
2095 fixed. Otherwise, you may experience firmware panics or lockups when
2096 booting the kernel. If unsure and you are not observing these
2097 symptoms, you should assume that it is safe to say Y.
2100 bool "ARM Scalable Matrix Extension support"
2102 depends on ARM64_SVE
2104 The Scalable Matrix Extension (SME) is an extension to the AArch64
2105 execution state which utilises a substantial subset of the SVE
2106 instruction set, together with the addition of new architectural
2107 register state capable of holding two dimensional matrix tiles to
2108 enable various matrix operations.
2110 config ARM64_MODULE_PLTS
2111 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2113 select HAVE_MOD_ARCH_SPECIFIC
2115 Allocate PLTs when loading modules so that jumps and calls whose
2116 targets are too far away for their relative offsets to be encoded
2117 in the instructions themselves can be bounced via veneers in the
2118 module's PLT. This allows modules to be allocated in the generic
2119 vmalloc area after the dedicated module memory area has been
2122 When running with address space randomization (KASLR), the module
2123 region itself may be too far away for ordinary relative jumps and
2124 calls, and so in that case, module PLTs are required and cannot be
2127 Specific errata workaround(s) might also force module PLTs to be
2128 enabled (ARM64_ERRATUM_843419).
2130 config ARM64_PSEUDO_NMI
2131 bool "Support for NMI-like interrupts"
2134 Adds support for mimicking Non-Maskable Interrupts through the use of
2135 GIC interrupt priority. This support requires version 3 or later of
2138 This high priority configuration for interrupts needs to be
2139 explicitly enabled by setting the kernel parameter
2140 "irqchip.gicv3_pseudo_nmi" to 1.
2145 config ARM64_DEBUG_PRIORITY_MASKING
2146 bool "Debug interrupt priority masking"
2148 This adds runtime checks to functions enabling/disabling
2149 interrupts when using priority masking. The additional checks verify
2150 the validity of ICC_PMR_EL1 when calling concerned functions.
2153 endif # ARM64_PSEUDO_NMI
2156 bool "Build a relocatable kernel image" if EXPERT
2157 select ARCH_HAS_RELR
2160 This builds the kernel as a Position Independent Executable (PIE),
2161 which retains all relocation metadata required to relocate the
2162 kernel binary at runtime to a different virtual address than the
2163 address it was linked at.
2164 Since AArch64 uses the RELA relocation format, this requires a
2165 relocation pass at runtime even if the kernel is loaded at the
2166 same address it was linked at.
2168 config RANDOMIZE_BASE
2169 bool "Randomize the address of the kernel image"
2170 select ARM64_MODULE_PLTS if MODULES
2173 Randomizes the virtual address at which the kernel image is
2174 loaded, as a security feature that deters exploit attempts
2175 relying on knowledge of the location of kernel internals.
2177 It is the bootloader's job to provide entropy, by passing a
2178 random u64 value in /chosen/kaslr-seed at kernel entry.
2180 When booting via the UEFI stub, it will invoke the firmware's
2181 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2182 to the kernel proper. In addition, it will randomise the physical
2183 location of the kernel Image as well.
2187 config RANDOMIZE_MODULE_REGION_FULL
2188 bool "Randomize the module region over a 2 GB range"
2189 depends on RANDOMIZE_BASE
2192 Randomizes the location of the module region inside a 2 GB window
2193 covering the core kernel. This way, it is less likely for modules
2194 to leak information about the location of core kernel data structures
2195 but it does imply that function calls between modules and the core
2196 kernel will need to be resolved via veneers in the module PLT.
2198 When this option is not set, the module region will be randomized over
2199 a limited range that contains the [_stext, _etext] interval of the
2200 core kernel, so branch relocations are almost always in range unless
2201 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2202 particular case of region exhaustion, modules might be able to fall
2203 back to a larger 2GB area.
2205 config CC_HAVE_STACKPROTECTOR_SYSREG
2206 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2208 config STACKPROTECTOR_PER_TASK
2210 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2212 config UNWIND_PATCH_PAC_INTO_SCS
2213 bool "Enable shadow call stack dynamically using code patching"
2214 # needs Clang with https://reviews.llvm.org/D111780 incorporated
2215 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2216 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2217 depends on SHADOW_CALL_STACK
2218 select UNWIND_TABLES
2221 endmenu # "Kernel Features"
2225 config ARM64_ACPI_PARKING_PROTOCOL
2226 bool "Enable support for the ARM64 ACPI parking protocol"
2229 Enable support for the ARM64 ACPI parking protocol. If disabled
2230 the kernel will not allow booting through the ARM64 ACPI parking
2231 protocol even if the corresponding data is present in the ACPI
2235 string "Default kernel command string"
2238 Provide a set of default command-line options at build time by
2239 entering them here. As a minimum, you should specify the the
2240 root device (e.g. root=/dev/nfs).
2243 prompt "Kernel command line type" if CMDLINE != ""
2244 default CMDLINE_FROM_BOOTLOADER
2246 Choose how the kernel will handle the provided default kernel
2247 command line string.
2249 config CMDLINE_FROM_BOOTLOADER
2250 bool "Use bootloader kernel arguments if available"
2252 Uses the command-line options passed by the boot loader. If
2253 the boot loader doesn't provide any, the default kernel command
2254 string provided in CMDLINE will be used.
2256 config CMDLINE_FORCE
2257 bool "Always use the default kernel command string"
2259 Always use the default kernel command string, even if the boot
2260 loader passes other arguments to the kernel.
2261 This is useful if you cannot or don't want to change the
2262 command-line options your boot loader passes to the kernel.
2270 bool "UEFI runtime support"
2271 depends on OF && !CPU_BIG_ENDIAN
2272 depends on KERNEL_MODE_NEON
2273 select ARCH_SUPPORTS_ACPI
2276 select EFI_PARAMS_FROM_FDT
2277 select EFI_RUNTIME_WRAPPERS
2279 select EFI_GENERIC_STUB
2280 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2283 This option provides support for runtime services provided
2284 by UEFI firmware (such as non-volatile variables, realtime
2285 clock, and platform reset). A UEFI stub is also provided to
2286 allow the kernel to be booted as an EFI application. This
2287 is only useful on systems that have UEFI firmware.
2290 bool "Enable support for SMBIOS (DMI) tables"
2294 This enables SMBIOS/DMI feature for systems.
2296 This option is only useful on systems that have UEFI firmware.
2297 However, even with this option, the resultant kernel should
2298 continue to boot on existing non-UEFI platforms.
2300 endmenu # "Boot options"
2302 menu "Power management options"
2304 source "kernel/power/Kconfig"
2306 config ARCH_HIBERNATION_POSSIBLE
2310 config ARCH_HIBERNATION_HEADER
2312 depends on HIBERNATION
2314 config ARCH_SUSPEND_POSSIBLE
2317 endmenu # "Power management options"
2319 menu "CPU Power Management"
2321 source "drivers/cpuidle/Kconfig"
2323 source "drivers/cpufreq/Kconfig"
2325 endmenu # "CPU Power Management"
2327 source "drivers/acpi/Kconfig"
2329 source "arch/arm64/kvm/Kconfig"