3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_ELF_RANDOMIZE
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_SPECIAL
25 select ARCH_HAS_SET_MEMORY
26 select ARCH_HAS_SG_CHAIN
27 select ARCH_HAS_STRICT_KERNEL_RWX
28 select ARCH_HAS_STRICT_MODULE_RWX
29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
30 select ARCH_HAS_SYNC_DMA_FOR_CPU
31 select ARCH_HAS_SYSCALL_WRAPPER
32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
33 select ARCH_HAVE_NMI_SAFE_CMPXCHG
34 select ARCH_INLINE_READ_LOCK if !PREEMPT
35 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
36 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
37 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
38 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
39 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
42 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
43 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
44 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
46 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
50 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
51 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
52 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
53 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
54 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
56 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
60 select ARCH_USE_CMPXCHG_LOCKREF
61 select ARCH_USE_QUEUED_RWLOCKS
62 select ARCH_USE_QUEUED_SPINLOCKS
63 select ARCH_SUPPORTS_MEMORY_FAILURE
64 select ARCH_SUPPORTS_ATOMIC_RMW
65 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
66 select ARCH_SUPPORTS_NUMA_BALANCING
67 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
68 select ARCH_WANT_FRAME_POINTERS
69 select ARCH_HAS_UBSAN_SANITIZE_ALL
73 select AUDIT_ARCH_COMPAT_GENERIC
74 select ARM_GIC_V2M if PCI
76 select ARM_GIC_V3_ITS if PCI
78 select BUILDTIME_EXTABLE_SORT
79 select CLONE_BACKWARDS
81 select CPU_PM if (SUSPEND || CPU_IDLE)
83 select DCACHE_WORD_ACCESS
87 select GENERIC_ALLOCATOR
88 select GENERIC_ARCH_TOPOLOGY
89 select GENERIC_CLOCKEVENTS
90 select GENERIC_CLOCKEVENTS_BROADCAST
91 select GENERIC_CPU_AUTOPROBE
92 select GENERIC_EARLY_IOREMAP
93 select GENERIC_IDLE_POLL_SETUP
94 select GENERIC_IRQ_MULTI_HANDLER
95 select GENERIC_IRQ_PROBE
96 select GENERIC_IRQ_SHOW
97 select GENERIC_IRQ_SHOW_LEVEL
98 select GENERIC_PCI_IOMAP
99 select GENERIC_SCHED_CLOCK
100 select GENERIC_SMP_IDLE_THREAD
101 select GENERIC_STRNCPY_FROM_USER
102 select GENERIC_STRNLEN_USER
103 select GENERIC_TIME_VSYSCALL
104 select HANDLE_DOMAIN_IRQ
105 select HARDIRQS_SW_RESEND
106 select HAVE_ACPI_APEI if (ACPI && EFI)
107 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
108 select HAVE_ARCH_AUDITSYSCALL
109 select HAVE_ARCH_BITREVERSE
110 select HAVE_ARCH_HUGE_VMAP
111 select HAVE_ARCH_JUMP_LABEL
112 select HAVE_ARCH_JUMP_LABEL_RELATIVE
113 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
114 select HAVE_ARCH_KGDB
115 select HAVE_ARCH_MMAP_RND_BITS
116 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
117 select HAVE_ARCH_PREL32_RELOCATIONS
118 select HAVE_ARCH_SECCOMP_FILTER
119 select HAVE_ARCH_STACKLEAK
120 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
121 select HAVE_ARCH_TRACEHOOK
122 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
123 select HAVE_ARCH_VMAP_STACK
124 select HAVE_ARM_SMCCC
126 select HAVE_C_RECORDMCOUNT
127 select HAVE_CMPXCHG_DOUBLE
128 select HAVE_CMPXCHG_LOCAL
129 select HAVE_CONTEXT_TRACKING
130 select HAVE_DEBUG_BUGVERBOSE
131 select HAVE_DEBUG_KMEMLEAK
132 select HAVE_DMA_CONTIGUOUS
133 select HAVE_DYNAMIC_FTRACE
134 select HAVE_EFFICIENT_UNALIGNED_ACCESS
135 select HAVE_FTRACE_MCOUNT_RECORD
136 select HAVE_FUNCTION_TRACER
137 select HAVE_FUNCTION_GRAPH_TRACER
138 select HAVE_GCC_PLUGINS
139 select HAVE_GENERIC_DMA_COHERENT
140 select HAVE_HW_BREAKPOINT if PERF_EVENTS
141 select HAVE_IRQ_TIME_ACCOUNTING
143 select HAVE_MEMBLOCK_NODE_MAP if NUMA
145 select HAVE_PATA_PLATFORM
146 select HAVE_PERF_EVENTS
147 select HAVE_PERF_REGS
148 select HAVE_PERF_USER_STACK_DUMP
149 select HAVE_REGS_AND_STACK_ACCESS_API
150 select HAVE_RCU_TABLE_FREE
151 select HAVE_RCU_TABLE_INVALIDATE
153 select HAVE_STACKPROTECTOR
154 select HAVE_SYSCALL_TRACEPOINTS
156 select HAVE_KRETPROBES
157 select IOMMU_DMA if IOMMU_SUPPORT
159 select IRQ_FORCED_THREADING
160 select MODULES_USE_ELF_RELA
161 select MULTI_IRQ_HANDLER
162 select NEED_DMA_MAP_STATE
163 select NEED_SG_DMA_LENGTH
165 select OF_EARLY_FLATTREE
166 select OF_RESERVED_MEM
167 select PCI_ECAM if ACPI
173 select SYSCTL_EXCEPTION_TRACE
174 select THREAD_INFO_IN_TASK
176 ARM 64-bit (AArch64) Linux support.
184 config ARM64_PAGE_SHIFT
186 default 16 if ARM64_64K_PAGES
187 default 14 if ARM64_16K_PAGES
190 config ARM64_CONT_SHIFT
192 default 5 if ARM64_64K_PAGES
193 default 7 if ARM64_16K_PAGES
196 config ARCH_MMAP_RND_BITS_MIN
197 default 14 if ARM64_64K_PAGES
198 default 16 if ARM64_16K_PAGES
201 # max bits determined by the following formula:
202 # VA_BITS - PAGE_SHIFT - 3
203 config ARCH_MMAP_RND_BITS_MAX
204 default 19 if ARM64_VA_BITS=36
205 default 24 if ARM64_VA_BITS=39
206 default 27 if ARM64_VA_BITS=42
207 default 30 if ARM64_VA_BITS=47
208 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
209 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
210 default 33 if ARM64_VA_BITS=48
211 default 14 if ARM64_64K_PAGES
212 default 16 if ARM64_16K_PAGES
215 config ARCH_MMAP_RND_COMPAT_BITS_MIN
216 default 7 if ARM64_64K_PAGES
217 default 9 if ARM64_16K_PAGES
220 config ARCH_MMAP_RND_COMPAT_BITS_MAX
226 config STACKTRACE_SUPPORT
229 config ILLEGAL_POINTER_VALUE
231 default 0xdead000000000000
233 config LOCKDEP_SUPPORT
236 config TRACE_IRQFLAGS_SUPPORT
239 config RWSEM_XCHGADD_ALGORITHM
246 config GENERIC_BUG_RELATIVE_POINTERS
248 depends on GENERIC_BUG
250 config GENERIC_HWEIGHT
256 config GENERIC_CALIBRATE_DELAY
262 config HAVE_GENERIC_GUP
268 config KERNEL_MODE_NEON
271 config FIX_EARLYCON_MEM
274 config PGTABLE_LEVELS
276 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
277 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
278 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
279 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
280 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
281 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
283 config ARCH_SUPPORTS_UPROBES
286 config ARCH_PROC_KCORE_TEXT
289 source "arch/arm64/Kconfig.platforms"
296 This feature enables support for PCI bus system. If you say Y
297 here, the kernel will include drivers and infrastructure code
298 to support PCI bus devices.
303 config PCI_DOMAINS_GENERIC
309 source "drivers/pci/Kconfig"
313 menu "Kernel Features"
315 menu "ARM errata workarounds via the alternatives framework"
317 config ARM64_ERRATUM_826319
318 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
321 This option adds an alternative code sequence to work around ARM
322 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
323 AXI master interface and an L2 cache.
325 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
326 and is unable to accept a certain write via this interface, it will
327 not progress on read data presented on the read data channel and the
330 The workaround promotes data cache clean instructions to
331 data cache clean-and-invalidate.
332 Please note that this does not necessarily enable the workaround,
333 as it depends on the alternative framework, which will only patch
334 the kernel if an affected CPU is detected.
338 config ARM64_ERRATUM_827319
339 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
342 This option adds an alternative code sequence to work around ARM
343 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
344 master interface and an L2 cache.
346 Under certain conditions this erratum can cause a clean line eviction
347 to occur at the same time as another transaction to the same address
348 on the AMBA 5 CHI interface, which can cause data corruption if the
349 interconnect reorders the two transactions.
351 The workaround promotes data cache clean instructions to
352 data cache clean-and-invalidate.
353 Please note that this does not necessarily enable the workaround,
354 as it depends on the alternative framework, which will only patch
355 the kernel if an affected CPU is detected.
359 config ARM64_ERRATUM_824069
360 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
363 This option adds an alternative code sequence to work around ARM
364 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
365 to a coherent interconnect.
367 If a Cortex-A53 processor is executing a store or prefetch for
368 write instruction at the same time as a processor in another
369 cluster is executing a cache maintenance operation to the same
370 address, then this erratum might cause a clean cache line to be
371 incorrectly marked as dirty.
373 The workaround promotes data cache clean instructions to
374 data cache clean-and-invalidate.
375 Please note that this option does not necessarily enable the
376 workaround, as it depends on the alternative framework, which will
377 only patch the kernel if an affected CPU is detected.
381 config ARM64_ERRATUM_819472
382 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
385 This option adds an alternative code sequence to work around ARM
386 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
387 present when it is connected to a coherent interconnect.
389 If the processor is executing a load and store exclusive sequence at
390 the same time as a processor in another cluster is executing a cache
391 maintenance operation to the same address, then this erratum might
392 cause data corruption.
394 The workaround promotes data cache clean instructions to
395 data cache clean-and-invalidate.
396 Please note that this does not necessarily enable the workaround,
397 as it depends on the alternative framework, which will only patch
398 the kernel if an affected CPU is detected.
402 config ARM64_ERRATUM_832075
403 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
406 This option adds an alternative code sequence to work around ARM
407 erratum 832075 on Cortex-A57 parts up to r1p2.
409 Affected Cortex-A57 parts might deadlock when exclusive load/store
410 instructions to Write-Back memory are mixed with Device loads.
412 The workaround is to promote device loads to use Load-Acquire
414 Please note that this does not necessarily enable the workaround,
415 as it depends on the alternative framework, which will only patch
416 the kernel if an affected CPU is detected.
420 config ARM64_ERRATUM_834220
421 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
425 This option adds an alternative code sequence to work around ARM
426 erratum 834220 on Cortex-A57 parts up to r1p2.
428 Affected Cortex-A57 parts might report a Stage 2 translation
429 fault as the result of a Stage 1 fault for load crossing a
430 page boundary when there is a permission or device memory
431 alignment fault at Stage 1 and a translation fault at Stage 2.
433 The workaround is to verify that the Stage 1 translation
434 doesn't generate a fault before handling the Stage 2 fault.
435 Please note that this does not necessarily enable the workaround,
436 as it depends on the alternative framework, which will only patch
437 the kernel if an affected CPU is detected.
441 config ARM64_ERRATUM_845719
442 bool "Cortex-A53: 845719: a load might read incorrect data"
446 This option adds an alternative code sequence to work around ARM
447 erratum 845719 on Cortex-A53 parts up to r0p4.
449 When running a compat (AArch32) userspace on an affected Cortex-A53
450 part, a load at EL0 from a virtual address that matches the bottom 32
451 bits of the virtual address used by a recent load at (AArch64) EL1
452 might return incorrect data.
454 The workaround is to write the contextidr_el1 register on exception
455 return to a 32-bit task.
456 Please note that this does not necessarily enable the workaround,
457 as it depends on the alternative framework, which will only patch
458 the kernel if an affected CPU is detected.
462 config ARM64_ERRATUM_843419
463 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
465 select ARM64_MODULE_PLTS if MODULES
467 This option links the kernel with '--fix-cortex-a53-843419' and
468 enables PLT support to replace certain ADRP instructions, which can
469 cause subsequent memory accesses to use an incorrect address on
470 Cortex-A53 parts up to r0p4.
474 config ARM64_ERRATUM_1024718
475 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
478 This option adds work around for Arm Cortex-A55 Erratum 1024718.
480 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
481 update of the hardware dirty bit when the DBM/AP bits are updated
482 without a break-before-make. The work around is to disable the usage
483 of hardware DBM locally on the affected cores. CPUs not affected by
484 erratum will continue to use the feature.
488 config ARM64_ERRATUM_1188873
489 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
491 select ARM_ARCH_TIMER_OOL_WORKAROUND
493 This option adds work arounds for ARM Cortex-A76 erratum 1188873
495 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
496 register corruption when accessing the timer registers from
501 config CAVIUM_ERRATUM_22375
502 bool "Cavium erratum 22375, 24313"
505 Enable workaround for erratum 22375, 24313.
507 This implements two gicv3-its errata workarounds for ThunderX. Both
508 with small impact affecting only ITS table allocation.
510 erratum 22375: only alloc 8MB table size
511 erratum 24313: ignore memory access type
513 The fixes are in ITS initialization and basically ignore memory access
514 type and table size provided by the TYPER and BASER registers.
518 config CAVIUM_ERRATUM_23144
519 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
523 ITS SYNC command hang for cross node io and collections/cpu mapping.
527 config CAVIUM_ERRATUM_23154
528 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
531 The gicv3 of ThunderX requires a modified version for
532 reading the IAR status to ensure data synchronization
533 (access to icc_iar1_el1 is not sync'ed before and after).
537 config CAVIUM_ERRATUM_27456
538 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
541 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
542 instructions may cause the icache to become corrupted if it
543 contains data for a non-current ASID. The fix is to
544 invalidate the icache when changing the mm context.
548 config CAVIUM_ERRATUM_30115
549 bool "Cavium erratum 30115: Guest may disable interrupts in host"
552 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
553 1.2, and T83 Pass 1.0, KVM guest execution may disable
554 interrupts in host. Trapping both GICv3 group-0 and group-1
555 accesses sidesteps the issue.
559 config QCOM_FALKOR_ERRATUM_1003
560 bool "Falkor E1003: Incorrect translation due to ASID change"
563 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
564 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
565 in TTBR1_EL1, this situation only occurs in the entry trampoline and
566 then only for entries in the walk cache, since the leaf translation
567 is unchanged. Work around the erratum by invalidating the walk cache
568 entries for the trampoline before entering the kernel proper.
570 config QCOM_FALKOR_ERRATUM_1009
571 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
574 On Falkor v1, the CPU may prematurely complete a DSB following a
575 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
576 one more time to fix the issue.
580 config QCOM_QDF2400_ERRATUM_0065
581 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
584 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
585 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
586 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
590 config SOCIONEXT_SYNQUACER_PREITS
591 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
594 Socionext Synquacer SoCs implement a separate h/w block to generate
595 MSI doorbell writes with non-zero values for the device ID.
599 config HISILICON_ERRATUM_161600802
600 bool "Hip07 161600802: Erroneous redistributor VLPI base"
603 The HiSilicon Hip07 SoC usees the wrong redistributor base
604 when issued ITS commands such as VMOVP and VMAPP, and requires
605 a 128kB offset to be applied to the target address in this commands.
609 config QCOM_FALKOR_ERRATUM_E1041
610 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
613 Falkor CPU may speculatively fetch instructions from an improper
614 memory location when MMU translation is changed from SCTLR_ELn[M]=1
615 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
624 default ARM64_4K_PAGES
626 Page size (translation granule) configuration.
628 config ARM64_4K_PAGES
631 This feature enables 4KB pages support.
633 config ARM64_16K_PAGES
636 The system will use 16KB pages support. AArch32 emulation
637 requires applications compiled with 16K (or a multiple of 16K)
640 config ARM64_64K_PAGES
643 This feature enables 64KB pages support (4KB by default)
644 allowing only two levels of page tables and faster TLB
645 look-up. AArch32 emulation requires applications compiled
646 with 64K aligned segments.
651 prompt "Virtual address space size"
652 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
653 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
654 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
656 Allows choosing one of multiple possible virtual address
657 space sizes. The level of translation table is determined by
658 a combination of page size and virtual address space size.
660 config ARM64_VA_BITS_36
661 bool "36-bit" if EXPERT
662 depends on ARM64_16K_PAGES
664 config ARM64_VA_BITS_39
666 depends on ARM64_4K_PAGES
668 config ARM64_VA_BITS_42
670 depends on ARM64_64K_PAGES
672 config ARM64_VA_BITS_47
674 depends on ARM64_16K_PAGES
676 config ARM64_VA_BITS_48
683 default 36 if ARM64_VA_BITS_36
684 default 39 if ARM64_VA_BITS_39
685 default 42 if ARM64_VA_BITS_42
686 default 47 if ARM64_VA_BITS_47
687 default 48 if ARM64_VA_BITS_48
690 prompt "Physical address space size"
691 default ARM64_PA_BITS_48
693 Choose the maximum physical address range that the kernel will
696 config ARM64_PA_BITS_48
699 config ARM64_PA_BITS_52
700 bool "52-bit (ARMv8.2)"
701 depends on ARM64_64K_PAGES
702 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
704 Enable support for a 52-bit physical address space, introduced as
705 part of the ARMv8.2-LPA extension.
707 With this enabled, the kernel will also continue to work on CPUs that
708 do not support ARMv8.2-LPA, but with some added memory overhead (and
709 minor performance overhead).
715 default 48 if ARM64_PA_BITS_48
716 default 52 if ARM64_PA_BITS_52
718 config CPU_BIG_ENDIAN
719 bool "Build big-endian kernel"
721 Say Y if you plan on running a kernel in big-endian mode.
724 bool "Multi-core scheduler support"
726 Multi-core scheduler support improves the CPU scheduler's decision
727 making when dealing with multi-core CPU chips at a cost of slightly
728 increased overhead in some places. If unsure say N here.
731 bool "SMT scheduler support"
733 Improves the CPU scheduler's decision making when dealing with
734 MultiThreading at a cost of slightly increased overhead in some
735 places. If unsure say N here.
738 int "Maximum number of CPUs (2-4096)"
740 # These have to remain sorted largest to smallest
744 bool "Support for hot-pluggable CPUs"
745 select GENERIC_IRQ_MIGRATION
747 Say Y here to experiment with turning CPUs off and on. CPUs
748 can be controlled through /sys/devices/system/cpu.
750 # Common NUMA Features
752 bool "Numa Memory Allocation and Scheduler Support"
753 select ACPI_NUMA if ACPI
756 Enable NUMA (Non Uniform Memory Access) support.
758 The kernel will try to allocate memory used by a CPU on the
759 local memory of the CPU and add some more
760 NUMA awareness to the kernel.
763 int "Maximum NUMA Nodes (as a power of 2)"
766 depends on NEED_MULTIPLE_NODES
768 Specify the maximum number of NUMA Nodes available on the target
769 system. Increases memory reserved to accommodate various tables.
771 config USE_PERCPU_NUMA_NODE_ID
775 config HAVE_SETUP_PER_CPU_AREA
779 config NEED_PER_CPU_EMBED_FIRST_CHUNK
786 source kernel/Kconfig.hz
788 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
791 config ARCH_SPARSEMEM_ENABLE
793 select SPARSEMEM_VMEMMAP_ENABLE
795 config ARCH_SPARSEMEM_DEFAULT
796 def_bool ARCH_SPARSEMEM_ENABLE
798 config ARCH_SELECT_MEMORY_MODEL
799 def_bool ARCH_SPARSEMEM_ENABLE
801 config ARCH_FLATMEM_ENABLE
804 config HAVE_ARCH_PFN_VALID
807 config HW_PERF_EVENTS
811 config SYS_SUPPORTS_HUGETLBFS
814 config ARCH_WANT_HUGE_PMD_SHARE
815 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
817 config ARCH_HAS_CACHE_LINE_SIZE
821 bool "Enable seccomp to safely compute untrusted bytecode"
823 This kernel feature is useful for number crunching applications
824 that may need to compute untrusted bytecode during their
825 execution. By using pipes or other transports made available to
826 the process as file descriptors supporting the read/write
827 syscalls, it's possible to isolate those applications in
828 their own address space using seccomp. Once seccomp is
829 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
830 and the task is only allowed to execute a few safe syscalls
831 defined by each seccomp mode.
834 bool "Enable paravirtualization code"
836 This changes the kernel so it can modify itself when it is run
837 under a hypervisor, potentially improving performance significantly
838 over full virtualization.
840 config PARAVIRT_TIME_ACCOUNTING
841 bool "Paravirtual steal time accounting"
845 Select this option to enable fine granularity task steal time
846 accounting. Time spent executing other tasks in parallel with
847 the current vCPU is discounted from the vCPU power. To account for
848 that, there can be a small performance impact.
850 If in doubt, say N here.
853 depends on PM_SLEEP_SMP
855 bool "kexec system call"
857 kexec is a system call that implements the ability to shutdown your
858 current kernel, and to start another kernel. It is like a reboot
859 but it is independent of the system firmware. And like a reboot
860 you can start any kernel with it, not just Linux.
863 bool "Build kdump crash kernel"
865 Generate crash dump after being started by kexec. This should
866 be normally only set in special crash dump kernels which are
867 loaded in the main kernel with kexec-tools into a specially
868 reserved region and then later executed after a crash by
871 For more details see Documentation/kdump/kdump.txt
878 bool "Xen guest support on ARM64"
879 depends on ARM64 && OF
883 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
885 config FORCE_MAX_ZONEORDER
887 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
888 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
891 The kernel memory allocator divides physically contiguous memory
892 blocks into "zones", where each zone is a power of two number of
893 pages. This option selects the largest power of two that the kernel
894 keeps in the memory allocator. If you need to allocate very large
895 blocks of physically contiguous memory, then you may need to
898 This config option is actually maximum order plus one. For example,
899 a value of 11 means that the largest free memory block is 2^10 pages.
901 We make sure that we can allocate upto a HugePage size for each configuration.
903 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
905 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
906 4M allocations matching the default size used by generic code.
908 config UNMAP_KERNEL_AT_EL0
909 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
912 Speculation attacks against some high-performance processors can
913 be used to bypass MMU permission checks and leak kernel data to
914 userspace. This can be defended against by unmapping the kernel
915 when running in userspace, mapping it back in on exception entry
916 via a trampoline page in the vector table.
920 config HARDEN_BRANCH_PREDICTOR
921 bool "Harden the branch predictor against aliasing attacks" if EXPERT
924 Speculation attacks against some high-performance processors rely on
925 being able to manipulate the branch predictor for a victim context by
926 executing aliasing branches in the attacker context. Such attacks
927 can be partially mitigated against by clearing internal branch
928 predictor state and limiting the prediction logic in some situations.
930 This config option will take CPU-specific actions to harden the
931 branch predictor against aliasing attacks and may rely on specific
932 instruction sequences or control bits being set by the system
937 config HARDEN_EL2_VECTORS
938 bool "Harden EL2 vector mapping against system register leak" if EXPERT
941 Speculation attacks against some high-performance processors can
942 be used to leak privileged information such as the vector base
943 register, resulting in a potential defeat of the EL2 layout
946 This config option will map the vectors to a fixed location,
947 independent of the EL2 code mapping, so that revealing VBAR_EL2
948 to an attacker does not give away any extra information. This
949 only gets enabled on affected CPUs.
954 bool "Speculative Store Bypass Disable" if EXPERT
957 This enables mitigation of the bypassing of previous stores
958 by speculative loads.
962 menuconfig ARMV8_DEPRECATED
963 bool "Emulate deprecated/obsolete ARMv8 instructions"
967 Legacy software support may require certain instructions
968 that have been deprecated or obsoleted in the architecture.
970 Enable this config to enable selective emulation of these
978 bool "Emulate SWP/SWPB instructions"
980 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
981 they are always undefined. Say Y here to enable software
982 emulation of these instructions for userspace using LDXR/STXR.
984 In some older versions of glibc [<=2.8] SWP is used during futex
985 trylock() operations with the assumption that the code will not
986 be preempted. This invalid assumption may be more likely to fail
987 with SWP emulation enabled, leading to deadlock of the user
990 NOTE: when accessing uncached shared regions, LDXR/STXR rely
991 on an external transaction monitoring block called a global
992 monitor to maintain update atomicity. If your system does not
993 implement a global monitor, this option can cause programs that
994 perform SWP operations to uncached memory to deadlock.
998 config CP15_BARRIER_EMULATION
999 bool "Emulate CP15 Barrier instructions"
1001 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1002 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1003 strongly recommended to use the ISB, DSB, and DMB
1004 instructions instead.
1006 Say Y here to enable software emulation of these
1007 instructions for AArch32 userspace code. When this option is
1008 enabled, CP15 barrier usage is traced which can help
1009 identify software that needs updating.
1013 config SETEND_EMULATION
1014 bool "Emulate SETEND instruction"
1016 The SETEND instruction alters the data-endianness of the
1017 AArch32 EL0, and is deprecated in ARMv8.
1019 Say Y here to enable software emulation of the instruction
1020 for AArch32 userspace code.
1022 Note: All the cpus on the system must have mixed endian support at EL0
1023 for this feature to be enabled. If a new CPU - which doesn't support mixed
1024 endian - is hotplugged in after this feature has been enabled, there could
1025 be unexpected results in the applications.
1030 config ARM64_SW_TTBR0_PAN
1031 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1033 Enabling this option prevents the kernel from accessing
1034 user-space memory directly by pointing TTBR0_EL1 to a reserved
1035 zeroed area and reserved ASID. The user access routines
1036 restore the valid TTBR0_EL1 temporarily.
1038 menu "ARMv8.1 architectural features"
1040 config ARM64_HW_AFDBM
1041 bool "Support for hardware updates of the Access and Dirty page flags"
1044 The ARMv8.1 architecture extensions introduce support for
1045 hardware updates of the access and dirty information in page
1046 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1047 capable processors, accesses to pages with PTE_AF cleared will
1048 set this bit instead of raising an access flag fault.
1049 Similarly, writes to read-only pages with the DBM bit set will
1050 clear the read-only bit (AP[2]) instead of raising a
1053 Kernels built with this configuration option enabled continue
1054 to work on pre-ARMv8.1 hardware and the performance impact is
1055 minimal. If unsure, say Y.
1058 bool "Enable support for Privileged Access Never (PAN)"
1061 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1062 prevents the kernel or hypervisor from accessing user-space (EL0)
1065 Choosing this option will cause any unprotected (not using
1066 copy_to_user et al) memory access to fail with a permission fault.
1068 The feature is detected at runtime, and will remain as a 'nop'
1069 instruction if the cpu does not implement the feature.
1071 config ARM64_LSE_ATOMICS
1072 bool "Atomic instructions"
1075 As part of the Large System Extensions, ARMv8.1 introduces new
1076 atomic instructions that are designed specifically to scale in
1079 Say Y here to make use of these instructions for the in-kernel
1080 atomic routines. This incurs a small overhead on CPUs that do
1081 not support these instructions and requires the kernel to be
1082 built with binutils >= 2.25 in order for the new instructions
1086 bool "Enable support for Virtualization Host Extensions (VHE)"
1089 Virtualization Host Extensions (VHE) allow the kernel to run
1090 directly at EL2 (instead of EL1) on processors that support
1091 it. This leads to better performance for KVM, as they reduce
1092 the cost of the world switch.
1094 Selecting this option allows the VHE feature to be detected
1095 at runtime, and does not affect processors that do not
1096 implement this feature.
1100 menu "ARMv8.2 architectural features"
1103 bool "Enable support for User Access Override (UAO)"
1106 User Access Override (UAO; part of the ARMv8.2 Extensions)
1107 causes the 'unprivileged' variant of the load/store instructions to
1108 be overridden to be privileged.
1110 This option changes get_user() and friends to use the 'unprivileged'
1111 variant of the load/store instructions. This ensures that user-space
1112 really did have access to the supplied memory. When addr_limit is
1113 set to kernel memory the UAO bit will be set, allowing privileged
1114 access to kernel memory.
1116 Choosing this option will cause copy_to_user() et al to use user-space
1119 The feature is detected at runtime, the kernel will use the
1120 regular load/store instructions if the cpu does not implement the
1124 bool "Enable support for persistent memory"
1125 select ARCH_HAS_PMEM_API
1126 select ARCH_HAS_UACCESS_FLUSHCACHE
1128 Say Y to enable support for the persistent memory API based on the
1129 ARMv8.2 DCPoP feature.
1131 The feature is detected at runtime, and the kernel will use DC CVAC
1132 operations if DC CVAP is not supported (following the behaviour of
1133 DC CVAP itself if the system does not define a point of persistence).
1135 config ARM64_RAS_EXTN
1136 bool "Enable support for RAS CPU Extensions"
1139 CPUs that support the Reliability, Availability and Serviceability
1140 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1141 errors, classify them and report them to software.
1143 On CPUs with these extensions system software can use additional
1144 barriers to determine if faults are pending and read the
1145 classification from a new set of registers.
1147 Selecting this feature will allow the kernel to use these barriers
1148 and access the new registers if the system supports the extension.
1149 Platform RAS features may additionally depend on firmware support.
1152 bool "Enable support for Common Not Private (CNP) translations"
1154 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1156 Common Not Private (CNP) allows translation table entries to
1157 be shared between different PEs in the same inner shareable
1158 domain, so the hardware can use this fact to optimise the
1159 caching of such entries in the TLB.
1161 Selecting this option allows the CNP feature to be detected
1162 at runtime, and does not affect PEs that do not implement
1168 bool "ARM Scalable Vector Extension support"
1170 depends on !KVM || ARM64_VHE
1172 The Scalable Vector Extension (SVE) is an extension to the AArch64
1173 execution state which complements and extends the SIMD functionality
1174 of the base architecture to support much larger vectors and to enable
1175 additional vectorisation opportunities.
1177 To enable use of this extension on CPUs that implement it, say Y.
1179 Note that for architectural reasons, firmware _must_ implement SVE
1180 support when running on SVE capable hardware. The required support
1183 * version 1.5 and later of the ARM Trusted Firmware
1184 * the AArch64 boot wrapper since commit 5e1261e08abf
1185 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1187 For other firmware implementations, consult the firmware documentation
1190 If you need the kernel to boot on SVE-capable hardware with broken
1191 firmware, you may need to say N here until you get your firmware
1192 fixed. Otherwise, you may experience firmware panics or lockups when
1193 booting the kernel. If unsure and you are not observing these
1194 symptoms, you should assume that it is safe to say Y.
1196 CPUs that support SVE are architecturally required to support the
1197 Virtualization Host Extensions (VHE), so the kernel makes no
1198 provision for supporting SVE alongside KVM without VHE enabled.
1199 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1200 KVM in the same kernel image.
1202 config ARM64_MODULE_PLTS
1204 select HAVE_MOD_ARCH_SPECIFIC
1209 This builds the kernel as a Position Independent Executable (PIE),
1210 which retains all relocation metadata required to relocate the
1211 kernel binary at runtime to a different virtual address than the
1212 address it was linked at.
1213 Since AArch64 uses the RELA relocation format, this requires a
1214 relocation pass at runtime even if the kernel is loaded at the
1215 same address it was linked at.
1217 config RANDOMIZE_BASE
1218 bool "Randomize the address of the kernel image"
1219 select ARM64_MODULE_PLTS if MODULES
1222 Randomizes the virtual address at which the kernel image is
1223 loaded, as a security feature that deters exploit attempts
1224 relying on knowledge of the location of kernel internals.
1226 It is the bootloader's job to provide entropy, by passing a
1227 random u64 value in /chosen/kaslr-seed at kernel entry.
1229 When booting via the UEFI stub, it will invoke the firmware's
1230 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1231 to the kernel proper. In addition, it will randomise the physical
1232 location of the kernel Image as well.
1236 config RANDOMIZE_MODULE_REGION_FULL
1237 bool "Randomize the module region over a 4 GB range"
1238 depends on RANDOMIZE_BASE
1241 Randomizes the location of the module region inside a 4 GB window
1242 covering the core kernel. This way, it is less likely for modules
1243 to leak information about the location of core kernel data structures
1244 but it does imply that function calls between modules and the core
1245 kernel will need to be resolved via veneers in the module PLT.
1247 When this option is not set, the module region will be randomized over
1248 a limited range that contains the [_stext, _etext] interval of the
1249 core kernel, so branch relocations are always in range.
1255 config ARM64_ACPI_PARKING_PROTOCOL
1256 bool "Enable support for the ARM64 ACPI parking protocol"
1259 Enable support for the ARM64 ACPI parking protocol. If disabled
1260 the kernel will not allow booting through the ARM64 ACPI parking
1261 protocol even if the corresponding data is present in the ACPI
1265 string "Default kernel command string"
1268 Provide a set of default command-line options at build time by
1269 entering them here. As a minimum, you should specify the the
1270 root device (e.g. root=/dev/nfs).
1272 config CMDLINE_FORCE
1273 bool "Always use the default kernel command string"
1275 Always use the default kernel command string, even if the boot
1276 loader passes other arguments to the kernel.
1277 This is useful if you cannot or don't want to change the
1278 command-line options your boot loader passes to the kernel.
1284 bool "UEFI runtime support"
1285 depends on OF && !CPU_BIG_ENDIAN
1286 depends on KERNEL_MODE_NEON
1287 select ARCH_SUPPORTS_ACPI
1290 select EFI_PARAMS_FROM_FDT
1291 select EFI_RUNTIME_WRAPPERS
1296 This option provides support for runtime services provided
1297 by UEFI firmware (such as non-volatile variables, realtime
1298 clock, and platform reset). A UEFI stub is also provided to
1299 allow the kernel to be booted as an EFI application. This
1300 is only useful on systems that have UEFI firmware.
1303 bool "Enable support for SMBIOS (DMI) tables"
1307 This enables SMBIOS/DMI feature for systems.
1309 This option is only useful on systems that have UEFI firmware.
1310 However, even with this option, the resultant kernel should
1311 continue to boot on existing non-UEFI platforms.
1316 bool "Kernel support for 32-bit EL0"
1317 depends on ARM64_4K_PAGES || EXPERT
1318 select COMPAT_BINFMT_ELF if BINFMT_ELF
1320 select OLD_SIGSUSPEND3
1321 select COMPAT_OLD_SIGACTION
1323 This option enables support for a 32-bit EL0 running under a 64-bit
1324 kernel at EL1. AArch32-specific components such as system calls,
1325 the user helper functions, VFP support and the ptrace interface are
1326 handled appropriately by the kernel.
1328 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1329 that you will only be able to execute AArch32 binaries that were compiled
1330 with page size aligned segments.
1332 If you want to execute 32-bit userspace applications, say Y.
1334 config SYSVIPC_COMPAT
1336 depends on COMPAT && SYSVIPC
1338 menu "Power management options"
1340 source "kernel/power/Kconfig"
1342 config ARCH_HIBERNATION_POSSIBLE
1346 config ARCH_HIBERNATION_HEADER
1348 depends on HIBERNATION
1350 config ARCH_SUSPEND_POSSIBLE
1355 menu "CPU Power Management"
1357 source "drivers/cpuidle/Kconfig"
1359 source "drivers/cpufreq/Kconfig"
1363 source "drivers/firmware/Kconfig"
1365 source "drivers/acpi/Kconfig"
1367 source "arch/arm64/kvm/Kconfig"
1370 source "arch/arm64/crypto/Kconfig"