3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
15 select ARCH_HAS_ELF_RANDOMIZE
16 select ARCH_HAS_FAST_MULTIPLIER
17 select ARCH_HAS_FORTIFY_SOURCE
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
21 select ARCH_HAS_MEMBARRIER_SYNC_CORE
22 select ARCH_HAS_PTE_SPECIAL
23 select ARCH_HAS_SET_MEMORY
24 select ARCH_HAS_SG_CHAIN
25 select ARCH_HAS_STRICT_KERNEL_RWX
26 select ARCH_HAS_STRICT_MODULE_RWX
27 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
28 select ARCH_HAVE_NMI_SAFE_CMPXCHG
29 select ARCH_INLINE_READ_LOCK if !PREEMPT
30 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
31 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
32 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
33 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
34 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
35 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
36 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
37 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
38 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
39 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
41 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
42 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
43 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
44 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
45 select ARCH_USE_CMPXCHG_LOCKREF
46 select ARCH_USE_QUEUED_RWLOCKS
47 select ARCH_SUPPORTS_MEMORY_FAILURE
48 select ARCH_SUPPORTS_ATOMIC_RMW
49 select ARCH_SUPPORTS_NUMA_BALANCING
50 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
51 select ARCH_WANT_FRAME_POINTERS
52 select ARCH_HAS_UBSAN_SANITIZE_ALL
56 select AUDIT_ARCH_COMPAT_GENERIC
57 select ARM_GIC_V2M if PCI
59 select ARM_GIC_V3_ITS if PCI
61 select BUILDTIME_EXTABLE_SORT
62 select CLONE_BACKWARDS
64 select CPU_PM if (SUSPEND || CPU_IDLE)
65 select DCACHE_WORD_ACCESS
69 select GENERIC_ALLOCATOR
70 select GENERIC_ARCH_TOPOLOGY
71 select GENERIC_CLOCKEVENTS
72 select GENERIC_CLOCKEVENTS_BROADCAST
73 select GENERIC_CPU_AUTOPROBE
74 select GENERIC_EARLY_IOREMAP
75 select GENERIC_IDLE_POLL_SETUP
76 select GENERIC_IRQ_PROBE
77 select GENERIC_IRQ_SHOW
78 select GENERIC_IRQ_SHOW_LEVEL
79 select GENERIC_PCI_IOMAP
80 select GENERIC_SCHED_CLOCK
81 select GENERIC_SMP_IDLE_THREAD
82 select GENERIC_STRNCPY_FROM_USER
83 select GENERIC_STRNLEN_USER
84 select GENERIC_TIME_VSYSCALL
85 select HANDLE_DOMAIN_IRQ
86 select HARDIRQS_SW_RESEND
87 select HAVE_ACPI_APEI if (ACPI && EFI)
88 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
89 select HAVE_ARCH_AUDITSYSCALL
90 select HAVE_ARCH_BITREVERSE
91 select HAVE_ARCH_HUGE_VMAP
92 select HAVE_ARCH_JUMP_LABEL
93 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
95 select HAVE_ARCH_MMAP_RND_BITS
96 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
97 select HAVE_ARCH_SECCOMP_FILTER
98 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
99 select HAVE_ARCH_TRACEHOOK
100 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
101 select HAVE_ARCH_VMAP_STACK
102 select HAVE_ARM_SMCCC
104 select HAVE_C_RECORDMCOUNT
105 select HAVE_CC_STACKPROTECTOR
106 select HAVE_CMPXCHG_DOUBLE
107 select HAVE_CMPXCHG_LOCAL
108 select HAVE_CONTEXT_TRACKING
109 select HAVE_DEBUG_BUGVERBOSE
110 select HAVE_DEBUG_KMEMLEAK
111 select HAVE_DMA_CONTIGUOUS
112 select HAVE_DYNAMIC_FTRACE
113 select HAVE_EFFICIENT_UNALIGNED_ACCESS
114 select HAVE_FTRACE_MCOUNT_RECORD
115 select HAVE_FUNCTION_TRACER
116 select HAVE_FUNCTION_GRAPH_TRACER
117 select HAVE_GCC_PLUGINS
118 select HAVE_GENERIC_DMA_COHERENT
119 select HAVE_HW_BREAKPOINT if PERF_EVENTS
120 select HAVE_IRQ_TIME_ACCOUNTING
122 select HAVE_MEMBLOCK_NODE_MAP if NUMA
124 select HAVE_PATA_PLATFORM
125 select HAVE_PERF_EVENTS
126 select HAVE_PERF_REGS
127 select HAVE_PERF_USER_STACK_DUMP
128 select HAVE_REGS_AND_STACK_ACCESS_API
129 select HAVE_RCU_TABLE_FREE
130 select HAVE_SYSCALL_TRACEPOINTS
132 select HAVE_KRETPROBES
133 select IOMMU_DMA if IOMMU_SUPPORT
135 select IRQ_FORCED_THREADING
136 select MODULES_USE_ELF_RELA
137 select MULTI_IRQ_HANDLER
138 select NEED_DMA_MAP_STATE
139 select NEED_SG_DMA_LENGTH
142 select OF_EARLY_FLATTREE
143 select OF_RESERVED_MEM
144 select PCI_ECAM if ACPI
150 select SYSCTL_EXCEPTION_TRACE
151 select THREAD_INFO_IN_TASK
153 ARM 64-bit (AArch64) Linux support.
161 config ARM64_PAGE_SHIFT
163 default 16 if ARM64_64K_PAGES
164 default 14 if ARM64_16K_PAGES
167 config ARM64_CONT_SHIFT
169 default 5 if ARM64_64K_PAGES
170 default 7 if ARM64_16K_PAGES
173 config ARCH_MMAP_RND_BITS_MIN
174 default 14 if ARM64_64K_PAGES
175 default 16 if ARM64_16K_PAGES
178 # max bits determined by the following formula:
179 # VA_BITS - PAGE_SHIFT - 3
180 config ARCH_MMAP_RND_BITS_MAX
181 default 19 if ARM64_VA_BITS=36
182 default 24 if ARM64_VA_BITS=39
183 default 27 if ARM64_VA_BITS=42
184 default 30 if ARM64_VA_BITS=47
185 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
186 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
187 default 33 if ARM64_VA_BITS=48
188 default 14 if ARM64_64K_PAGES
189 default 16 if ARM64_16K_PAGES
192 config ARCH_MMAP_RND_COMPAT_BITS_MIN
193 default 7 if ARM64_64K_PAGES
194 default 9 if ARM64_16K_PAGES
197 config ARCH_MMAP_RND_COMPAT_BITS_MAX
203 config STACKTRACE_SUPPORT
206 config ILLEGAL_POINTER_VALUE
208 default 0xdead000000000000
210 config LOCKDEP_SUPPORT
213 config TRACE_IRQFLAGS_SUPPORT
216 config RWSEM_XCHGADD_ALGORITHM
223 config GENERIC_BUG_RELATIVE_POINTERS
225 depends on GENERIC_BUG
227 config GENERIC_HWEIGHT
233 config GENERIC_CALIBRATE_DELAY
239 config HAVE_GENERIC_GUP
245 config KERNEL_MODE_NEON
248 config FIX_EARLYCON_MEM
251 config PGTABLE_LEVELS
253 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
254 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
255 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
256 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
257 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
258 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
260 config ARCH_SUPPORTS_UPROBES
263 config ARCH_PROC_KCORE_TEXT
266 config MULTI_IRQ_HANDLER
269 source "init/Kconfig"
271 source "kernel/Kconfig.freezer"
273 source "arch/arm64/Kconfig.platforms"
280 This feature enables support for PCI bus system. If you say Y
281 here, the kernel will include drivers and infrastructure code
282 to support PCI bus devices.
287 config PCI_DOMAINS_GENERIC
293 source "drivers/pci/Kconfig"
297 menu "Kernel Features"
299 menu "ARM errata workarounds via the alternatives framework"
301 config ARM64_ERRATUM_826319
302 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
305 This option adds an alternative code sequence to work around ARM
306 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
307 AXI master interface and an L2 cache.
309 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
310 and is unable to accept a certain write via this interface, it will
311 not progress on read data presented on the read data channel and the
314 The workaround promotes data cache clean instructions to
315 data cache clean-and-invalidate.
316 Please note that this does not necessarily enable the workaround,
317 as it depends on the alternative framework, which will only patch
318 the kernel if an affected CPU is detected.
322 config ARM64_ERRATUM_827319
323 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
326 This option adds an alternative code sequence to work around ARM
327 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
328 master interface and an L2 cache.
330 Under certain conditions this erratum can cause a clean line eviction
331 to occur at the same time as another transaction to the same address
332 on the AMBA 5 CHI interface, which can cause data corruption if the
333 interconnect reorders the two transactions.
335 The workaround promotes data cache clean instructions to
336 data cache clean-and-invalidate.
337 Please note that this does not necessarily enable the workaround,
338 as it depends on the alternative framework, which will only patch
339 the kernel if an affected CPU is detected.
343 config ARM64_ERRATUM_824069
344 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
347 This option adds an alternative code sequence to work around ARM
348 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
349 to a coherent interconnect.
351 If a Cortex-A53 processor is executing a store or prefetch for
352 write instruction at the same time as a processor in another
353 cluster is executing a cache maintenance operation to the same
354 address, then this erratum might cause a clean cache line to be
355 incorrectly marked as dirty.
357 The workaround promotes data cache clean instructions to
358 data cache clean-and-invalidate.
359 Please note that this option does not necessarily enable the
360 workaround, as it depends on the alternative framework, which will
361 only patch the kernel if an affected CPU is detected.
365 config ARM64_ERRATUM_819472
366 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
369 This option adds an alternative code sequence to work around ARM
370 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
371 present when it is connected to a coherent interconnect.
373 If the processor is executing a load and store exclusive sequence at
374 the same time as a processor in another cluster is executing a cache
375 maintenance operation to the same address, then this erratum might
376 cause data corruption.
378 The workaround promotes data cache clean instructions to
379 data cache clean-and-invalidate.
380 Please note that this does not necessarily enable the workaround,
381 as it depends on the alternative framework, which will only patch
382 the kernel if an affected CPU is detected.
386 config ARM64_ERRATUM_832075
387 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
390 This option adds an alternative code sequence to work around ARM
391 erratum 832075 on Cortex-A57 parts up to r1p2.
393 Affected Cortex-A57 parts might deadlock when exclusive load/store
394 instructions to Write-Back memory are mixed with Device loads.
396 The workaround is to promote device loads to use Load-Acquire
398 Please note that this does not necessarily enable the workaround,
399 as it depends on the alternative framework, which will only patch
400 the kernel if an affected CPU is detected.
404 config ARM64_ERRATUM_834220
405 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
409 This option adds an alternative code sequence to work around ARM
410 erratum 834220 on Cortex-A57 parts up to r1p2.
412 Affected Cortex-A57 parts might report a Stage 2 translation
413 fault as the result of a Stage 1 fault for load crossing a
414 page boundary when there is a permission or device memory
415 alignment fault at Stage 1 and a translation fault at Stage 2.
417 The workaround is to verify that the Stage 1 translation
418 doesn't generate a fault before handling the Stage 2 fault.
419 Please note that this does not necessarily enable the workaround,
420 as it depends on the alternative framework, which will only patch
421 the kernel if an affected CPU is detected.
425 config ARM64_ERRATUM_845719
426 bool "Cortex-A53: 845719: a load might read incorrect data"
430 This option adds an alternative code sequence to work around ARM
431 erratum 845719 on Cortex-A53 parts up to r0p4.
433 When running a compat (AArch32) userspace on an affected Cortex-A53
434 part, a load at EL0 from a virtual address that matches the bottom 32
435 bits of the virtual address used by a recent load at (AArch64) EL1
436 might return incorrect data.
438 The workaround is to write the contextidr_el1 register on exception
439 return to a 32-bit task.
440 Please note that this does not necessarily enable the workaround,
441 as it depends on the alternative framework, which will only patch
442 the kernel if an affected CPU is detected.
446 config ARM64_ERRATUM_843419
447 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
449 select ARM64_MODULE_PLTS if MODULES
451 This option links the kernel with '--fix-cortex-a53-843419' and
452 enables PLT support to replace certain ADRP instructions, which can
453 cause subsequent memory accesses to use an incorrect address on
454 Cortex-A53 parts up to r0p4.
458 config ARM64_ERRATUM_1024718
459 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
462 This option adds work around for Arm Cortex-A55 Erratum 1024718.
464 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
465 update of the hardware dirty bit when the DBM/AP bits are updated
466 without a break-before-make. The work around is to disable the usage
467 of hardware DBM locally on the affected cores. CPUs not affected by
468 erratum will continue to use the feature.
472 config CAVIUM_ERRATUM_22375
473 bool "Cavium erratum 22375, 24313"
476 Enable workaround for erratum 22375, 24313.
478 This implements two gicv3-its errata workarounds for ThunderX. Both
479 with small impact affecting only ITS table allocation.
481 erratum 22375: only alloc 8MB table size
482 erratum 24313: ignore memory access type
484 The fixes are in ITS initialization and basically ignore memory access
485 type and table size provided by the TYPER and BASER registers.
489 config CAVIUM_ERRATUM_23144
490 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
494 ITS SYNC command hang for cross node io and collections/cpu mapping.
498 config CAVIUM_ERRATUM_23154
499 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
502 The gicv3 of ThunderX requires a modified version for
503 reading the IAR status to ensure data synchronization
504 (access to icc_iar1_el1 is not sync'ed before and after).
508 config CAVIUM_ERRATUM_27456
509 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
512 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
513 instructions may cause the icache to become corrupted if it
514 contains data for a non-current ASID. The fix is to
515 invalidate the icache when changing the mm context.
519 config CAVIUM_ERRATUM_30115
520 bool "Cavium erratum 30115: Guest may disable interrupts in host"
523 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
524 1.2, and T83 Pass 1.0, KVM guest execution may disable
525 interrupts in host. Trapping both GICv3 group-0 and group-1
526 accesses sidesteps the issue.
530 config QCOM_FALKOR_ERRATUM_1003
531 bool "Falkor E1003: Incorrect translation due to ASID change"
534 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
535 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
536 in TTBR1_EL1, this situation only occurs in the entry trampoline and
537 then only for entries in the walk cache, since the leaf translation
538 is unchanged. Work around the erratum by invalidating the walk cache
539 entries for the trampoline before entering the kernel proper.
541 config QCOM_FALKOR_ERRATUM_1009
542 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
545 On Falkor v1, the CPU may prematurely complete a DSB following a
546 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
547 one more time to fix the issue.
551 config QCOM_QDF2400_ERRATUM_0065
552 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
555 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
556 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
557 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
561 config SOCIONEXT_SYNQUACER_PREITS
562 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
565 Socionext Synquacer SoCs implement a separate h/w block to generate
566 MSI doorbell writes with non-zero values for the device ID.
570 config HISILICON_ERRATUM_161600802
571 bool "Hip07 161600802: Erroneous redistributor VLPI base"
574 The HiSilicon Hip07 SoC usees the wrong redistributor base
575 when issued ITS commands such as VMOVP and VMAPP, and requires
576 a 128kB offset to be applied to the target address in this commands.
580 config QCOM_FALKOR_ERRATUM_E1041
581 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
584 Falkor CPU may speculatively fetch instructions from an improper
585 memory location when MMU translation is changed from SCTLR_ELn[M]=1
586 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
595 default ARM64_4K_PAGES
597 Page size (translation granule) configuration.
599 config ARM64_4K_PAGES
602 This feature enables 4KB pages support.
604 config ARM64_16K_PAGES
607 The system will use 16KB pages support. AArch32 emulation
608 requires applications compiled with 16K (or a multiple of 16K)
611 config ARM64_64K_PAGES
614 This feature enables 64KB pages support (4KB by default)
615 allowing only two levels of page tables and faster TLB
616 look-up. AArch32 emulation requires applications compiled
617 with 64K aligned segments.
622 prompt "Virtual address space size"
623 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
624 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
625 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
627 Allows choosing one of multiple possible virtual address
628 space sizes. The level of translation table is determined by
629 a combination of page size and virtual address space size.
631 config ARM64_VA_BITS_36
632 bool "36-bit" if EXPERT
633 depends on ARM64_16K_PAGES
635 config ARM64_VA_BITS_39
637 depends on ARM64_4K_PAGES
639 config ARM64_VA_BITS_42
641 depends on ARM64_64K_PAGES
643 config ARM64_VA_BITS_47
645 depends on ARM64_16K_PAGES
647 config ARM64_VA_BITS_48
654 default 36 if ARM64_VA_BITS_36
655 default 39 if ARM64_VA_BITS_39
656 default 42 if ARM64_VA_BITS_42
657 default 47 if ARM64_VA_BITS_47
658 default 48 if ARM64_VA_BITS_48
661 prompt "Physical address space size"
662 default ARM64_PA_BITS_48
664 Choose the maximum physical address range that the kernel will
667 config ARM64_PA_BITS_48
670 config ARM64_PA_BITS_52
671 bool "52-bit (ARMv8.2)"
672 depends on ARM64_64K_PAGES
673 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
675 Enable support for a 52-bit physical address space, introduced as
676 part of the ARMv8.2-LPA extension.
678 With this enabled, the kernel will also continue to work on CPUs that
679 do not support ARMv8.2-LPA, but with some added memory overhead (and
680 minor performance overhead).
686 default 48 if ARM64_PA_BITS_48
687 default 52 if ARM64_PA_BITS_52
689 config CPU_BIG_ENDIAN
690 bool "Build big-endian kernel"
692 Say Y if you plan on running a kernel in big-endian mode.
695 bool "Multi-core scheduler support"
697 Multi-core scheduler support improves the CPU scheduler's decision
698 making when dealing with multi-core CPU chips at a cost of slightly
699 increased overhead in some places. If unsure say N here.
702 bool "SMT scheduler support"
704 Improves the CPU scheduler's decision making when dealing with
705 MultiThreading at a cost of slightly increased overhead in some
706 places. If unsure say N here.
709 int "Maximum number of CPUs (2-4096)"
711 # These have to remain sorted largest to smallest
715 bool "Support for hot-pluggable CPUs"
716 select GENERIC_IRQ_MIGRATION
718 Say Y here to experiment with turning CPUs off and on. CPUs
719 can be controlled through /sys/devices/system/cpu.
721 # Common NUMA Features
723 bool "Numa Memory Allocation and Scheduler Support"
724 select ACPI_NUMA if ACPI
727 Enable NUMA (Non Uniform Memory Access) support.
729 The kernel will try to allocate memory used by a CPU on the
730 local memory of the CPU and add some more
731 NUMA awareness to the kernel.
734 int "Maximum NUMA Nodes (as a power of 2)"
737 depends on NEED_MULTIPLE_NODES
739 Specify the maximum number of NUMA Nodes available on the target
740 system. Increases memory reserved to accommodate various tables.
742 config USE_PERCPU_NUMA_NODE_ID
746 config HAVE_SETUP_PER_CPU_AREA
750 config NEED_PER_CPU_EMBED_FIRST_CHUNK
758 source kernel/Kconfig.preempt
759 source kernel/Kconfig.hz
761 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
764 config ARCH_HAS_HOLES_MEMORYMODEL
765 def_bool y if SPARSEMEM
767 config ARCH_SPARSEMEM_ENABLE
769 select SPARSEMEM_VMEMMAP_ENABLE
771 config ARCH_SPARSEMEM_DEFAULT
772 def_bool ARCH_SPARSEMEM_ENABLE
774 config ARCH_SELECT_MEMORY_MODEL
775 def_bool ARCH_SPARSEMEM_ENABLE
777 config HAVE_ARCH_PFN_VALID
778 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
780 config HW_PERF_EVENTS
784 config SYS_SUPPORTS_HUGETLBFS
787 config ARCH_WANT_HUGE_PMD_SHARE
788 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
790 config ARCH_HAS_CACHE_LINE_SIZE
796 bool "Enable seccomp to safely compute untrusted bytecode"
798 This kernel feature is useful for number crunching applications
799 that may need to compute untrusted bytecode during their
800 execution. By using pipes or other transports made available to
801 the process as file descriptors supporting the read/write
802 syscalls, it's possible to isolate those applications in
803 their own address space using seccomp. Once seccomp is
804 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
805 and the task is only allowed to execute a few safe syscalls
806 defined by each seccomp mode.
809 bool "Enable paravirtualization code"
811 This changes the kernel so it can modify itself when it is run
812 under a hypervisor, potentially improving performance significantly
813 over full virtualization.
815 config PARAVIRT_TIME_ACCOUNTING
816 bool "Paravirtual steal time accounting"
820 Select this option to enable fine granularity task steal time
821 accounting. Time spent executing other tasks in parallel with
822 the current vCPU is discounted from the vCPU power. To account for
823 that, there can be a small performance impact.
825 If in doubt, say N here.
828 depends on PM_SLEEP_SMP
830 bool "kexec system call"
832 kexec is a system call that implements the ability to shutdown your
833 current kernel, and to start another kernel. It is like a reboot
834 but it is independent of the system firmware. And like a reboot
835 you can start any kernel with it, not just Linux.
838 bool "Build kdump crash kernel"
840 Generate crash dump after being started by kexec. This should
841 be normally only set in special crash dump kernels which are
842 loaded in the main kernel with kexec-tools into a specially
843 reserved region and then later executed after a crash by
846 For more details see Documentation/kdump/kdump.txt
853 bool "Xen guest support on ARM64"
854 depends on ARM64 && OF
858 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
860 config FORCE_MAX_ZONEORDER
862 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
863 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
866 The kernel memory allocator divides physically contiguous memory
867 blocks into "zones", where each zone is a power of two number of
868 pages. This option selects the largest power of two that the kernel
869 keeps in the memory allocator. If you need to allocate very large
870 blocks of physically contiguous memory, then you may need to
873 This config option is actually maximum order plus one. For example,
874 a value of 11 means that the largest free memory block is 2^10 pages.
876 We make sure that we can allocate upto a HugePage size for each configuration.
878 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
880 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
881 4M allocations matching the default size used by generic code.
883 config UNMAP_KERNEL_AT_EL0
884 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
887 Speculation attacks against some high-performance processors can
888 be used to bypass MMU permission checks and leak kernel data to
889 userspace. This can be defended against by unmapping the kernel
890 when running in userspace, mapping it back in on exception entry
891 via a trampoline page in the vector table.
895 config HARDEN_BRANCH_PREDICTOR
896 bool "Harden the branch predictor against aliasing attacks" if EXPERT
899 Speculation attacks against some high-performance processors rely on
900 being able to manipulate the branch predictor for a victim context by
901 executing aliasing branches in the attacker context. Such attacks
902 can be partially mitigated against by clearing internal branch
903 predictor state and limiting the prediction logic in some situations.
905 This config option will take CPU-specific actions to harden the
906 branch predictor against aliasing attacks and may rely on specific
907 instruction sequences or control bits being set by the system
912 config HARDEN_EL2_VECTORS
913 bool "Harden EL2 vector mapping against system register leak" if EXPERT
916 Speculation attacks against some high-performance processors can
917 be used to leak privileged information such as the vector base
918 register, resulting in a potential defeat of the EL2 layout
921 This config option will map the vectors to a fixed location,
922 independent of the EL2 code mapping, so that revealing VBAR_EL2
923 to an attacker does not give away any extra information. This
924 only gets enabled on affected CPUs.
929 bool "Speculative Store Bypass Disable" if EXPERT
932 This enables mitigation of the bypassing of previous stores
933 by speculative loads.
937 menuconfig ARMV8_DEPRECATED
938 bool "Emulate deprecated/obsolete ARMv8 instructions"
942 Legacy software support may require certain instructions
943 that have been deprecated or obsoleted in the architecture.
945 Enable this config to enable selective emulation of these
953 bool "Emulate SWP/SWPB instructions"
955 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
956 they are always undefined. Say Y here to enable software
957 emulation of these instructions for userspace using LDXR/STXR.
959 In some older versions of glibc [<=2.8] SWP is used during futex
960 trylock() operations with the assumption that the code will not
961 be preempted. This invalid assumption may be more likely to fail
962 with SWP emulation enabled, leading to deadlock of the user
965 NOTE: when accessing uncached shared regions, LDXR/STXR rely
966 on an external transaction monitoring block called a global
967 monitor to maintain update atomicity. If your system does not
968 implement a global monitor, this option can cause programs that
969 perform SWP operations to uncached memory to deadlock.
973 config CP15_BARRIER_EMULATION
974 bool "Emulate CP15 Barrier instructions"
976 The CP15 barrier instructions - CP15ISB, CP15DSB, and
977 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
978 strongly recommended to use the ISB, DSB, and DMB
979 instructions instead.
981 Say Y here to enable software emulation of these
982 instructions for AArch32 userspace code. When this option is
983 enabled, CP15 barrier usage is traced which can help
984 identify software that needs updating.
988 config SETEND_EMULATION
989 bool "Emulate SETEND instruction"
991 The SETEND instruction alters the data-endianness of the
992 AArch32 EL0, and is deprecated in ARMv8.
994 Say Y here to enable software emulation of the instruction
995 for AArch32 userspace code.
997 Note: All the cpus on the system must have mixed endian support at EL0
998 for this feature to be enabled. If a new CPU - which doesn't support mixed
999 endian - is hotplugged in after this feature has been enabled, there could
1000 be unexpected results in the applications.
1005 config ARM64_SW_TTBR0_PAN
1006 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1008 Enabling this option prevents the kernel from accessing
1009 user-space memory directly by pointing TTBR0_EL1 to a reserved
1010 zeroed area and reserved ASID. The user access routines
1011 restore the valid TTBR0_EL1 temporarily.
1013 menu "ARMv8.1 architectural features"
1015 config ARM64_HW_AFDBM
1016 bool "Support for hardware updates of the Access and Dirty page flags"
1019 The ARMv8.1 architecture extensions introduce support for
1020 hardware updates of the access and dirty information in page
1021 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1022 capable processors, accesses to pages with PTE_AF cleared will
1023 set this bit instead of raising an access flag fault.
1024 Similarly, writes to read-only pages with the DBM bit set will
1025 clear the read-only bit (AP[2]) instead of raising a
1028 Kernels built with this configuration option enabled continue
1029 to work on pre-ARMv8.1 hardware and the performance impact is
1030 minimal. If unsure, say Y.
1033 bool "Enable support for Privileged Access Never (PAN)"
1036 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1037 prevents the kernel or hypervisor from accessing user-space (EL0)
1040 Choosing this option will cause any unprotected (not using
1041 copy_to_user et al) memory access to fail with a permission fault.
1043 The feature is detected at runtime, and will remain as a 'nop'
1044 instruction if the cpu does not implement the feature.
1046 config ARM64_LSE_ATOMICS
1047 bool "Atomic instructions"
1050 As part of the Large System Extensions, ARMv8.1 introduces new
1051 atomic instructions that are designed specifically to scale in
1054 Say Y here to make use of these instructions for the in-kernel
1055 atomic routines. This incurs a small overhead on CPUs that do
1056 not support these instructions and requires the kernel to be
1057 built with binutils >= 2.25 in order for the new instructions
1061 bool "Enable support for Virtualization Host Extensions (VHE)"
1064 Virtualization Host Extensions (VHE) allow the kernel to run
1065 directly at EL2 (instead of EL1) on processors that support
1066 it. This leads to better performance for KVM, as they reduce
1067 the cost of the world switch.
1069 Selecting this option allows the VHE feature to be detected
1070 at runtime, and does not affect processors that do not
1071 implement this feature.
1075 menu "ARMv8.2 architectural features"
1078 bool "Enable support for User Access Override (UAO)"
1081 User Access Override (UAO; part of the ARMv8.2 Extensions)
1082 causes the 'unprivileged' variant of the load/store instructions to
1083 be overridden to be privileged.
1085 This option changes get_user() and friends to use the 'unprivileged'
1086 variant of the load/store instructions. This ensures that user-space
1087 really did have access to the supplied memory. When addr_limit is
1088 set to kernel memory the UAO bit will be set, allowing privileged
1089 access to kernel memory.
1091 Choosing this option will cause copy_to_user() et al to use user-space
1094 The feature is detected at runtime, the kernel will use the
1095 regular load/store instructions if the cpu does not implement the
1099 bool "Enable support for persistent memory"
1100 select ARCH_HAS_PMEM_API
1101 select ARCH_HAS_UACCESS_FLUSHCACHE
1103 Say Y to enable support for the persistent memory API based on the
1104 ARMv8.2 DCPoP feature.
1106 The feature is detected at runtime, and the kernel will use DC CVAC
1107 operations if DC CVAP is not supported (following the behaviour of
1108 DC CVAP itself if the system does not define a point of persistence).
1110 config ARM64_RAS_EXTN
1111 bool "Enable support for RAS CPU Extensions"
1114 CPUs that support the Reliability, Availability and Serviceability
1115 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1116 errors, classify them and report them to software.
1118 On CPUs with these extensions system software can use additional
1119 barriers to determine if faults are pending and read the
1120 classification from a new set of registers.
1122 Selecting this feature will allow the kernel to use these barriers
1123 and access the new registers if the system supports the extension.
1124 Platform RAS features may additionally depend on firmware support.
1129 bool "ARM Scalable Vector Extension support"
1132 The Scalable Vector Extension (SVE) is an extension to the AArch64
1133 execution state which complements and extends the SIMD functionality
1134 of the base architecture to support much larger vectors and to enable
1135 additional vectorisation opportunities.
1137 To enable use of this extension on CPUs that implement it, say Y.
1139 Note that for architectural reasons, firmware _must_ implement SVE
1140 support when running on SVE capable hardware. The required support
1143 * version 1.5 and later of the ARM Trusted Firmware
1144 * the AArch64 boot wrapper since commit 5e1261e08abf
1145 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1147 For other firmware implementations, consult the firmware documentation
1150 If you need the kernel to boot on SVE-capable hardware with broken
1151 firmware, you may need to say N here until you get your firmware
1152 fixed. Otherwise, you may experience firmware panics or lockups when
1153 booting the kernel. If unsure and you are not observing these
1154 symptoms, you should assume that it is safe to say Y.
1156 config ARM64_MODULE_PLTS
1158 select HAVE_MOD_ARCH_SPECIFIC
1163 This builds the kernel as a Position Independent Executable (PIE),
1164 which retains all relocation metadata required to relocate the
1165 kernel binary at runtime to a different virtual address than the
1166 address it was linked at.
1167 Since AArch64 uses the RELA relocation format, this requires a
1168 relocation pass at runtime even if the kernel is loaded at the
1169 same address it was linked at.
1171 config RANDOMIZE_BASE
1172 bool "Randomize the address of the kernel image"
1173 select ARM64_MODULE_PLTS if MODULES
1176 Randomizes the virtual address at which the kernel image is
1177 loaded, as a security feature that deters exploit attempts
1178 relying on knowledge of the location of kernel internals.
1180 It is the bootloader's job to provide entropy, by passing a
1181 random u64 value in /chosen/kaslr-seed at kernel entry.
1183 When booting via the UEFI stub, it will invoke the firmware's
1184 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1185 to the kernel proper. In addition, it will randomise the physical
1186 location of the kernel Image as well.
1190 config RANDOMIZE_MODULE_REGION_FULL
1191 bool "Randomize the module region over a 4 GB range"
1192 depends on RANDOMIZE_BASE
1195 Randomizes the location of the module region inside a 4 GB window
1196 covering the core kernel. This way, it is less likely for modules
1197 to leak information about the location of core kernel data structures
1198 but it does imply that function calls between modules and the core
1199 kernel will need to be resolved via veneers in the module PLT.
1201 When this option is not set, the module region will be randomized over
1202 a limited range that contains the [_stext, _etext] interval of the
1203 core kernel, so branch relocations are always in range.
1209 config ARM64_ACPI_PARKING_PROTOCOL
1210 bool "Enable support for the ARM64 ACPI parking protocol"
1213 Enable support for the ARM64 ACPI parking protocol. If disabled
1214 the kernel will not allow booting through the ARM64 ACPI parking
1215 protocol even if the corresponding data is present in the ACPI
1219 string "Default kernel command string"
1222 Provide a set of default command-line options at build time by
1223 entering them here. As a minimum, you should specify the the
1224 root device (e.g. root=/dev/nfs).
1226 config CMDLINE_FORCE
1227 bool "Always use the default kernel command string"
1229 Always use the default kernel command string, even if the boot
1230 loader passes other arguments to the kernel.
1231 This is useful if you cannot or don't want to change the
1232 command-line options your boot loader passes to the kernel.
1238 bool "UEFI runtime support"
1239 depends on OF && !CPU_BIG_ENDIAN
1240 depends on KERNEL_MODE_NEON
1243 select EFI_PARAMS_FROM_FDT
1244 select EFI_RUNTIME_WRAPPERS
1249 This option provides support for runtime services provided
1250 by UEFI firmware (such as non-volatile variables, realtime
1251 clock, and platform reset). A UEFI stub is also provided to
1252 allow the kernel to be booted as an EFI application. This
1253 is only useful on systems that have UEFI firmware.
1256 bool "Enable support for SMBIOS (DMI) tables"
1260 This enables SMBIOS/DMI feature for systems.
1262 This option is only useful on systems that have UEFI firmware.
1263 However, even with this option, the resultant kernel should
1264 continue to boot on existing non-UEFI platforms.
1268 menu "Userspace binary formats"
1270 source "fs/Kconfig.binfmt"
1273 bool "Kernel support for 32-bit EL0"
1274 depends on ARM64_4K_PAGES || EXPERT
1275 select COMPAT_BINFMT_ELF if BINFMT_ELF
1277 select OLD_SIGSUSPEND3
1278 select COMPAT_OLD_SIGACTION
1280 This option enables support for a 32-bit EL0 running under a 64-bit
1281 kernel at EL1. AArch32-specific components such as system calls,
1282 the user helper functions, VFP support and the ptrace interface are
1283 handled appropriately by the kernel.
1285 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1286 that you will only be able to execute AArch32 binaries that were compiled
1287 with page size aligned segments.
1289 If you want to execute 32-bit userspace applications, say Y.
1291 config SYSVIPC_COMPAT
1293 depends on COMPAT && SYSVIPC
1297 menu "Power management options"
1299 source "kernel/power/Kconfig"
1301 config ARCH_HIBERNATION_POSSIBLE
1305 config ARCH_HIBERNATION_HEADER
1307 depends on HIBERNATION
1309 config ARCH_SUSPEND_POSSIBLE
1314 menu "CPU Power Management"
1316 source "drivers/cpuidle/Kconfig"
1318 source "drivers/cpufreq/Kconfig"
1322 source "net/Kconfig"
1324 source "drivers/Kconfig"
1326 source "drivers/firmware/Kconfig"
1328 source "drivers/acpi/Kconfig"
1332 source "arch/arm64/kvm/Kconfig"
1334 source "arch/arm64/Kconfig.debug"
1336 source "security/Kconfig"
1338 source "crypto/Kconfig"
1340 source "arch/arm64/crypto/Kconfig"
1343 source "lib/Kconfig"