3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_SG_CHAIN
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_USE_CMPXCHG_LOCKREF
8 select ARCH_SUPPORTS_ATOMIC_RMW
9 select ARCH_WANT_OPTIONAL_GPIOLIB
10 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
11 select ARCH_WANT_FRAME_POINTERS
15 select AUDIT_ARCH_COMPAT_GENERIC
17 select BUILDTIME_EXTABLE_SORT
18 select CLONE_BACKWARDS
20 select CPU_PM if (SUSPEND || CPU_IDLE)
21 select DCACHE_WORD_ACCESS
22 select GENERIC_ALLOCATOR
23 select GENERIC_CLOCKEVENTS
24 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
25 select GENERIC_CPU_AUTOPROBE
26 select GENERIC_EARLY_IOREMAP
28 select GENERIC_IRQ_PROBE
29 select GENERIC_IRQ_SHOW
30 select GENERIC_SCHED_CLOCK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
34 select GENERIC_TIME_VSYSCALL
35 select HANDLE_DOMAIN_IRQ
36 select HARDIRQS_SW_RESEND
37 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
38 select HAVE_ARCH_AUDITSYSCALL
39 select HAVE_ARCH_JUMP_LABEL
41 select HAVE_ARCH_SECCOMP_FILTER
42 select HAVE_ARCH_TRACEHOOK
44 select HAVE_C_RECORDMCOUNT
45 select HAVE_CC_STACKPROTECTOR
46 select HAVE_CMPXCHG_DOUBLE
47 select HAVE_DEBUG_BUGVERBOSE
48 select HAVE_DEBUG_KMEMLEAK
49 select HAVE_DMA_API_DEBUG
51 select HAVE_DMA_CONTIGUOUS
52 select HAVE_DYNAMIC_FTRACE
53 select HAVE_EFFICIENT_UNALIGNED_ACCESS
54 select HAVE_FTRACE_MCOUNT_RECORD
55 select HAVE_FUNCTION_TRACER
56 select HAVE_FUNCTION_GRAPH_TRACER
57 select HAVE_GENERIC_DMA_COHERENT
58 select HAVE_HW_BREAKPOINT if PERF_EVENTS
60 select HAVE_PATA_PLATFORM
61 select HAVE_PERF_EVENTS
63 select HAVE_PERF_USER_STACK_DUMP
64 select HAVE_RCU_TABLE_FREE
65 select HAVE_SYSCALL_TRACEPOINTS
67 select MODULES_USE_ELF_RELA
70 select OF_EARLY_FLATTREE
71 select OF_RESERVED_MEM
72 select PERF_USE_VMALLOC
77 select SYSCTL_EXCEPTION_TRACE
78 select HAVE_CONTEXT_TRACKING
80 ARM 64-bit (AArch64) Linux support.
85 config ARCH_PHYS_ADDR_T_64BIT
94 config STACKTRACE_SUPPORT
97 config LOCKDEP_SUPPORT
100 config TRACE_IRQFLAGS_SUPPORT
103 config RWSEM_XCHGADD_ALGORITHM
106 config GENERIC_HWEIGHT
112 config GENERIC_CALIBRATE_DELAY
118 config HAVE_GENERIC_RCU_GUP
121 config ARCH_DMA_ADDR_T_64BIT
124 config NEED_DMA_MAP_STATE
127 config NEED_SG_DMA_LENGTH
136 config KERNEL_MODE_NEON
139 config FIX_EARLYCON_MEM
142 source "init/Kconfig"
144 source "kernel/Kconfig.freezer"
146 menu "Platform selection"
149 bool "Cavium Inc. Thunder SoC Family"
151 This enables support for Cavium's Thunder Family of SoCs.
154 bool "ARMv8 software model (Versatile Express)"
155 select ARCH_REQUIRE_GPIOLIB
156 select COMMON_CLK_VERSATILE
157 select POWER_RESET_VEXPRESS
158 select VEXPRESS_CONFIG
160 This enables support for the ARMv8 software model (Versatile
164 bool "AppliedMicro X-Gene SOC Family"
166 This enables support for AppliedMicro X-Gene SOC Family
178 This feature enables support for PCI bus system. If you say Y
179 here, the kernel will include drivers and infrastructure code
180 to support PCI bus devices.
185 config PCI_DOMAINS_GENERIC
191 source "drivers/pci/Kconfig"
192 source "drivers/pci/pcie/Kconfig"
193 source "drivers/pci/hotplug/Kconfig"
197 menu "Kernel Features"
199 menu "ARM errata workarounds via the alternatives framework"
201 config ARM64_ERRATUM_826319
202 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
205 This option adds an alternative code sequence to work around ARM
206 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
207 AXI master interface and an L2 cache.
209 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
210 and is unable to accept a certain write via this interface, it will
211 not progress on read data presented on the read data channel and the
214 The workaround promotes data cache clean instructions to
215 data cache clean-and-invalidate.
216 Please note that this does not necessarily enable the workaround,
217 as it depends on the alternative framework, which will only patch
218 the kernel if an affected CPU is detected.
222 config ARM64_ERRATUM_827319
223 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
226 This option adds an alternative code sequence to work around ARM
227 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
228 master interface and an L2 cache.
230 Under certain conditions this erratum can cause a clean line eviction
231 to occur at the same time as another transaction to the same address
232 on the AMBA 5 CHI interface, which can cause data corruption if the
233 interconnect reorders the two transactions.
235 The workaround promotes data cache clean instructions to
236 data cache clean-and-invalidate.
237 Please note that this does not necessarily enable the workaround,
238 as it depends on the alternative framework, which will only patch
239 the kernel if an affected CPU is detected.
243 config ARM64_ERRATUM_824069
244 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
247 This option adds an alternative code sequence to work around ARM
248 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
249 to a coherent interconnect.
251 If a Cortex-A53 processor is executing a store or prefetch for
252 write instruction at the same time as a processor in another
253 cluster is executing a cache maintenance operation to the same
254 address, then this erratum might cause a clean cache line to be
255 incorrectly marked as dirty.
257 The workaround promotes data cache clean instructions to
258 data cache clean-and-invalidate.
259 Please note that this option does not necessarily enable the
260 workaround, as it depends on the alternative framework, which will
261 only patch the kernel if an affected CPU is detected.
265 config ARM64_ERRATUM_819472
266 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
269 This option adds an alternative code sequence to work around ARM
270 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
271 present when it is connected to a coherent interconnect.
273 If the processor is executing a load and store exclusive sequence at
274 the same time as a processor in another cluster is executing a cache
275 maintenance operation to the same address, then this erratum might
276 cause data corruption.
278 The workaround promotes data cache clean instructions to
279 data cache clean-and-invalidate.
280 Please note that this does not necessarily enable the workaround,
281 as it depends on the alternative framework, which will only patch
282 the kernel if an affected CPU is detected.
286 config ARM64_ERRATUM_832075
287 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
290 This option adds an alternative code sequence to work around ARM
291 erratum 832075 on Cortex-A57 parts up to r1p2.
293 Affected Cortex-A57 parts might deadlock when exclusive load/store
294 instructions to Write-Back memory are mixed with Device loads.
296 The workaround is to promote device loads to use Load-Acquire
298 Please note that this does not necessarily enable the workaround,
299 as it depends on the alternative framework, which will only patch
300 the kernel if an affected CPU is detected.
309 default ARM64_4K_PAGES
311 Page size (translation granule) configuration.
313 config ARM64_4K_PAGES
316 This feature enables 4KB pages support.
318 config ARM64_64K_PAGES
321 This feature enables 64KB pages support (4KB by default)
322 allowing only two levels of page tables and faster TLB
323 look-up. AArch32 emulation is not available when this feature
329 prompt "Virtual address space size"
330 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
331 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
333 Allows choosing one of multiple possible virtual address
334 space sizes. The level of translation table is determined by
335 a combination of page size and virtual address space size.
337 config ARM64_VA_BITS_39
339 depends on ARM64_4K_PAGES
341 config ARM64_VA_BITS_42
343 depends on ARM64_64K_PAGES
345 config ARM64_VA_BITS_48
353 default 39 if ARM64_VA_BITS_39
354 default 42 if ARM64_VA_BITS_42
355 default 48 if ARM64_VA_BITS_48
357 config ARM64_PGTABLE_LEVELS
359 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
360 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
361 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
362 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
364 config CPU_BIG_ENDIAN
365 bool "Build big-endian kernel"
367 Say Y if you plan on running a kernel in big-endian mode.
370 bool "Symmetric Multi-Processing"
372 This enables support for systems with more than one CPU. If
373 you say N here, the kernel will run on single and
374 multiprocessor machines, but will use only one CPU of a
375 multiprocessor machine. If you say Y here, the kernel will run
376 on many, but not all, single processor machines. On a single
377 processor machine, the kernel will run faster if you say N
380 If you don't know what to do here, say N.
383 bool "Multi-core scheduler support"
386 Multi-core scheduler support improves the CPU scheduler's decision
387 making when dealing with multi-core CPU chips at a cost of slightly
388 increased overhead in some places. If unsure say N here.
391 bool "SMT scheduler support"
394 Improves the CPU scheduler's decision making when dealing with
395 MultiThreading at a cost of slightly increased overhead in some
396 places. If unsure say N here.
399 int "Maximum number of CPUs (2-64)"
402 # These have to remain sorted largest to smallest
406 bool "Support for hot-pluggable CPUs"
409 Say Y here to experiment with turning CPUs off and on. CPUs
410 can be controlled through /sys/devices/system/cpu.
412 source kernel/Kconfig.preempt
418 config ARCH_HAS_HOLES_MEMORYMODEL
419 def_bool y if SPARSEMEM
421 config ARCH_SPARSEMEM_ENABLE
423 select SPARSEMEM_VMEMMAP_ENABLE
425 config ARCH_SPARSEMEM_DEFAULT
426 def_bool ARCH_SPARSEMEM_ENABLE
428 config ARCH_SELECT_MEMORY_MODEL
429 def_bool ARCH_SPARSEMEM_ENABLE
431 config HAVE_ARCH_PFN_VALID
432 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
434 config HW_PERF_EVENTS
435 bool "Enable hardware performance counter support for perf events"
436 depends on PERF_EVENTS
439 Enable hardware performance counter support for perf events. If
440 disabled, perf events will use software events only.
442 config SYS_SUPPORTS_HUGETLBFS
445 config ARCH_WANT_GENERAL_HUGETLB
448 config ARCH_WANT_HUGE_PMD_SHARE
449 def_bool y if !ARM64_64K_PAGES
451 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
454 config ARCH_HAS_CACHE_LINE_SIZE
460 bool "Enable seccomp to safely compute untrusted bytecode"
462 This kernel feature is useful for number crunching applications
463 that may need to compute untrusted bytecode during their
464 execution. By using pipes or other transports made available to
465 the process as file descriptors supporting the read/write
466 syscalls, it's possible to isolate those applications in
467 their own address space using seccomp. Once seccomp is
468 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
469 and the task is only allowed to execute a few safe syscalls
470 defined by each seccomp mode.
477 bool "Xen guest support on ARM64"
478 depends on ARM64 && OF
481 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
483 config FORCE_MAX_ZONEORDER
485 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
488 menuconfig ARMV8_DEPRECATED
489 bool "Emulate deprecated/obsolete ARMv8 instructions"
492 Legacy software support may require certain instructions
493 that have been deprecated or obsoleted in the architecture.
495 Enable this config to enable selective emulation of these
503 bool "Emulate SWP/SWPB instructions"
505 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
506 they are always undefined. Say Y here to enable software
507 emulation of these instructions for userspace using LDXR/STXR.
509 In some older versions of glibc [<=2.8] SWP is used during futex
510 trylock() operations with the assumption that the code will not
511 be preempted. This invalid assumption may be more likely to fail
512 with SWP emulation enabled, leading to deadlock of the user
515 NOTE: when accessing uncached shared regions, LDXR/STXR rely
516 on an external transaction monitoring block called a global
517 monitor to maintain update atomicity. If your system does not
518 implement a global monitor, this option can cause programs that
519 perform SWP operations to uncached memory to deadlock.
523 config CP15_BARRIER_EMULATION
524 bool "Emulate CP15 Barrier instructions"
526 The CP15 barrier instructions - CP15ISB, CP15DSB, and
527 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
528 strongly recommended to use the ISB, DSB, and DMB
529 instructions instead.
531 Say Y here to enable software emulation of these
532 instructions for AArch32 userspace code. When this option is
533 enabled, CP15 barrier usage is traced which can help
534 identify software that needs updating.
545 string "Default kernel command string"
548 Provide a set of default command-line options at build time by
549 entering them here. As a minimum, you should specify the the
550 root device (e.g. root=/dev/nfs).
553 bool "Always use the default kernel command string"
555 Always use the default kernel command string, even if the boot
556 loader passes other arguments to the kernel.
557 This is useful if you cannot or don't want to change the
558 command-line options your boot loader passes to the kernel.
564 bool "UEFI runtime support"
565 depends on OF && !CPU_BIG_ENDIAN
568 select EFI_PARAMS_FROM_FDT
569 select EFI_RUNTIME_WRAPPERS
574 This option provides support for runtime services provided
575 by UEFI firmware (such as non-volatile variables, realtime
576 clock, and platform reset). A UEFI stub is also provided to
577 allow the kernel to be booted as an EFI application. This
578 is only useful on systems that have UEFI firmware.
581 bool "Enable support for SMBIOS (DMI) tables"
585 This enables SMBIOS/DMI feature for systems.
587 This option is only useful on systems that have UEFI firmware.
588 However, even with this option, the resultant kernel should
589 continue to boot on existing non-UEFI platforms.
593 menu "Userspace binary formats"
595 source "fs/Kconfig.binfmt"
598 bool "Kernel support for 32-bit EL0"
599 depends on !ARM64_64K_PAGES
600 select COMPAT_BINFMT_ELF
602 select OLD_SIGSUSPEND3
603 select COMPAT_OLD_SIGACTION
605 This option enables support for a 32-bit EL0 running under a 64-bit
606 kernel at EL1. AArch32-specific components such as system calls,
607 the user helper functions, VFP support and the ptrace interface are
608 handled appropriately by the kernel.
610 If you want to execute 32-bit userspace applications, say Y.
612 config SYSVIPC_COMPAT
614 depends on COMPAT && SYSVIPC
618 menu "Power management options"
620 source "kernel/power/Kconfig"
622 config ARCH_SUSPEND_POSSIBLE
625 config ARM64_CPU_SUSPEND
630 menu "CPU Power Management"
632 source "drivers/cpuidle/Kconfig"
634 source "drivers/cpufreq/Kconfig"
640 source "drivers/Kconfig"
642 source "drivers/firmware/Kconfig"
646 source "arch/arm64/kvm/Kconfig"
648 source "arch/arm64/Kconfig.debug"
650 source "security/Kconfig"
652 source "crypto/Kconfig"
654 source "arch/arm64/crypto/Kconfig"