3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_DEVMEM_IS_ALLOWED
7 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
8 select ARCH_HAS_ELF_RANDOMIZE
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_HAS_SG_CHAIN
11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_SUPPORTS_ATOMIC_RMW
14 select ARCH_SUPPORTS_NUMA_BALANCING
15 select ARCH_WANT_OPTIONAL_GPIOLIB
16 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
17 select ARCH_WANT_FRAME_POINTERS
18 select ARCH_HAS_UBSAN_SANITIZE_ALL
22 select AUDIT_ARCH_COMPAT_GENERIC
23 select ARM_GIC_V2M if PCI_MSI
25 select ARM_GIC_V3_ITS if PCI_MSI
27 select BUILDTIME_EXTABLE_SORT
28 select CLONE_BACKWARDS
30 select CPU_PM if (SUSPEND || CPU_IDLE)
31 select DCACHE_WORD_ACCESS
34 select GENERIC_ALLOCATOR
35 select GENERIC_CLOCKEVENTS
36 select GENERIC_CLOCKEVENTS_BROADCAST
37 select GENERIC_CPU_AUTOPROBE
38 select GENERIC_EARLY_IOREMAP
39 select GENERIC_IDLE_POLL_SETUP
40 select GENERIC_IRQ_PROBE
41 select GENERIC_IRQ_SHOW
42 select GENERIC_IRQ_SHOW_LEVEL
43 select GENERIC_PCI_IOMAP
44 select GENERIC_SCHED_CLOCK
45 select GENERIC_SMP_IDLE_THREAD
46 select GENERIC_STRNCPY_FROM_USER
47 select GENERIC_STRNLEN_USER
48 select GENERIC_TIME_VSYSCALL
49 select HANDLE_DOMAIN_IRQ
50 select HARDIRQS_SW_RESEND
51 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
52 select HAVE_ARCH_AUDITSYSCALL
53 select HAVE_ARCH_BITREVERSE
54 select HAVE_ARCH_HUGE_VMAP
55 select HAVE_ARCH_JUMP_LABEL
56 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
58 select HAVE_ARCH_MMAP_RND_BITS
59 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
60 select HAVE_ARCH_SECCOMP_FILTER
61 select HAVE_ARCH_TRACEHOOK
62 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
65 select HAVE_C_RECORDMCOUNT
66 select HAVE_CC_STACKPROTECTOR
67 select HAVE_CMPXCHG_DOUBLE
68 select HAVE_CMPXCHG_LOCAL
69 select HAVE_CONTEXT_TRACKING
70 select HAVE_DEBUG_BUGVERBOSE
71 select HAVE_DEBUG_KMEMLEAK
72 select HAVE_DMA_API_DEBUG
73 select HAVE_DMA_CONTIGUOUS
74 select HAVE_DYNAMIC_FTRACE
75 select HAVE_EFFICIENT_UNALIGNED_ACCESS
76 select HAVE_FTRACE_MCOUNT_RECORD
77 select HAVE_FUNCTION_TRACER
78 select HAVE_FUNCTION_GRAPH_TRACER
79 select HAVE_GENERIC_DMA_COHERENT
80 select HAVE_HW_BREAKPOINT if PERF_EVENTS
81 select HAVE_IRQ_TIME_ACCOUNTING
83 select HAVE_MEMBLOCK_NODE_MAP if NUMA
84 select HAVE_PATA_PLATFORM
85 select HAVE_PERF_EVENTS
87 select HAVE_PERF_USER_STACK_DUMP
88 select HAVE_REGS_AND_STACK_ACCESS_API
89 select HAVE_RCU_TABLE_FREE
90 select HAVE_SYSCALL_TRACEPOINTS
92 select HAVE_KRETPROBES if HAVE_KPROBES
93 select IOMMU_DMA if IOMMU_SUPPORT
95 select IRQ_FORCED_THREADING
96 select MODULES_USE_ELF_RELA
99 select OF_EARLY_FLATTREE
100 select OF_NUMA if NUMA && OF
101 select OF_RESERVED_MEM
102 select PERF_USE_VMALLOC
106 select SYSCTL_EXCEPTION_TRACE
108 ARM 64-bit (AArch64) Linux support.
113 config ARCH_PHYS_ADDR_T_64BIT
119 config ARM64_PAGE_SHIFT
121 default 16 if ARM64_64K_PAGES
122 default 14 if ARM64_16K_PAGES
125 config ARM64_CONT_SHIFT
127 default 5 if ARM64_64K_PAGES
128 default 7 if ARM64_16K_PAGES
131 config ARCH_MMAP_RND_BITS_MIN
132 default 14 if ARM64_64K_PAGES
133 default 16 if ARM64_16K_PAGES
136 # max bits determined by the following formula:
137 # VA_BITS - PAGE_SHIFT - 3
138 config ARCH_MMAP_RND_BITS_MAX
139 default 19 if ARM64_VA_BITS=36
140 default 24 if ARM64_VA_BITS=39
141 default 27 if ARM64_VA_BITS=42
142 default 30 if ARM64_VA_BITS=47
143 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
144 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
145 default 33 if ARM64_VA_BITS=48
146 default 14 if ARM64_64K_PAGES
147 default 16 if ARM64_16K_PAGES
150 config ARCH_MMAP_RND_COMPAT_BITS_MIN
151 default 7 if ARM64_64K_PAGES
152 default 9 if ARM64_16K_PAGES
155 config ARCH_MMAP_RND_COMPAT_BITS_MAX
161 config STACKTRACE_SUPPORT
164 config ILLEGAL_POINTER_VALUE
166 default 0xdead000000000000
168 config LOCKDEP_SUPPORT
171 config TRACE_IRQFLAGS_SUPPORT
174 config RWSEM_XCHGADD_ALGORITHM
181 config GENERIC_BUG_RELATIVE_POINTERS
183 depends on GENERIC_BUG
185 config GENERIC_HWEIGHT
191 config GENERIC_CALIBRATE_DELAY
197 config HAVE_GENERIC_RCU_GUP
200 config ARCH_DMA_ADDR_T_64BIT
203 config NEED_DMA_MAP_STATE
206 config NEED_SG_DMA_LENGTH
218 config KERNEL_MODE_NEON
221 config FIX_EARLYCON_MEM
224 config PGTABLE_LEVELS
226 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
227 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
228 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
229 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
230 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
231 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
233 source "init/Kconfig"
235 source "kernel/Kconfig.freezer"
237 source "arch/arm64/Kconfig.platforms"
244 This feature enables support for PCI bus system. If you say Y
245 here, the kernel will include drivers and infrastructure code
246 to support PCI bus devices.
251 config PCI_DOMAINS_GENERIC
257 source "drivers/pci/Kconfig"
261 menu "Kernel Features"
263 menu "ARM errata workarounds via the alternatives framework"
265 config ARM64_ERRATUM_826319
266 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
269 This option adds an alternative code sequence to work around ARM
270 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
271 AXI master interface and an L2 cache.
273 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
274 and is unable to accept a certain write via this interface, it will
275 not progress on read data presented on the read data channel and the
278 The workaround promotes data cache clean instructions to
279 data cache clean-and-invalidate.
280 Please note that this does not necessarily enable the workaround,
281 as it depends on the alternative framework, which will only patch
282 the kernel if an affected CPU is detected.
286 config ARM64_ERRATUM_827319
287 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
290 This option adds an alternative code sequence to work around ARM
291 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
292 master interface and an L2 cache.
294 Under certain conditions this erratum can cause a clean line eviction
295 to occur at the same time as another transaction to the same address
296 on the AMBA 5 CHI interface, which can cause data corruption if the
297 interconnect reorders the two transactions.
299 The workaround promotes data cache clean instructions to
300 data cache clean-and-invalidate.
301 Please note that this does not necessarily enable the workaround,
302 as it depends on the alternative framework, which will only patch
303 the kernel if an affected CPU is detected.
307 config ARM64_ERRATUM_824069
308 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
311 This option adds an alternative code sequence to work around ARM
312 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
313 to a coherent interconnect.
315 If a Cortex-A53 processor is executing a store or prefetch for
316 write instruction at the same time as a processor in another
317 cluster is executing a cache maintenance operation to the same
318 address, then this erratum might cause a clean cache line to be
319 incorrectly marked as dirty.
321 The workaround promotes data cache clean instructions to
322 data cache clean-and-invalidate.
323 Please note that this option does not necessarily enable the
324 workaround, as it depends on the alternative framework, which will
325 only patch the kernel if an affected CPU is detected.
329 config ARM64_ERRATUM_819472
330 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
333 This option adds an alternative code sequence to work around ARM
334 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
335 present when it is connected to a coherent interconnect.
337 If the processor is executing a load and store exclusive sequence at
338 the same time as a processor in another cluster is executing a cache
339 maintenance operation to the same address, then this erratum might
340 cause data corruption.
342 The workaround promotes data cache clean instructions to
343 data cache clean-and-invalidate.
344 Please note that this does not necessarily enable the workaround,
345 as it depends on the alternative framework, which will only patch
346 the kernel if an affected CPU is detected.
350 config ARM64_ERRATUM_832075
351 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
354 This option adds an alternative code sequence to work around ARM
355 erratum 832075 on Cortex-A57 parts up to r1p2.
357 Affected Cortex-A57 parts might deadlock when exclusive load/store
358 instructions to Write-Back memory are mixed with Device loads.
360 The workaround is to promote device loads to use Load-Acquire
362 Please note that this does not necessarily enable the workaround,
363 as it depends on the alternative framework, which will only patch
364 the kernel if an affected CPU is detected.
368 config ARM64_ERRATUM_834220
369 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
373 This option adds an alternative code sequence to work around ARM
374 erratum 834220 on Cortex-A57 parts up to r1p2.
376 Affected Cortex-A57 parts might report a Stage 2 translation
377 fault as the result of a Stage 1 fault for load crossing a
378 page boundary when there is a permission or device memory
379 alignment fault at Stage 1 and a translation fault at Stage 2.
381 The workaround is to verify that the Stage 1 translation
382 doesn't generate a fault before handling the Stage 2 fault.
383 Please note that this does not necessarily enable the workaround,
384 as it depends on the alternative framework, which will only patch
385 the kernel if an affected CPU is detected.
389 config ARM64_ERRATUM_845719
390 bool "Cortex-A53: 845719: a load might read incorrect data"
394 This option adds an alternative code sequence to work around ARM
395 erratum 845719 on Cortex-A53 parts up to r0p4.
397 When running a compat (AArch32) userspace on an affected Cortex-A53
398 part, a load at EL0 from a virtual address that matches the bottom 32
399 bits of the virtual address used by a recent load at (AArch64) EL1
400 might return incorrect data.
402 The workaround is to write the contextidr_el1 register on exception
403 return to a 32-bit task.
404 Please note that this does not necessarily enable the workaround,
405 as it depends on the alternative framework, which will only patch
406 the kernel if an affected CPU is detected.
410 config ARM64_ERRATUM_843419
411 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
414 select ARM64_MODULE_CMODEL_LARGE
416 This option builds kernel modules using the large memory model in
417 order to avoid the use of the ADRP instruction, which can cause
418 a subsequent memory access to use an incorrect address on Cortex-A53
421 Note that the kernel itself must be linked with a version of ld
422 which fixes potentially affected ADRP instructions through the
427 config CAVIUM_ERRATUM_22375
428 bool "Cavium erratum 22375, 24313"
431 Enable workaround for erratum 22375, 24313.
433 This implements two gicv3-its errata workarounds for ThunderX. Both
434 with small impact affecting only ITS table allocation.
436 erratum 22375: only alloc 8MB table size
437 erratum 24313: ignore memory access type
439 The fixes are in ITS initialization and basically ignore memory access
440 type and table size provided by the TYPER and BASER registers.
444 config CAVIUM_ERRATUM_23144
445 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
449 ITS SYNC command hang for cross node io and collections/cpu mapping.
453 config CAVIUM_ERRATUM_23154
454 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
457 The gicv3 of ThunderX requires a modified version for
458 reading the IAR status to ensure data synchronization
459 (access to icc_iar1_el1 is not sync'ed before and after).
463 config CAVIUM_ERRATUM_27456
464 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
467 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
468 instructions may cause the icache to become corrupted if it
469 contains data for a non-current ASID. The fix is to
470 invalidate the icache when changing the mm context.
479 default ARM64_4K_PAGES
481 Page size (translation granule) configuration.
483 config ARM64_4K_PAGES
486 This feature enables 4KB pages support.
488 config ARM64_16K_PAGES
491 The system will use 16KB pages support. AArch32 emulation
492 requires applications compiled with 16K (or a multiple of 16K)
495 config ARM64_64K_PAGES
498 This feature enables 64KB pages support (4KB by default)
499 allowing only two levels of page tables and faster TLB
500 look-up. AArch32 emulation requires applications compiled
501 with 64K aligned segments.
506 prompt "Virtual address space size"
507 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
508 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
509 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
511 Allows choosing one of multiple possible virtual address
512 space sizes. The level of translation table is determined by
513 a combination of page size and virtual address space size.
515 config ARM64_VA_BITS_36
516 bool "36-bit" if EXPERT
517 depends on ARM64_16K_PAGES
519 config ARM64_VA_BITS_39
521 depends on ARM64_4K_PAGES
523 config ARM64_VA_BITS_42
525 depends on ARM64_64K_PAGES
527 config ARM64_VA_BITS_47
529 depends on ARM64_16K_PAGES
531 config ARM64_VA_BITS_48
538 default 36 if ARM64_VA_BITS_36
539 default 39 if ARM64_VA_BITS_39
540 default 42 if ARM64_VA_BITS_42
541 default 47 if ARM64_VA_BITS_47
542 default 48 if ARM64_VA_BITS_48
544 config CPU_BIG_ENDIAN
545 bool "Build big-endian kernel"
547 Say Y if you plan on running a kernel in big-endian mode.
550 bool "Multi-core scheduler support"
552 Multi-core scheduler support improves the CPU scheduler's decision
553 making when dealing with multi-core CPU chips at a cost of slightly
554 increased overhead in some places. If unsure say N here.
557 bool "SMT scheduler support"
559 Improves the CPU scheduler's decision making when dealing with
560 MultiThreading at a cost of slightly increased overhead in some
561 places. If unsure say N here.
564 int "Maximum number of CPUs (2-4096)"
566 # These have to remain sorted largest to smallest
570 bool "Support for hot-pluggable CPUs"
571 select GENERIC_IRQ_MIGRATION
573 Say Y here to experiment with turning CPUs off and on. CPUs
574 can be controlled through /sys/devices/system/cpu.
576 # Common NUMA Features
578 bool "Numa Memory Allocation and Scheduler Support"
581 Enable NUMA (Non Uniform Memory Access) support.
583 The kernel will try to allocate memory used by a CPU on the
584 local memory of the CPU and add some more
585 NUMA awareness to the kernel.
588 int "Maximum NUMA Nodes (as a power of 2)"
591 depends on NEED_MULTIPLE_NODES
593 Specify the maximum number of NUMA Nodes available on the target
594 system. Increases memory reserved to accommodate various tables.
596 config USE_PERCPU_NUMA_NODE_ID
600 source kernel/Kconfig.preempt
601 source kernel/Kconfig.hz
603 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
604 depends on !HIBERNATION
607 config ARCH_HAS_HOLES_MEMORYMODEL
608 def_bool y if SPARSEMEM
610 config ARCH_SPARSEMEM_ENABLE
612 select SPARSEMEM_VMEMMAP_ENABLE
614 config ARCH_SPARSEMEM_DEFAULT
615 def_bool ARCH_SPARSEMEM_ENABLE
617 config ARCH_SELECT_MEMORY_MODEL
618 def_bool ARCH_SPARSEMEM_ENABLE
620 config HAVE_ARCH_PFN_VALID
621 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
623 config HW_PERF_EVENTS
627 config SYS_SUPPORTS_HUGETLBFS
630 config ARCH_WANT_HUGE_PMD_SHARE
631 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
633 config ARCH_HAS_CACHE_LINE_SIZE
639 bool "Enable seccomp to safely compute untrusted bytecode"
641 This kernel feature is useful for number crunching applications
642 that may need to compute untrusted bytecode during their
643 execution. By using pipes or other transports made available to
644 the process as file descriptors supporting the read/write
645 syscalls, it's possible to isolate those applications in
646 their own address space using seccomp. Once seccomp is
647 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
648 and the task is only allowed to execute a few safe syscalls
649 defined by each seccomp mode.
652 bool "Enable paravirtualization code"
654 This changes the kernel so it can modify itself when it is run
655 under a hypervisor, potentially improving performance significantly
656 over full virtualization.
658 config PARAVIRT_TIME_ACCOUNTING
659 bool "Paravirtual steal time accounting"
663 Select this option to enable fine granularity task steal time
664 accounting. Time spent executing other tasks in parallel with
665 the current vCPU is discounted from the vCPU power. To account for
666 that, there can be a small performance impact.
668 If in doubt, say N here.
675 bool "Xen guest support on ARM64"
676 depends on ARM64 && OF
680 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
682 config FORCE_MAX_ZONEORDER
684 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
685 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
688 The kernel memory allocator divides physically contiguous memory
689 blocks into "zones", where each zone is a power of two number of
690 pages. This option selects the largest power of two that the kernel
691 keeps in the memory allocator. If you need to allocate very large
692 blocks of physically contiguous memory, then you may need to
695 This config option is actually maximum order plus one. For example,
696 a value of 11 means that the largest free memory block is 2^10 pages.
698 We make sure that we can allocate upto a HugePage size for each configuration.
700 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
702 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
703 4M allocations matching the default size used by generic code.
705 menuconfig ARMV8_DEPRECATED
706 bool "Emulate deprecated/obsolete ARMv8 instructions"
709 Legacy software support may require certain instructions
710 that have been deprecated or obsoleted in the architecture.
712 Enable this config to enable selective emulation of these
720 bool "Emulate SWP/SWPB instructions"
722 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
723 they are always undefined. Say Y here to enable software
724 emulation of these instructions for userspace using LDXR/STXR.
726 In some older versions of glibc [<=2.8] SWP is used during futex
727 trylock() operations with the assumption that the code will not
728 be preempted. This invalid assumption may be more likely to fail
729 with SWP emulation enabled, leading to deadlock of the user
732 NOTE: when accessing uncached shared regions, LDXR/STXR rely
733 on an external transaction monitoring block called a global
734 monitor to maintain update atomicity. If your system does not
735 implement a global monitor, this option can cause programs that
736 perform SWP operations to uncached memory to deadlock.
740 config CP15_BARRIER_EMULATION
741 bool "Emulate CP15 Barrier instructions"
743 The CP15 barrier instructions - CP15ISB, CP15DSB, and
744 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
745 strongly recommended to use the ISB, DSB, and DMB
746 instructions instead.
748 Say Y here to enable software emulation of these
749 instructions for AArch32 userspace code. When this option is
750 enabled, CP15 barrier usage is traced which can help
751 identify software that needs updating.
755 config SETEND_EMULATION
756 bool "Emulate SETEND instruction"
758 The SETEND instruction alters the data-endianness of the
759 AArch32 EL0, and is deprecated in ARMv8.
761 Say Y here to enable software emulation of the instruction
762 for AArch32 userspace code.
764 Note: All the cpus on the system must have mixed endian support at EL0
765 for this feature to be enabled. If a new CPU - which doesn't support mixed
766 endian - is hotplugged in after this feature has been enabled, there could
767 be unexpected results in the applications.
772 menu "ARMv8.1 architectural features"
774 config ARM64_HW_AFDBM
775 bool "Support for hardware updates of the Access and Dirty page flags"
778 The ARMv8.1 architecture extensions introduce support for
779 hardware updates of the access and dirty information in page
780 table entries. When enabled in TCR_EL1 (HA and HD bits) on
781 capable processors, accesses to pages with PTE_AF cleared will
782 set this bit instead of raising an access flag fault.
783 Similarly, writes to read-only pages with the DBM bit set will
784 clear the read-only bit (AP[2]) instead of raising a
787 Kernels built with this configuration option enabled continue
788 to work on pre-ARMv8.1 hardware and the performance impact is
789 minimal. If unsure, say Y.
792 bool "Enable support for Privileged Access Never (PAN)"
795 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
796 prevents the kernel or hypervisor from accessing user-space (EL0)
799 Choosing this option will cause any unprotected (not using
800 copy_to_user et al) memory access to fail with a permission fault.
802 The feature is detected at runtime, and will remain as a 'nop'
803 instruction if the cpu does not implement the feature.
805 config ARM64_LSE_ATOMICS
806 bool "Atomic instructions"
808 As part of the Large System Extensions, ARMv8.1 introduces new
809 atomic instructions that are designed specifically to scale in
812 Say Y here to make use of these instructions for the in-kernel
813 atomic routines. This incurs a small overhead on CPUs that do
814 not support these instructions and requires the kernel to be
815 built with binutils >= 2.25.
818 bool "Enable support for Virtualization Host Extensions (VHE)"
821 Virtualization Host Extensions (VHE) allow the kernel to run
822 directly at EL2 (instead of EL1) on processors that support
823 it. This leads to better performance for KVM, as they reduce
824 the cost of the world switch.
826 Selecting this option allows the VHE feature to be detected
827 at runtime, and does not affect processors that do not
828 implement this feature.
832 menu "ARMv8.2 architectural features"
835 bool "Enable support for User Access Override (UAO)"
838 User Access Override (UAO; part of the ARMv8.2 Extensions)
839 causes the 'unprivileged' variant of the load/store instructions to
840 be overriden to be privileged.
842 This option changes get_user() and friends to use the 'unprivileged'
843 variant of the load/store instructions. This ensures that user-space
844 really did have access to the supplied memory. When addr_limit is
845 set to kernel memory the UAO bit will be set, allowing privileged
846 access to kernel memory.
848 Choosing this option will cause copy_to_user() et al to use user-space
851 The feature is detected at runtime, the kernel will use the
852 regular load/store instructions if the cpu does not implement the
857 config ARM64_MODULE_CMODEL_LARGE
860 config ARM64_MODULE_PLTS
862 select ARM64_MODULE_CMODEL_LARGE
863 select HAVE_MOD_ARCH_SPECIFIC
868 This builds the kernel as a Position Independent Executable (PIE),
869 which retains all relocation metadata required to relocate the
870 kernel binary at runtime to a different virtual address than the
871 address it was linked at.
872 Since AArch64 uses the RELA relocation format, this requires a
873 relocation pass at runtime even if the kernel is loaded at the
874 same address it was linked at.
876 config RANDOMIZE_BASE
877 bool "Randomize the address of the kernel image"
878 select ARM64_MODULE_PLTS
881 Randomizes the virtual address at which the kernel image is
882 loaded, as a security feature that deters exploit attempts
883 relying on knowledge of the location of kernel internals.
885 It is the bootloader's job to provide entropy, by passing a
886 random u64 value in /chosen/kaslr-seed at kernel entry.
888 When booting via the UEFI stub, it will invoke the firmware's
889 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
890 to the kernel proper. In addition, it will randomise the physical
891 location of the kernel Image as well.
895 config RANDOMIZE_MODULE_REGION_FULL
896 bool "Randomize the module region independently from the core kernel"
897 depends on RANDOMIZE_BASE
900 Randomizes the location of the module region without considering the
901 location of the core kernel. This way, it is impossible for modules
902 to leak information about the location of core kernel data structures
903 but it does imply that function calls between modules and the core
904 kernel will need to be resolved via veneers in the module PLT.
906 When this option is not set, the module region will be randomized over
907 a limited range that contains the [_stext, _etext] interval of the
908 core kernel, so branch relocations are always in range.
914 config ARM64_ACPI_PARKING_PROTOCOL
915 bool "Enable support for the ARM64 ACPI parking protocol"
918 Enable support for the ARM64 ACPI parking protocol. If disabled
919 the kernel will not allow booting through the ARM64 ACPI parking
920 protocol even if the corresponding data is present in the ACPI
924 string "Default kernel command string"
927 Provide a set of default command-line options at build time by
928 entering them here. As a minimum, you should specify the the
929 root device (e.g. root=/dev/nfs).
932 bool "Always use the default kernel command string"
934 Always use the default kernel command string, even if the boot
935 loader passes other arguments to the kernel.
936 This is useful if you cannot or don't want to change the
937 command-line options your boot loader passes to the kernel.
943 bool "UEFI runtime support"
944 depends on OF && !CPU_BIG_ENDIAN
947 select EFI_PARAMS_FROM_FDT
948 select EFI_RUNTIME_WRAPPERS
953 This option provides support for runtime services provided
954 by UEFI firmware (such as non-volatile variables, realtime
955 clock, and platform reset). A UEFI stub is also provided to
956 allow the kernel to be booted as an EFI application. This
957 is only useful on systems that have UEFI firmware.
960 bool "Enable support for SMBIOS (DMI) tables"
964 This enables SMBIOS/DMI feature for systems.
966 This option is only useful on systems that have UEFI firmware.
967 However, even with this option, the resultant kernel should
968 continue to boot on existing non-UEFI platforms.
972 menu "Userspace binary formats"
974 source "fs/Kconfig.binfmt"
977 bool "Kernel support for 32-bit EL0"
978 depends on ARM64_4K_PAGES || EXPERT
979 select COMPAT_BINFMT_ELF
981 select OLD_SIGSUSPEND3
982 select COMPAT_OLD_SIGACTION
984 This option enables support for a 32-bit EL0 running under a 64-bit
985 kernel at EL1. AArch32-specific components such as system calls,
986 the user helper functions, VFP support and the ptrace interface are
987 handled appropriately by the kernel.
989 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
990 that you will only be able to execute AArch32 binaries that were compiled
991 with page size aligned segments.
993 If you want to execute 32-bit userspace applications, say Y.
995 config SYSVIPC_COMPAT
997 depends on COMPAT && SYSVIPC
1001 menu "Power management options"
1003 source "kernel/power/Kconfig"
1005 config ARCH_HIBERNATION_POSSIBLE
1009 config ARCH_HIBERNATION_HEADER
1011 depends on HIBERNATION
1013 config ARCH_SUSPEND_POSSIBLE
1018 menu "CPU Power Management"
1020 source "drivers/cpuidle/Kconfig"
1022 source "drivers/cpufreq/Kconfig"
1026 source "net/Kconfig"
1028 source "drivers/Kconfig"
1030 source "drivers/firmware/Kconfig"
1032 source "drivers/acpi/Kconfig"
1036 source "arch/arm64/kvm/Kconfig"
1038 source "arch/arm64/Kconfig.debug"
1040 source "security/Kconfig"
1042 source "crypto/Kconfig"
1044 source "arch/arm64/crypto/Kconfig"
1047 source "lib/Kconfig"