3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
15 select ARCH_HAS_ELF_RANDOMIZE
16 select ARCH_HAS_FAST_MULTIPLIER
17 select ARCH_HAS_FORTIFY_SOURCE
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
21 select ARCH_HAS_MEMBARRIER_SYNC_CORE
22 select ARCH_HAS_PTE_SPECIAL
23 select ARCH_HAS_SET_MEMORY
24 select ARCH_HAS_SG_CHAIN
25 select ARCH_HAS_STRICT_KERNEL_RWX
26 select ARCH_HAS_STRICT_MODULE_RWX
27 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
28 select ARCH_HAVE_NMI_SAFE_CMPXCHG
29 select ARCH_INLINE_READ_LOCK if !PREEMPT
30 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
31 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
32 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
33 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
34 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
35 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
36 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
37 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
38 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
39 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
41 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
42 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
43 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
44 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
45 select ARCH_USE_CMPXCHG_LOCKREF
46 select ARCH_USE_QUEUED_RWLOCKS
47 select ARCH_SUPPORTS_MEMORY_FAILURE
48 select ARCH_SUPPORTS_ATOMIC_RMW
49 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
50 select ARCH_SUPPORTS_NUMA_BALANCING
51 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
52 select ARCH_WANT_FRAME_POINTERS
53 select ARCH_HAS_UBSAN_SANITIZE_ALL
57 select AUDIT_ARCH_COMPAT_GENERIC
58 select ARM_GIC_V2M if PCI
60 select ARM_GIC_V3_ITS if PCI
62 select BUILDTIME_EXTABLE_SORT
63 select CLONE_BACKWARDS
65 select CPU_PM if (SUSPEND || CPU_IDLE)
66 select DCACHE_WORD_ACCESS
70 select GENERIC_ALLOCATOR
71 select GENERIC_ARCH_TOPOLOGY
72 select GENERIC_CLOCKEVENTS
73 select GENERIC_CLOCKEVENTS_BROADCAST
74 select GENERIC_CPU_AUTOPROBE
75 select GENERIC_EARLY_IOREMAP
76 select GENERIC_IDLE_POLL_SETUP
77 select GENERIC_IRQ_PROBE
78 select GENERIC_IRQ_SHOW
79 select GENERIC_IRQ_SHOW_LEVEL
80 select GENERIC_PCI_IOMAP
81 select GENERIC_SCHED_CLOCK
82 select GENERIC_SMP_IDLE_THREAD
83 select GENERIC_STRNCPY_FROM_USER
84 select GENERIC_STRNLEN_USER
85 select GENERIC_TIME_VSYSCALL
86 select HANDLE_DOMAIN_IRQ
87 select HARDIRQS_SW_RESEND
88 select HAVE_ACPI_APEI if (ACPI && EFI)
89 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
90 select HAVE_ARCH_AUDITSYSCALL
91 select HAVE_ARCH_BITREVERSE
92 select HAVE_ARCH_HUGE_VMAP
93 select HAVE_ARCH_JUMP_LABEL
94 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
96 select HAVE_ARCH_MMAP_RND_BITS
97 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
98 select HAVE_ARCH_SECCOMP_FILTER
99 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
100 select HAVE_ARCH_TRACEHOOK
101 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
102 select HAVE_ARCH_VMAP_STACK
103 select HAVE_ARM_SMCCC
105 select HAVE_C_RECORDMCOUNT
106 select HAVE_CMPXCHG_DOUBLE
107 select HAVE_CMPXCHG_LOCAL
108 select HAVE_CONTEXT_TRACKING
109 select HAVE_DEBUG_BUGVERBOSE
110 select HAVE_DEBUG_KMEMLEAK
111 select HAVE_DMA_CONTIGUOUS
112 select HAVE_DYNAMIC_FTRACE
113 select HAVE_EFFICIENT_UNALIGNED_ACCESS
114 select HAVE_FTRACE_MCOUNT_RECORD
115 select HAVE_FUNCTION_TRACER
116 select HAVE_FUNCTION_GRAPH_TRACER
117 select HAVE_GCC_PLUGINS
118 select HAVE_GENERIC_DMA_COHERENT
119 select HAVE_HW_BREAKPOINT if PERF_EVENTS
120 select HAVE_IRQ_TIME_ACCOUNTING
122 select HAVE_MEMBLOCK_NODE_MAP if NUMA
124 select HAVE_PATA_PLATFORM
125 select HAVE_PERF_EVENTS
126 select HAVE_PERF_REGS
127 select HAVE_PERF_USER_STACK_DUMP
128 select HAVE_REGS_AND_STACK_ACCESS_API
129 select HAVE_RCU_TABLE_FREE
130 select HAVE_STACKPROTECTOR
131 select HAVE_SYSCALL_TRACEPOINTS
133 select HAVE_KRETPROBES
134 select IOMMU_DMA if IOMMU_SUPPORT
136 select IRQ_FORCED_THREADING
137 select MODULES_USE_ELF_RELA
138 select MULTI_IRQ_HANDLER
139 select NEED_DMA_MAP_STATE
140 select NEED_SG_DMA_LENGTH
143 select OF_EARLY_FLATTREE
144 select OF_RESERVED_MEM
145 select PCI_ECAM if ACPI
151 select SYSCTL_EXCEPTION_TRACE
152 select THREAD_INFO_IN_TASK
154 ARM 64-bit (AArch64) Linux support.
162 config ARM64_PAGE_SHIFT
164 default 16 if ARM64_64K_PAGES
165 default 14 if ARM64_16K_PAGES
168 config ARM64_CONT_SHIFT
170 default 5 if ARM64_64K_PAGES
171 default 7 if ARM64_16K_PAGES
174 config ARCH_MMAP_RND_BITS_MIN
175 default 14 if ARM64_64K_PAGES
176 default 16 if ARM64_16K_PAGES
179 # max bits determined by the following formula:
180 # VA_BITS - PAGE_SHIFT - 3
181 config ARCH_MMAP_RND_BITS_MAX
182 default 19 if ARM64_VA_BITS=36
183 default 24 if ARM64_VA_BITS=39
184 default 27 if ARM64_VA_BITS=42
185 default 30 if ARM64_VA_BITS=47
186 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
187 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
188 default 33 if ARM64_VA_BITS=48
189 default 14 if ARM64_64K_PAGES
190 default 16 if ARM64_16K_PAGES
193 config ARCH_MMAP_RND_COMPAT_BITS_MIN
194 default 7 if ARM64_64K_PAGES
195 default 9 if ARM64_16K_PAGES
198 config ARCH_MMAP_RND_COMPAT_BITS_MAX
204 config STACKTRACE_SUPPORT
207 config ILLEGAL_POINTER_VALUE
209 default 0xdead000000000000
211 config LOCKDEP_SUPPORT
214 config TRACE_IRQFLAGS_SUPPORT
217 config RWSEM_XCHGADD_ALGORITHM
224 config GENERIC_BUG_RELATIVE_POINTERS
226 depends on GENERIC_BUG
228 config GENERIC_HWEIGHT
234 config GENERIC_CALIBRATE_DELAY
240 config HAVE_GENERIC_GUP
246 config KERNEL_MODE_NEON
249 config FIX_EARLYCON_MEM
252 config PGTABLE_LEVELS
254 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
255 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
256 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
257 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
258 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
259 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
261 config ARCH_SUPPORTS_UPROBES
264 config ARCH_PROC_KCORE_TEXT
267 config MULTI_IRQ_HANDLER
270 source "arch/arm64/Kconfig.platforms"
277 This feature enables support for PCI bus system. If you say Y
278 here, the kernel will include drivers and infrastructure code
279 to support PCI bus devices.
284 config PCI_DOMAINS_GENERIC
290 source "drivers/pci/Kconfig"
294 menu "Kernel Features"
296 menu "ARM errata workarounds via the alternatives framework"
298 config ARM64_ERRATUM_826319
299 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
302 This option adds an alternative code sequence to work around ARM
303 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
304 AXI master interface and an L2 cache.
306 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
307 and is unable to accept a certain write via this interface, it will
308 not progress on read data presented on the read data channel and the
311 The workaround promotes data cache clean instructions to
312 data cache clean-and-invalidate.
313 Please note that this does not necessarily enable the workaround,
314 as it depends on the alternative framework, which will only patch
315 the kernel if an affected CPU is detected.
319 config ARM64_ERRATUM_827319
320 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
323 This option adds an alternative code sequence to work around ARM
324 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
325 master interface and an L2 cache.
327 Under certain conditions this erratum can cause a clean line eviction
328 to occur at the same time as another transaction to the same address
329 on the AMBA 5 CHI interface, which can cause data corruption if the
330 interconnect reorders the two transactions.
332 The workaround promotes data cache clean instructions to
333 data cache clean-and-invalidate.
334 Please note that this does not necessarily enable the workaround,
335 as it depends on the alternative framework, which will only patch
336 the kernel if an affected CPU is detected.
340 config ARM64_ERRATUM_824069
341 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
344 This option adds an alternative code sequence to work around ARM
345 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
346 to a coherent interconnect.
348 If a Cortex-A53 processor is executing a store or prefetch for
349 write instruction at the same time as a processor in another
350 cluster is executing a cache maintenance operation to the same
351 address, then this erratum might cause a clean cache line to be
352 incorrectly marked as dirty.
354 The workaround promotes data cache clean instructions to
355 data cache clean-and-invalidate.
356 Please note that this option does not necessarily enable the
357 workaround, as it depends on the alternative framework, which will
358 only patch the kernel if an affected CPU is detected.
362 config ARM64_ERRATUM_819472
363 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
366 This option adds an alternative code sequence to work around ARM
367 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
368 present when it is connected to a coherent interconnect.
370 If the processor is executing a load and store exclusive sequence at
371 the same time as a processor in another cluster is executing a cache
372 maintenance operation to the same address, then this erratum might
373 cause data corruption.
375 The workaround promotes data cache clean instructions to
376 data cache clean-and-invalidate.
377 Please note that this does not necessarily enable the workaround,
378 as it depends on the alternative framework, which will only patch
379 the kernel if an affected CPU is detected.
383 config ARM64_ERRATUM_832075
384 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
387 This option adds an alternative code sequence to work around ARM
388 erratum 832075 on Cortex-A57 parts up to r1p2.
390 Affected Cortex-A57 parts might deadlock when exclusive load/store
391 instructions to Write-Back memory are mixed with Device loads.
393 The workaround is to promote device loads to use Load-Acquire
395 Please note that this does not necessarily enable the workaround,
396 as it depends on the alternative framework, which will only patch
397 the kernel if an affected CPU is detected.
401 config ARM64_ERRATUM_834220
402 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
406 This option adds an alternative code sequence to work around ARM
407 erratum 834220 on Cortex-A57 parts up to r1p2.
409 Affected Cortex-A57 parts might report a Stage 2 translation
410 fault as the result of a Stage 1 fault for load crossing a
411 page boundary when there is a permission or device memory
412 alignment fault at Stage 1 and a translation fault at Stage 2.
414 The workaround is to verify that the Stage 1 translation
415 doesn't generate a fault before handling the Stage 2 fault.
416 Please note that this does not necessarily enable the workaround,
417 as it depends on the alternative framework, which will only patch
418 the kernel if an affected CPU is detected.
422 config ARM64_ERRATUM_845719
423 bool "Cortex-A53: 845719: a load might read incorrect data"
427 This option adds an alternative code sequence to work around ARM
428 erratum 845719 on Cortex-A53 parts up to r0p4.
430 When running a compat (AArch32) userspace on an affected Cortex-A53
431 part, a load at EL0 from a virtual address that matches the bottom 32
432 bits of the virtual address used by a recent load at (AArch64) EL1
433 might return incorrect data.
435 The workaround is to write the contextidr_el1 register on exception
436 return to a 32-bit task.
437 Please note that this does not necessarily enable the workaround,
438 as it depends on the alternative framework, which will only patch
439 the kernel if an affected CPU is detected.
443 config ARM64_ERRATUM_843419
444 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
446 select ARM64_MODULE_PLTS if MODULES
448 This option links the kernel with '--fix-cortex-a53-843419' and
449 enables PLT support to replace certain ADRP instructions, which can
450 cause subsequent memory accesses to use an incorrect address on
451 Cortex-A53 parts up to r0p4.
455 config ARM64_ERRATUM_1024718
456 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
459 This option adds work around for Arm Cortex-A55 Erratum 1024718.
461 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
462 update of the hardware dirty bit when the DBM/AP bits are updated
463 without a break-before-make. The work around is to disable the usage
464 of hardware DBM locally on the affected cores. CPUs not affected by
465 erratum will continue to use the feature.
469 config CAVIUM_ERRATUM_22375
470 bool "Cavium erratum 22375, 24313"
473 Enable workaround for erratum 22375, 24313.
475 This implements two gicv3-its errata workarounds for ThunderX. Both
476 with small impact affecting only ITS table allocation.
478 erratum 22375: only alloc 8MB table size
479 erratum 24313: ignore memory access type
481 The fixes are in ITS initialization and basically ignore memory access
482 type and table size provided by the TYPER and BASER registers.
486 config CAVIUM_ERRATUM_23144
487 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
491 ITS SYNC command hang for cross node io and collections/cpu mapping.
495 config CAVIUM_ERRATUM_23154
496 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
499 The gicv3 of ThunderX requires a modified version for
500 reading the IAR status to ensure data synchronization
501 (access to icc_iar1_el1 is not sync'ed before and after).
505 config CAVIUM_ERRATUM_27456
506 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
509 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
510 instructions may cause the icache to become corrupted if it
511 contains data for a non-current ASID. The fix is to
512 invalidate the icache when changing the mm context.
516 config CAVIUM_ERRATUM_30115
517 bool "Cavium erratum 30115: Guest may disable interrupts in host"
520 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
521 1.2, and T83 Pass 1.0, KVM guest execution may disable
522 interrupts in host. Trapping both GICv3 group-0 and group-1
523 accesses sidesteps the issue.
527 config QCOM_FALKOR_ERRATUM_1003
528 bool "Falkor E1003: Incorrect translation due to ASID change"
531 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
532 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
533 in TTBR1_EL1, this situation only occurs in the entry trampoline and
534 then only for entries in the walk cache, since the leaf translation
535 is unchanged. Work around the erratum by invalidating the walk cache
536 entries for the trampoline before entering the kernel proper.
538 config QCOM_FALKOR_ERRATUM_1009
539 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
542 On Falkor v1, the CPU may prematurely complete a DSB following a
543 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
544 one more time to fix the issue.
548 config QCOM_QDF2400_ERRATUM_0065
549 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
552 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
553 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
554 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
558 config SOCIONEXT_SYNQUACER_PREITS
559 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
562 Socionext Synquacer SoCs implement a separate h/w block to generate
563 MSI doorbell writes with non-zero values for the device ID.
567 config HISILICON_ERRATUM_161600802
568 bool "Hip07 161600802: Erroneous redistributor VLPI base"
571 The HiSilicon Hip07 SoC usees the wrong redistributor base
572 when issued ITS commands such as VMOVP and VMAPP, and requires
573 a 128kB offset to be applied to the target address in this commands.
577 config QCOM_FALKOR_ERRATUM_E1041
578 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
581 Falkor CPU may speculatively fetch instructions from an improper
582 memory location when MMU translation is changed from SCTLR_ELn[M]=1
583 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
592 default ARM64_4K_PAGES
594 Page size (translation granule) configuration.
596 config ARM64_4K_PAGES
599 This feature enables 4KB pages support.
601 config ARM64_16K_PAGES
604 The system will use 16KB pages support. AArch32 emulation
605 requires applications compiled with 16K (or a multiple of 16K)
608 config ARM64_64K_PAGES
611 This feature enables 64KB pages support (4KB by default)
612 allowing only two levels of page tables and faster TLB
613 look-up. AArch32 emulation requires applications compiled
614 with 64K aligned segments.
619 prompt "Virtual address space size"
620 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
621 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
622 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
624 Allows choosing one of multiple possible virtual address
625 space sizes. The level of translation table is determined by
626 a combination of page size and virtual address space size.
628 config ARM64_VA_BITS_36
629 bool "36-bit" if EXPERT
630 depends on ARM64_16K_PAGES
632 config ARM64_VA_BITS_39
634 depends on ARM64_4K_PAGES
636 config ARM64_VA_BITS_42
638 depends on ARM64_64K_PAGES
640 config ARM64_VA_BITS_47
642 depends on ARM64_16K_PAGES
644 config ARM64_VA_BITS_48
651 default 36 if ARM64_VA_BITS_36
652 default 39 if ARM64_VA_BITS_39
653 default 42 if ARM64_VA_BITS_42
654 default 47 if ARM64_VA_BITS_47
655 default 48 if ARM64_VA_BITS_48
658 prompt "Physical address space size"
659 default ARM64_PA_BITS_48
661 Choose the maximum physical address range that the kernel will
664 config ARM64_PA_BITS_48
667 config ARM64_PA_BITS_52
668 bool "52-bit (ARMv8.2)"
669 depends on ARM64_64K_PAGES
670 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
672 Enable support for a 52-bit physical address space, introduced as
673 part of the ARMv8.2-LPA extension.
675 With this enabled, the kernel will also continue to work on CPUs that
676 do not support ARMv8.2-LPA, but with some added memory overhead (and
677 minor performance overhead).
683 default 48 if ARM64_PA_BITS_48
684 default 52 if ARM64_PA_BITS_52
686 config CPU_BIG_ENDIAN
687 bool "Build big-endian kernel"
689 Say Y if you plan on running a kernel in big-endian mode.
692 bool "Multi-core scheduler support"
694 Multi-core scheduler support improves the CPU scheduler's decision
695 making when dealing with multi-core CPU chips at a cost of slightly
696 increased overhead in some places. If unsure say N here.
699 bool "SMT scheduler support"
701 Improves the CPU scheduler's decision making when dealing with
702 MultiThreading at a cost of slightly increased overhead in some
703 places. If unsure say N here.
706 int "Maximum number of CPUs (2-4096)"
708 # These have to remain sorted largest to smallest
712 bool "Support for hot-pluggable CPUs"
713 select GENERIC_IRQ_MIGRATION
715 Say Y here to experiment with turning CPUs off and on. CPUs
716 can be controlled through /sys/devices/system/cpu.
718 # Common NUMA Features
720 bool "Numa Memory Allocation and Scheduler Support"
721 select ACPI_NUMA if ACPI
724 Enable NUMA (Non Uniform Memory Access) support.
726 The kernel will try to allocate memory used by a CPU on the
727 local memory of the CPU and add some more
728 NUMA awareness to the kernel.
731 int "Maximum NUMA Nodes (as a power of 2)"
734 depends on NEED_MULTIPLE_NODES
736 Specify the maximum number of NUMA Nodes available on the target
737 system. Increases memory reserved to accommodate various tables.
739 config USE_PERCPU_NUMA_NODE_ID
743 config HAVE_SETUP_PER_CPU_AREA
747 config NEED_PER_CPU_EMBED_FIRST_CHUNK
755 source kernel/Kconfig.preempt
756 source kernel/Kconfig.hz
758 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
761 config ARCH_HAS_HOLES_MEMORYMODEL
762 def_bool y if SPARSEMEM
764 config ARCH_SPARSEMEM_ENABLE
766 select SPARSEMEM_VMEMMAP_ENABLE
768 config ARCH_SPARSEMEM_DEFAULT
769 def_bool ARCH_SPARSEMEM_ENABLE
771 config ARCH_SELECT_MEMORY_MODEL
772 def_bool ARCH_SPARSEMEM_ENABLE
774 config HAVE_ARCH_PFN_VALID
775 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
777 config HW_PERF_EVENTS
781 config SYS_SUPPORTS_HUGETLBFS
784 config ARCH_WANT_HUGE_PMD_SHARE
785 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
787 config ARCH_HAS_CACHE_LINE_SIZE
791 bool "Enable seccomp to safely compute untrusted bytecode"
793 This kernel feature is useful for number crunching applications
794 that may need to compute untrusted bytecode during their
795 execution. By using pipes or other transports made available to
796 the process as file descriptors supporting the read/write
797 syscalls, it's possible to isolate those applications in
798 their own address space using seccomp. Once seccomp is
799 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
800 and the task is only allowed to execute a few safe syscalls
801 defined by each seccomp mode.
804 bool "Enable paravirtualization code"
806 This changes the kernel so it can modify itself when it is run
807 under a hypervisor, potentially improving performance significantly
808 over full virtualization.
810 config PARAVIRT_TIME_ACCOUNTING
811 bool "Paravirtual steal time accounting"
815 Select this option to enable fine granularity task steal time
816 accounting. Time spent executing other tasks in parallel with
817 the current vCPU is discounted from the vCPU power. To account for
818 that, there can be a small performance impact.
820 If in doubt, say N here.
823 depends on PM_SLEEP_SMP
825 bool "kexec system call"
827 kexec is a system call that implements the ability to shutdown your
828 current kernel, and to start another kernel. It is like a reboot
829 but it is independent of the system firmware. And like a reboot
830 you can start any kernel with it, not just Linux.
833 bool "Build kdump crash kernel"
835 Generate crash dump after being started by kexec. This should
836 be normally only set in special crash dump kernels which are
837 loaded in the main kernel with kexec-tools into a specially
838 reserved region and then later executed after a crash by
841 For more details see Documentation/kdump/kdump.txt
848 bool "Xen guest support on ARM64"
849 depends on ARM64 && OF
853 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
855 config FORCE_MAX_ZONEORDER
857 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
858 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
861 The kernel memory allocator divides physically contiguous memory
862 blocks into "zones", where each zone is a power of two number of
863 pages. This option selects the largest power of two that the kernel
864 keeps in the memory allocator. If you need to allocate very large
865 blocks of physically contiguous memory, then you may need to
868 This config option is actually maximum order plus one. For example,
869 a value of 11 means that the largest free memory block is 2^10 pages.
871 We make sure that we can allocate upto a HugePage size for each configuration.
873 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
875 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
876 4M allocations matching the default size used by generic code.
878 config UNMAP_KERNEL_AT_EL0
879 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
882 Speculation attacks against some high-performance processors can
883 be used to bypass MMU permission checks and leak kernel data to
884 userspace. This can be defended against by unmapping the kernel
885 when running in userspace, mapping it back in on exception entry
886 via a trampoline page in the vector table.
890 config HARDEN_BRANCH_PREDICTOR
891 bool "Harden the branch predictor against aliasing attacks" if EXPERT
894 Speculation attacks against some high-performance processors rely on
895 being able to manipulate the branch predictor for a victim context by
896 executing aliasing branches in the attacker context. Such attacks
897 can be partially mitigated against by clearing internal branch
898 predictor state and limiting the prediction logic in some situations.
900 This config option will take CPU-specific actions to harden the
901 branch predictor against aliasing attacks and may rely on specific
902 instruction sequences or control bits being set by the system
907 config HARDEN_EL2_VECTORS
908 bool "Harden EL2 vector mapping against system register leak" if EXPERT
911 Speculation attacks against some high-performance processors can
912 be used to leak privileged information such as the vector base
913 register, resulting in a potential defeat of the EL2 layout
916 This config option will map the vectors to a fixed location,
917 independent of the EL2 code mapping, so that revealing VBAR_EL2
918 to an attacker does not give away any extra information. This
919 only gets enabled on affected CPUs.
924 bool "Speculative Store Bypass Disable" if EXPERT
927 This enables mitigation of the bypassing of previous stores
928 by speculative loads.
932 menuconfig ARMV8_DEPRECATED
933 bool "Emulate deprecated/obsolete ARMv8 instructions"
937 Legacy software support may require certain instructions
938 that have been deprecated or obsoleted in the architecture.
940 Enable this config to enable selective emulation of these
948 bool "Emulate SWP/SWPB instructions"
950 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
951 they are always undefined. Say Y here to enable software
952 emulation of these instructions for userspace using LDXR/STXR.
954 In some older versions of glibc [<=2.8] SWP is used during futex
955 trylock() operations with the assumption that the code will not
956 be preempted. This invalid assumption may be more likely to fail
957 with SWP emulation enabled, leading to deadlock of the user
960 NOTE: when accessing uncached shared regions, LDXR/STXR rely
961 on an external transaction monitoring block called a global
962 monitor to maintain update atomicity. If your system does not
963 implement a global monitor, this option can cause programs that
964 perform SWP operations to uncached memory to deadlock.
968 config CP15_BARRIER_EMULATION
969 bool "Emulate CP15 Barrier instructions"
971 The CP15 barrier instructions - CP15ISB, CP15DSB, and
972 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
973 strongly recommended to use the ISB, DSB, and DMB
974 instructions instead.
976 Say Y here to enable software emulation of these
977 instructions for AArch32 userspace code. When this option is
978 enabled, CP15 barrier usage is traced which can help
979 identify software that needs updating.
983 config SETEND_EMULATION
984 bool "Emulate SETEND instruction"
986 The SETEND instruction alters the data-endianness of the
987 AArch32 EL0, and is deprecated in ARMv8.
989 Say Y here to enable software emulation of the instruction
990 for AArch32 userspace code.
992 Note: All the cpus on the system must have mixed endian support at EL0
993 for this feature to be enabled. If a new CPU - which doesn't support mixed
994 endian - is hotplugged in after this feature has been enabled, there could
995 be unexpected results in the applications.
1000 config ARM64_SW_TTBR0_PAN
1001 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1003 Enabling this option prevents the kernel from accessing
1004 user-space memory directly by pointing TTBR0_EL1 to a reserved
1005 zeroed area and reserved ASID. The user access routines
1006 restore the valid TTBR0_EL1 temporarily.
1008 menu "ARMv8.1 architectural features"
1010 config ARM64_HW_AFDBM
1011 bool "Support for hardware updates of the Access and Dirty page flags"
1014 The ARMv8.1 architecture extensions introduce support for
1015 hardware updates of the access and dirty information in page
1016 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1017 capable processors, accesses to pages with PTE_AF cleared will
1018 set this bit instead of raising an access flag fault.
1019 Similarly, writes to read-only pages with the DBM bit set will
1020 clear the read-only bit (AP[2]) instead of raising a
1023 Kernels built with this configuration option enabled continue
1024 to work on pre-ARMv8.1 hardware and the performance impact is
1025 minimal. If unsure, say Y.
1028 bool "Enable support for Privileged Access Never (PAN)"
1031 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1032 prevents the kernel or hypervisor from accessing user-space (EL0)
1035 Choosing this option will cause any unprotected (not using
1036 copy_to_user et al) memory access to fail with a permission fault.
1038 The feature is detected at runtime, and will remain as a 'nop'
1039 instruction if the cpu does not implement the feature.
1041 config ARM64_LSE_ATOMICS
1042 bool "Atomic instructions"
1045 As part of the Large System Extensions, ARMv8.1 introduces new
1046 atomic instructions that are designed specifically to scale in
1049 Say Y here to make use of these instructions for the in-kernel
1050 atomic routines. This incurs a small overhead on CPUs that do
1051 not support these instructions and requires the kernel to be
1052 built with binutils >= 2.25 in order for the new instructions
1056 bool "Enable support for Virtualization Host Extensions (VHE)"
1059 Virtualization Host Extensions (VHE) allow the kernel to run
1060 directly at EL2 (instead of EL1) on processors that support
1061 it. This leads to better performance for KVM, as they reduce
1062 the cost of the world switch.
1064 Selecting this option allows the VHE feature to be detected
1065 at runtime, and does not affect processors that do not
1066 implement this feature.
1070 menu "ARMv8.2 architectural features"
1073 bool "Enable support for User Access Override (UAO)"
1076 User Access Override (UAO; part of the ARMv8.2 Extensions)
1077 causes the 'unprivileged' variant of the load/store instructions to
1078 be overridden to be privileged.
1080 This option changes get_user() and friends to use the 'unprivileged'
1081 variant of the load/store instructions. This ensures that user-space
1082 really did have access to the supplied memory. When addr_limit is
1083 set to kernel memory the UAO bit will be set, allowing privileged
1084 access to kernel memory.
1086 Choosing this option will cause copy_to_user() et al to use user-space
1089 The feature is detected at runtime, the kernel will use the
1090 regular load/store instructions if the cpu does not implement the
1094 bool "Enable support for persistent memory"
1095 select ARCH_HAS_PMEM_API
1096 select ARCH_HAS_UACCESS_FLUSHCACHE
1098 Say Y to enable support for the persistent memory API based on the
1099 ARMv8.2 DCPoP feature.
1101 The feature is detected at runtime, and the kernel will use DC CVAC
1102 operations if DC CVAP is not supported (following the behaviour of
1103 DC CVAP itself if the system does not define a point of persistence).
1105 config ARM64_RAS_EXTN
1106 bool "Enable support for RAS CPU Extensions"
1109 CPUs that support the Reliability, Availability and Serviceability
1110 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1111 errors, classify them and report them to software.
1113 On CPUs with these extensions system software can use additional
1114 barriers to determine if faults are pending and read the
1115 classification from a new set of registers.
1117 Selecting this feature will allow the kernel to use these barriers
1118 and access the new registers if the system supports the extension.
1119 Platform RAS features may additionally depend on firmware support.
1124 bool "ARM Scalable Vector Extension support"
1126 depends on !KVM || ARM64_VHE
1128 The Scalable Vector Extension (SVE) is an extension to the AArch64
1129 execution state which complements and extends the SIMD functionality
1130 of the base architecture to support much larger vectors and to enable
1131 additional vectorisation opportunities.
1133 To enable use of this extension on CPUs that implement it, say Y.
1135 Note that for architectural reasons, firmware _must_ implement SVE
1136 support when running on SVE capable hardware. The required support
1139 * version 1.5 and later of the ARM Trusted Firmware
1140 * the AArch64 boot wrapper since commit 5e1261e08abf
1141 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1143 For other firmware implementations, consult the firmware documentation
1146 If you need the kernel to boot on SVE-capable hardware with broken
1147 firmware, you may need to say N here until you get your firmware
1148 fixed. Otherwise, you may experience firmware panics or lockups when
1149 booting the kernel. If unsure and you are not observing these
1150 symptoms, you should assume that it is safe to say Y.
1152 CPUs that support SVE are architecturally required to support the
1153 Virtualization Host Extensions (VHE), so the kernel makes no
1154 provision for supporting SVE alongside KVM without VHE enabled.
1155 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1156 KVM in the same kernel image.
1158 config ARM64_MODULE_PLTS
1160 select HAVE_MOD_ARCH_SPECIFIC
1165 This builds the kernel as a Position Independent Executable (PIE),
1166 which retains all relocation metadata required to relocate the
1167 kernel binary at runtime to a different virtual address than the
1168 address it was linked at.
1169 Since AArch64 uses the RELA relocation format, this requires a
1170 relocation pass at runtime even if the kernel is loaded at the
1171 same address it was linked at.
1173 config RANDOMIZE_BASE
1174 bool "Randomize the address of the kernel image"
1175 select ARM64_MODULE_PLTS if MODULES
1178 Randomizes the virtual address at which the kernel image is
1179 loaded, as a security feature that deters exploit attempts
1180 relying on knowledge of the location of kernel internals.
1182 It is the bootloader's job to provide entropy, by passing a
1183 random u64 value in /chosen/kaslr-seed at kernel entry.
1185 When booting via the UEFI stub, it will invoke the firmware's
1186 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1187 to the kernel proper. In addition, it will randomise the physical
1188 location of the kernel Image as well.
1192 config RANDOMIZE_MODULE_REGION_FULL
1193 bool "Randomize the module region over a 4 GB range"
1194 depends on RANDOMIZE_BASE
1197 Randomizes the location of the module region inside a 4 GB window
1198 covering the core kernel. This way, it is less likely for modules
1199 to leak information about the location of core kernel data structures
1200 but it does imply that function calls between modules and the core
1201 kernel will need to be resolved via veneers in the module PLT.
1203 When this option is not set, the module region will be randomized over
1204 a limited range that contains the [_stext, _etext] interval of the
1205 core kernel, so branch relocations are always in range.
1211 config ARM64_ACPI_PARKING_PROTOCOL
1212 bool "Enable support for the ARM64 ACPI parking protocol"
1215 Enable support for the ARM64 ACPI parking protocol. If disabled
1216 the kernel will not allow booting through the ARM64 ACPI parking
1217 protocol even if the corresponding data is present in the ACPI
1221 string "Default kernel command string"
1224 Provide a set of default command-line options at build time by
1225 entering them here. As a minimum, you should specify the the
1226 root device (e.g. root=/dev/nfs).
1228 config CMDLINE_FORCE
1229 bool "Always use the default kernel command string"
1231 Always use the default kernel command string, even if the boot
1232 loader passes other arguments to the kernel.
1233 This is useful if you cannot or don't want to change the
1234 command-line options your boot loader passes to the kernel.
1240 bool "UEFI runtime support"
1241 depends on OF && !CPU_BIG_ENDIAN
1242 depends on KERNEL_MODE_NEON
1245 select EFI_PARAMS_FROM_FDT
1246 select EFI_RUNTIME_WRAPPERS
1251 This option provides support for runtime services provided
1252 by UEFI firmware (such as non-volatile variables, realtime
1253 clock, and platform reset). A UEFI stub is also provided to
1254 allow the kernel to be booted as an EFI application. This
1255 is only useful on systems that have UEFI firmware.
1258 bool "Enable support for SMBIOS (DMI) tables"
1262 This enables SMBIOS/DMI feature for systems.
1264 This option is only useful on systems that have UEFI firmware.
1265 However, even with this option, the resultant kernel should
1266 continue to boot on existing non-UEFI platforms.
1271 bool "Kernel support for 32-bit EL0"
1272 depends on ARM64_4K_PAGES || EXPERT
1273 select COMPAT_BINFMT_ELF if BINFMT_ELF
1275 select OLD_SIGSUSPEND3
1276 select COMPAT_OLD_SIGACTION
1278 This option enables support for a 32-bit EL0 running under a 64-bit
1279 kernel at EL1. AArch32-specific components such as system calls,
1280 the user helper functions, VFP support and the ptrace interface are
1281 handled appropriately by the kernel.
1283 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1284 that you will only be able to execute AArch32 binaries that were compiled
1285 with page size aligned segments.
1287 If you want to execute 32-bit userspace applications, say Y.
1289 config SYSVIPC_COMPAT
1291 depends on COMPAT && SYSVIPC
1293 menu "Power management options"
1295 source "kernel/power/Kconfig"
1297 config ARCH_HIBERNATION_POSSIBLE
1301 config ARCH_HIBERNATION_HEADER
1303 depends on HIBERNATION
1305 config ARCH_SUSPEND_POSSIBLE
1310 menu "CPU Power Management"
1312 source "drivers/cpuidle/Kconfig"
1314 source "drivers/cpufreq/Kconfig"
1318 source "drivers/firmware/Kconfig"
1320 source "drivers/acpi/Kconfig"
1322 source "arch/arm64/kvm/Kconfig"
1325 source "arch/arm64/crypto/Kconfig"