1 /* linux/arch/arm/plat-s3c/pm.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2004-2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C common power management (suspend to ram) support.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/suspend.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial_s3c.h>
24 #include <asm/cacheflush.h>
25 #include <asm/suspend.h>
27 #ifdef CONFIG_SAMSUNG_ATAGS
28 #include <mach/hardware.h>
30 #ifndef CONFIG_ARCH_EXYNOS
31 #include <mach/regs-clock.h>
32 #include <mach/regs-irq.h>
34 #include <mach/irqs.h>
40 #include <mach/pm-core.h>
42 /* for external use */
44 unsigned long s3c_pm_flags;
48 * This code supports debug output to the low level UARTs for use on
49 * resume before the console layer is available.
52 #ifdef CONFIG_SAMSUNG_PM_DEBUG
53 extern void printascii(const char *);
55 void s3c_pm_dbg(const char *fmt, ...)
61 vsnprintf(buff, sizeof(buff), fmt, va);
67 static inline void s3c_pm_debug_init(void)
69 /* restart uart clocks so we can use them to output */
70 s3c_pm_debug_init_uart();
74 #define s3c_pm_debug_init() do { } while(0)
76 #endif /* CONFIG_SAMSUNG_PM_DEBUG */
78 /* Save the UART configurations if we are configured for debug. */
80 unsigned char pm_uart_udivslot;
82 #ifdef CONFIG_SAMSUNG_PM_DEBUG
84 static struct pm_uart_save uart_save;
86 static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
88 void __iomem *regs = S3C_VA_UARTx(uart);
90 save->ulcon = __raw_readl(regs + S3C2410_ULCON);
91 save->ucon = __raw_readl(regs + S3C2410_UCON);
92 save->ufcon = __raw_readl(regs + S3C2410_UFCON);
93 save->umcon = __raw_readl(regs + S3C2410_UMCON);
94 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
97 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
99 S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
100 uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
103 static void s3c_pm_save_uarts(void)
105 s3c_pm_save_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
108 static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
110 void __iomem *regs = S3C_VA_UARTx(uart);
112 s3c_pm_arch_update_uart(regs, save);
114 __raw_writel(save->ulcon, regs + S3C2410_ULCON);
115 __raw_writel(save->ucon, regs + S3C2410_UCON);
116 __raw_writel(save->ufcon, regs + S3C2410_UFCON);
117 __raw_writel(save->umcon, regs + S3C2410_UMCON);
118 __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
120 if (pm_uart_udivslot)
121 __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
124 static void s3c_pm_restore_uarts(void)
126 s3c_pm_restore_uart(CONFIG_DEBUG_S3C_UART, &uart_save);
129 static void s3c_pm_save_uarts(void) { }
130 static void s3c_pm_restore_uarts(void) { }
133 /* The IRQ ext-int code goes here, it is too small to currently bother
134 * with its own file. */
136 unsigned long s3c_irqwake_intmask = 0xffffffffL;
137 unsigned long s3c_irqwake_eintmask = 0xffffffffL;
139 int s3c_irqext_wake(struct irq_data *data, unsigned int state)
141 unsigned long bit = 1L << IRQ_EINT_BIT(data->irq);
143 if (!(s3c_irqwake_eintallow & bit))
146 printk(KERN_INFO "wake %s for irq %d\n",
147 state ? "enabled" : "disabled", data->irq);
150 s3c_irqwake_eintmask |= bit;
152 s3c_irqwake_eintmask &= ~bit;
157 /* helper functions to save and restore register state */
160 * s3c_pm_do_save() - save a set of registers for restoration on resume.
161 * @ptr: Pointer to an array of registers.
162 * @count: Size of the ptr array.
164 * Run through the list of registers given, saving their contents in the
165 * array for later restoration when we wakeup.
167 void s3c_pm_do_save(struct sleep_save *ptr, int count)
169 for (; count > 0; count--, ptr++) {
170 ptr->val = __raw_readl(ptr->reg);
171 S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
176 * s3c_pm_do_restore() - restore register values from the save list.
177 * @ptr: Pointer to an array of registers.
178 * @count: Size of the ptr array.
180 * Restore the register values saved from s3c_pm_do_save().
182 * Note, we do not use S3C_PMDBG() in here, as the system may not have
183 * restore the UARTs state yet
186 void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
188 for (; count > 0; count--, ptr++) {
189 printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
190 ptr->reg, ptr->val, __raw_readl(ptr->reg));
192 __raw_writel(ptr->val, ptr->reg);
197 * s3c_pm_do_restore_core() - early restore register values from save list.
199 * This is similar to s3c_pm_do_restore() except we try and minimise the
200 * side effects of the function in case registers that hardware might need
201 * to work has been restored.
203 * WARNING: Do not put any debug in here that may effect memory or use
204 * peripherals, as things may be changing!
207 void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
209 for (; count > 0; count--, ptr++)
210 __raw_writel(ptr->val, ptr->reg);
213 /* s3c2410_pm_show_resume_irqs
215 * print any IRQs asserted at resume time (ie, we woke from)
217 static void __maybe_unused s3c_pm_show_resume_irqs(int start,
225 for (i = 0; i <= 31; i++) {
226 if (which & (1L<<i)) {
227 S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
233 void (*pm_cpu_prep)(void);
234 int (*pm_cpu_sleep)(unsigned long);
236 #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
240 * central control for sleep/resume process
243 static int s3c_pm_enter(suspend_state_t state)
246 /* ensure the debug is initialised (if enabled) */
250 S3C_PMDBG("%s(%d)\n", __func__, state);
252 if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
253 printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
257 /* check if we have anything to wake-up with... bad things seem
258 * to happen if you suspend with no wakeup (system will often
259 * require a full power-cycle)
262 if (!of_have_populated_dt() &&
263 !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
264 !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
265 printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
266 printk(KERN_ERR "%s: Aborting sleep\n", __func__);
270 /* save all necessary core registers not covered by the drivers */
272 if (!of_have_populated_dt()) {
273 samsung_pm_save_gpios();
274 samsung_pm_saved_gpios();
280 /* set the irq configuration for wake */
282 s3c_pm_configure_extint();
284 S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
285 s3c_irqwake_intmask, s3c_irqwake_eintmask);
287 s3c_pm_arch_prepare_irqs();
289 /* call cpu specific preparation */
293 /* flush cache back to ram */
297 s3c_pm_check_store();
299 /* send the cpu to sleep... */
301 s3c_pm_arch_stop_clocks();
303 /* this will also act as our return point from when
304 * we resume as it saves its own register state and restores it
305 * during the resume. */
307 ret = cpu_suspend(0, pm_cpu_sleep);
311 /* restore the system state */
313 s3c_pm_restore_core();
314 s3c_pm_restore_uarts();
316 if (!of_have_populated_dt()) {
317 samsung_pm_restore_gpios();
318 s3c_pm_restored_gpios();
323 /* check what irq (if any) restored the system */
325 s3c_pm_arch_show_resume_irqs();
327 S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
329 /* LEDs should now be 1110 */
330 s3c_pm_debug_smdkled(1 << 1, 0);
332 s3c_pm_check_restore();
334 /* ok, let's return from sleep */
336 S3C_PMDBG("S3C PM Resume (post-restore)\n");
340 static int s3c_pm_prepare(void)
342 /* prepare check area if configured */
344 s3c_pm_check_prepare();
348 static void s3c_pm_finish(void)
350 s3c_pm_check_cleanup();
353 static const struct platform_suspend_ops s3c_pm_ops = {
354 .enter = s3c_pm_enter,
355 .prepare = s3c_pm_prepare,
356 .finish = s3c_pm_finish,
357 .valid = suspend_valid_only_mem,
362 * Attach the power management functions. This should be called
363 * from the board specific initialisation if the board supports
367 int __init s3c_pm_init(void)
369 printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
371 suspend_set_ops(&s3c_pm_ops);