2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
28 #include <plat/mcbsp.h>
30 #include "../mach-omap2/cm-regbits-34xx.h"
32 struct omap_mcbsp **mcbsp_ptr;
33 int omap_mcbsp_count, omap_mcbsp_cache_size;
35 void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
37 if (cpu_class_is_omap1()) {
38 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
39 __raw_writew((u16)val, mcbsp->io_base + reg);
40 } else if (cpu_is_omap2420()) {
41 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
42 __raw_writew((u16)val, mcbsp->io_base + reg);
44 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
45 __raw_writel(val, mcbsp->io_base + reg);
49 int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
51 if (cpu_class_is_omap1()) {
52 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
53 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
54 } else if (cpu_is_omap2420()) {
55 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
56 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
58 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
59 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
63 #ifdef CONFIG_ARCH_OMAP3
64 void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
66 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
69 int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
71 return __raw_readl(mcbsp->st_data->io_base_st + reg);
75 #define MCBSP_READ(mcbsp, reg) \
76 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
77 #define MCBSP_WRITE(mcbsp, reg, val) \
78 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
79 #define MCBSP_READ_CACHE(mcbsp, reg) \
80 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
82 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
83 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
85 #define MCBSP_ST_READ(mcbsp, reg) \
86 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
87 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
88 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
90 static void omap_mcbsp_dump_reg(u8 id)
92 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
94 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
95 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
96 MCBSP_READ(mcbsp, DRR2));
97 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
98 MCBSP_READ(mcbsp, DRR1));
99 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
100 MCBSP_READ(mcbsp, DXR2));
101 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
102 MCBSP_READ(mcbsp, DXR1));
103 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
104 MCBSP_READ(mcbsp, SPCR2));
105 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
106 MCBSP_READ(mcbsp, SPCR1));
107 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
108 MCBSP_READ(mcbsp, RCR2));
109 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
110 MCBSP_READ(mcbsp, RCR1));
111 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
112 MCBSP_READ(mcbsp, XCR2));
113 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
114 MCBSP_READ(mcbsp, XCR1));
115 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
116 MCBSP_READ(mcbsp, SRGR2));
117 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
118 MCBSP_READ(mcbsp, SRGR1));
119 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
120 MCBSP_READ(mcbsp, PCR0));
121 dev_dbg(mcbsp->dev, "***********************\n");
124 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
126 struct omap_mcbsp *mcbsp_tx = dev_id;
129 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
130 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
132 if (irqst_spcr2 & XSYNC_ERR) {
133 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
135 /* Writing zero to XSYNC_ERR clears the IRQ */
136 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
138 complete(&mcbsp_tx->tx_irq_completion);
144 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
146 struct omap_mcbsp *mcbsp_rx = dev_id;
149 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
150 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
152 if (irqst_spcr1 & RSYNC_ERR) {
153 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
155 /* Writing zero to RSYNC_ERR clears the IRQ */
156 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
158 complete(&mcbsp_rx->tx_irq_completion);
164 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
166 struct omap_mcbsp *mcbsp_dma_tx = data;
168 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
169 MCBSP_READ(mcbsp_dma_tx, SPCR2));
171 /* We can free the channels */
172 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
173 mcbsp_dma_tx->dma_tx_lch = -1;
175 complete(&mcbsp_dma_tx->tx_dma_completion);
178 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
180 struct omap_mcbsp *mcbsp_dma_rx = data;
182 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
183 MCBSP_READ(mcbsp_dma_rx, SPCR2));
185 /* We can free the channels */
186 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
187 mcbsp_dma_rx->dma_rx_lch = -1;
189 complete(&mcbsp_dma_rx->rx_dma_completion);
193 * omap_mcbsp_config simply write a config to the
195 * You either call this function or set the McBSP registers
196 * by yourself before calling omap_mcbsp_start().
198 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
200 struct omap_mcbsp *mcbsp;
202 if (!omap_mcbsp_check_valid_id(id)) {
203 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
206 mcbsp = id_to_mcbsp_ptr(id);
208 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
209 mcbsp->id, mcbsp->phys_base);
211 /* We write the given config */
212 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
213 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
214 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
215 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
216 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
217 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
218 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
219 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
220 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
221 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
222 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
223 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
224 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
225 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
228 EXPORT_SYMBOL(omap_mcbsp_config);
230 #ifdef CONFIG_ARCH_OMAP3
231 static void omap_st_on(struct omap_mcbsp *mcbsp)
236 * Sidetone uses McBSP ICLK - which must not idle when sidetones
237 * are enabled or sidetones start sounding ugly.
239 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
240 w &= ~(1 << (mcbsp->id - 2));
241 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
243 /* Enable McBSP Sidetone */
244 w = MCBSP_READ(mcbsp, SSELCR);
245 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
247 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
248 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
250 /* Enable Sidetone from Sidetone Core */
251 w = MCBSP_ST_READ(mcbsp, SSELCR);
252 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
255 static void omap_st_off(struct omap_mcbsp *mcbsp)
259 w = MCBSP_ST_READ(mcbsp, SSELCR);
260 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
262 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
263 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
265 w = MCBSP_READ(mcbsp, SSELCR);
266 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
268 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
269 w |= 1 << (mcbsp->id - 2);
270 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
273 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
277 val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
278 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
280 val = MCBSP_ST_READ(mcbsp, SSELCR);
282 if (val & ST_COEFFWREN)
283 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
285 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
287 for (i = 0; i < 128; i++)
288 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
292 val = MCBSP_ST_READ(mcbsp, SSELCR);
293 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
294 val = MCBSP_ST_READ(mcbsp, SSELCR);
296 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
299 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
302 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
305 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
307 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
308 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
310 w = MCBSP_ST_READ(mcbsp, SSELCR);
312 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
313 ST_CH1GAIN(st_data->ch1gain));
316 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
318 struct omap_mcbsp *mcbsp;
319 struct omap_mcbsp_st_data *st_data;
322 if (!omap_mcbsp_check_valid_id(id)) {
323 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
327 mcbsp = id_to_mcbsp_ptr(id);
328 st_data = mcbsp->st_data;
333 spin_lock_irq(&mcbsp->lock);
335 st_data->ch0gain = chgain;
336 else if (channel == 1)
337 st_data->ch1gain = chgain;
341 if (st_data->enabled)
342 omap_st_chgain(mcbsp);
343 spin_unlock_irq(&mcbsp->lock);
347 EXPORT_SYMBOL(omap_st_set_chgain);
349 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
351 struct omap_mcbsp *mcbsp;
352 struct omap_mcbsp_st_data *st_data;
355 if (!omap_mcbsp_check_valid_id(id)) {
356 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
360 mcbsp = id_to_mcbsp_ptr(id);
361 st_data = mcbsp->st_data;
366 spin_lock_irq(&mcbsp->lock);
368 *chgain = st_data->ch0gain;
369 else if (channel == 1)
370 *chgain = st_data->ch1gain;
373 spin_unlock_irq(&mcbsp->lock);
377 EXPORT_SYMBOL(omap_st_get_chgain);
379 static int omap_st_start(struct omap_mcbsp *mcbsp)
381 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
383 if (st_data && st_data->enabled && !st_data->running) {
384 omap_st_fir_write(mcbsp, st_data->taps);
385 omap_st_chgain(mcbsp);
389 st_data->running = 1;
396 int omap_st_enable(unsigned int id)
398 struct omap_mcbsp *mcbsp;
399 struct omap_mcbsp_st_data *st_data;
401 if (!omap_mcbsp_check_valid_id(id)) {
402 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
406 mcbsp = id_to_mcbsp_ptr(id);
407 st_data = mcbsp->st_data;
412 spin_lock_irq(&mcbsp->lock);
413 st_data->enabled = 1;
414 omap_st_start(mcbsp);
415 spin_unlock_irq(&mcbsp->lock);
419 EXPORT_SYMBOL(omap_st_enable);
421 static int omap_st_stop(struct omap_mcbsp *mcbsp)
423 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
425 if (st_data && st_data->running) {
428 st_data->running = 0;
435 int omap_st_disable(unsigned int id)
437 struct omap_mcbsp *mcbsp;
438 struct omap_mcbsp_st_data *st_data;
441 if (!omap_mcbsp_check_valid_id(id)) {
442 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
446 mcbsp = id_to_mcbsp_ptr(id);
447 st_data = mcbsp->st_data;
452 spin_lock_irq(&mcbsp->lock);
454 st_data->enabled = 0;
455 spin_unlock_irq(&mcbsp->lock);
459 EXPORT_SYMBOL(omap_st_disable);
461 int omap_st_is_enabled(unsigned int id)
463 struct omap_mcbsp *mcbsp;
464 struct omap_mcbsp_st_data *st_data;
466 if (!omap_mcbsp_check_valid_id(id)) {
467 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
471 mcbsp = id_to_mcbsp_ptr(id);
472 st_data = mcbsp->st_data;
478 return st_data->enabled;
480 EXPORT_SYMBOL(omap_st_is_enabled);
483 * omap_mcbsp_set_tx_threshold configures how to deal
484 * with transmit threshold. the threshold value and handler can be
487 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
489 struct omap_mcbsp *mcbsp;
491 if (!cpu_is_omap34xx())
494 if (!omap_mcbsp_check_valid_id(id)) {
495 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
498 mcbsp = id_to_mcbsp_ptr(id);
500 MCBSP_WRITE(mcbsp, THRSH2, threshold);
502 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
505 * omap_mcbsp_set_rx_threshold configures how to deal
506 * with receive threshold. the threshold value and handler can be
509 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
511 struct omap_mcbsp *mcbsp;
513 if (!cpu_is_omap34xx())
516 if (!omap_mcbsp_check_valid_id(id)) {
517 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
520 mcbsp = id_to_mcbsp_ptr(id);
522 MCBSP_WRITE(mcbsp, THRSH1, threshold);
524 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
527 * omap_mcbsp_get_max_tx_thres just return the current configured
528 * maximum threshold for transmission
530 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
532 struct omap_mcbsp *mcbsp;
534 if (!omap_mcbsp_check_valid_id(id)) {
535 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
538 mcbsp = id_to_mcbsp_ptr(id);
540 return mcbsp->max_tx_thres;
542 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
545 * omap_mcbsp_get_max_rx_thres just return the current configured
546 * maximum threshold for reception
548 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
550 struct omap_mcbsp *mcbsp;
552 if (!omap_mcbsp_check_valid_id(id)) {
553 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
556 mcbsp = id_to_mcbsp_ptr(id);
558 return mcbsp->max_rx_thres;
560 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
563 * omap_mcbsp_get_dma_op_mode just return the current configured
564 * operating mode for the mcbsp channel
566 int omap_mcbsp_get_dma_op_mode(unsigned int id)
568 struct omap_mcbsp *mcbsp;
571 if (!omap_mcbsp_check_valid_id(id)) {
572 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
575 mcbsp = id_to_mcbsp_ptr(id);
577 dma_op_mode = mcbsp->dma_op_mode;
581 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
583 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
586 * Enable wakup behavior, smart idle and all wakeups
587 * REVISIT: some wakeups may be unnecessary
589 if (cpu_is_omap34xx()) {
592 syscon = MCBSP_READ(mcbsp, SYSCON);
593 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
595 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
596 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
597 CLOCKACTIVITY(0x02));
598 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
600 syscon |= SIDLEMODE(0x01);
603 MCBSP_WRITE(mcbsp, SYSCON, syscon);
607 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
610 * Disable wakup behavior, smart idle and all wakeups
612 if (cpu_is_omap34xx()) {
615 syscon = MCBSP_READ(mcbsp, SYSCON);
616 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
618 * HW bug workaround - If no_idle mode is taken, we need to
619 * go to smart_idle before going to always_idle, or the
620 * device will not hit retention anymore.
622 syscon |= SIDLEMODE(0x02);
623 MCBSP_WRITE(mcbsp, SYSCON, syscon);
625 syscon &= ~(SIDLEMODE(0x03));
626 MCBSP_WRITE(mcbsp, SYSCON, syscon);
628 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
632 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
633 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
634 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
635 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
639 * We can choose between IRQ based or polled IO.
640 * This needs to be called before omap_mcbsp_request().
642 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
644 struct omap_mcbsp *mcbsp;
646 if (!omap_mcbsp_check_valid_id(id)) {
647 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
650 mcbsp = id_to_mcbsp_ptr(id);
652 spin_lock(&mcbsp->lock);
655 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
657 spin_unlock(&mcbsp->lock);
661 mcbsp->io_type = io_type;
663 spin_unlock(&mcbsp->lock);
667 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
669 int omap_mcbsp_request(unsigned int id)
671 struct omap_mcbsp *mcbsp;
675 if (!omap_mcbsp_check_valid_id(id)) {
676 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
679 mcbsp = id_to_mcbsp_ptr(id);
681 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
686 spin_lock(&mcbsp->lock);
688 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
695 mcbsp->reg_cache = reg_cache;
696 spin_unlock(&mcbsp->lock);
698 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
699 mcbsp->pdata->ops->request(id);
701 clk_enable(mcbsp->iclk);
702 clk_enable(mcbsp->fclk);
704 /* Do procedure specific to omap34xx arch, if applicable */
705 omap34xx_mcbsp_request(mcbsp);
708 * Make sure that transmitter, receiver and sample-rate generator are
709 * not running before activating IRQs.
711 MCBSP_WRITE(mcbsp, SPCR1, 0);
712 MCBSP_WRITE(mcbsp, SPCR2, 0);
714 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
715 /* We need to get IRQs here */
716 init_completion(&mcbsp->tx_irq_completion);
717 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
718 0, "McBSP", (void *)mcbsp);
720 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
721 "for McBSP%d\n", mcbsp->tx_irq,
723 goto err_clk_disable;
726 init_completion(&mcbsp->rx_irq_completion);
727 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
728 0, "McBSP", (void *)mcbsp);
730 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
731 "for McBSP%d\n", mcbsp->rx_irq,
739 free_irq(mcbsp->tx_irq, (void *)mcbsp);
741 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
742 mcbsp->pdata->ops->free(id);
744 /* Do procedure specific to omap34xx arch, if applicable */
745 omap34xx_mcbsp_free(mcbsp);
747 clk_disable(mcbsp->fclk);
748 clk_disable(mcbsp->iclk);
750 spin_lock(&mcbsp->lock);
752 mcbsp->reg_cache = NULL;
754 spin_unlock(&mcbsp->lock);
759 EXPORT_SYMBOL(omap_mcbsp_request);
761 void omap_mcbsp_free(unsigned int id)
763 struct omap_mcbsp *mcbsp;
766 if (!omap_mcbsp_check_valid_id(id)) {
767 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
770 mcbsp = id_to_mcbsp_ptr(id);
772 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
773 mcbsp->pdata->ops->free(id);
775 /* Do procedure specific to omap34xx arch, if applicable */
776 omap34xx_mcbsp_free(mcbsp);
778 clk_disable(mcbsp->fclk);
779 clk_disable(mcbsp->iclk);
781 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
783 free_irq(mcbsp->rx_irq, (void *)mcbsp);
784 free_irq(mcbsp->tx_irq, (void *)mcbsp);
787 reg_cache = mcbsp->reg_cache;
789 spin_lock(&mcbsp->lock);
791 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
794 mcbsp->reg_cache = NULL;
795 spin_unlock(&mcbsp->lock);
800 EXPORT_SYMBOL(omap_mcbsp_free);
803 * Here we start the McBSP, by enabling transmitter, receiver or both.
804 * If no transmitter or receiver is active prior calling, then sample-rate
805 * generator and frame sync are started.
807 void omap_mcbsp_start(unsigned int id, int tx, int rx)
809 struct omap_mcbsp *mcbsp;
813 if (!omap_mcbsp_check_valid_id(id)) {
814 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
817 mcbsp = id_to_mcbsp_ptr(id);
819 if (cpu_is_omap34xx())
820 omap_st_start(mcbsp);
822 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
823 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
825 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
826 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
829 /* Start the sample generator */
830 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
831 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
834 /* Enable transmitter and receiver */
836 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
837 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
840 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
841 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
844 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
845 * REVISIT: 100us may give enough time for two CLKSRG, however
846 * due to some unknown PM related, clock gating etc. reason it
852 /* Start frame sync */
853 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
854 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
857 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
858 /* Release the transmitter and receiver */
859 w = MCBSP_READ_CACHE(mcbsp, XCCR);
860 w &= ~(tx ? XDISABLE : 0);
861 MCBSP_WRITE(mcbsp, XCCR, w);
862 w = MCBSP_READ_CACHE(mcbsp, RCCR);
863 w &= ~(rx ? RDISABLE : 0);
864 MCBSP_WRITE(mcbsp, RCCR, w);
867 /* Dump McBSP Regs */
868 omap_mcbsp_dump_reg(id);
870 EXPORT_SYMBOL(omap_mcbsp_start);
872 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
874 struct omap_mcbsp *mcbsp;
878 if (!omap_mcbsp_check_valid_id(id)) {
879 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
883 mcbsp = id_to_mcbsp_ptr(id);
885 /* Reset transmitter */
887 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
888 w = MCBSP_READ_CACHE(mcbsp, XCCR);
889 w |= (tx ? XDISABLE : 0);
890 MCBSP_WRITE(mcbsp, XCCR, w);
892 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
893 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
897 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
898 w = MCBSP_READ_CACHE(mcbsp, RCCR);
899 w |= (rx ? RDISABLE : 0);
900 MCBSP_WRITE(mcbsp, RCCR, w);
902 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
903 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
905 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
906 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
909 /* Reset the sample rate generator */
910 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
911 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
914 if (cpu_is_omap34xx())
917 EXPORT_SYMBOL(omap_mcbsp_stop);
919 /* polled mcbsp i/o operations */
920 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
922 struct omap_mcbsp *mcbsp;
924 if (!omap_mcbsp_check_valid_id(id)) {
925 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
929 mcbsp = id_to_mcbsp_ptr(id);
931 MCBSP_WRITE(mcbsp, DXR1, buf);
932 /* if frame sync error - clear the error */
933 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
935 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
939 /* wait for transmit confirmation */
941 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
942 if (attemps++ > 1000) {
943 MCBSP_WRITE(mcbsp, SPCR2,
944 MCBSP_READ_CACHE(mcbsp, SPCR2) &
947 MCBSP_WRITE(mcbsp, SPCR2,
948 MCBSP_READ_CACHE(mcbsp, SPCR2) |
951 dev_err(mcbsp->dev, "Could not write to"
952 " McBSP%d Register\n", mcbsp->id);
960 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
962 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
964 struct omap_mcbsp *mcbsp;
966 if (!omap_mcbsp_check_valid_id(id)) {
967 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
970 mcbsp = id_to_mcbsp_ptr(id);
972 /* if frame sync error - clear the error */
973 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
975 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
979 /* wait for recieve confirmation */
981 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
982 if (attemps++ > 1000) {
983 MCBSP_WRITE(mcbsp, SPCR1,
984 MCBSP_READ_CACHE(mcbsp, SPCR1) &
987 MCBSP_WRITE(mcbsp, SPCR1,
988 MCBSP_READ_CACHE(mcbsp, SPCR1) |
991 dev_err(mcbsp->dev, "Could not read from"
992 " McBSP%d Register\n", mcbsp->id);
997 *buf = MCBSP_READ(mcbsp, DRR1);
1001 EXPORT_SYMBOL(omap_mcbsp_pollread);
1004 * IRQ based word transmission.
1006 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1008 struct omap_mcbsp *mcbsp;
1009 omap_mcbsp_word_length word_length;
1011 if (!omap_mcbsp_check_valid_id(id)) {
1012 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1016 mcbsp = id_to_mcbsp_ptr(id);
1017 word_length = mcbsp->tx_word_length;
1019 wait_for_completion(&mcbsp->tx_irq_completion);
1021 if (word_length > OMAP_MCBSP_WORD_16)
1022 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1023 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1025 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1027 u32 omap_mcbsp_recv_word(unsigned int id)
1029 struct omap_mcbsp *mcbsp;
1030 u16 word_lsb, word_msb = 0;
1031 omap_mcbsp_word_length word_length;
1033 if (!omap_mcbsp_check_valid_id(id)) {
1034 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1037 mcbsp = id_to_mcbsp_ptr(id);
1039 word_length = mcbsp->rx_word_length;
1041 wait_for_completion(&mcbsp->rx_irq_completion);
1043 if (word_length > OMAP_MCBSP_WORD_16)
1044 word_msb = MCBSP_READ(mcbsp, DRR2);
1045 word_lsb = MCBSP_READ(mcbsp, DRR1);
1047 return (word_lsb | (word_msb << 16));
1049 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1051 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1053 struct omap_mcbsp *mcbsp;
1054 omap_mcbsp_word_length tx_word_length;
1055 omap_mcbsp_word_length rx_word_length;
1056 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1058 if (!omap_mcbsp_check_valid_id(id)) {
1059 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1062 mcbsp = id_to_mcbsp_ptr(id);
1063 tx_word_length = mcbsp->tx_word_length;
1064 rx_word_length = mcbsp->rx_word_length;
1066 if (tx_word_length != rx_word_length)
1069 /* First we wait for the transmitter to be ready */
1070 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1071 while (!(spcr2 & XRDY)) {
1072 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1073 if (attempts++ > 1000) {
1074 /* We must reset the transmitter */
1075 MCBSP_WRITE(mcbsp, SPCR2,
1076 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1078 MCBSP_WRITE(mcbsp, SPCR2,
1079 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1081 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1082 "ready\n", mcbsp->id);
1087 /* Now we can push the data */
1088 if (tx_word_length > OMAP_MCBSP_WORD_16)
1089 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1090 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1092 /* We wait for the receiver to be ready */
1093 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1094 while (!(spcr1 & RRDY)) {
1095 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1096 if (attempts++ > 1000) {
1097 /* We must reset the receiver */
1098 MCBSP_WRITE(mcbsp, SPCR1,
1099 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1101 MCBSP_WRITE(mcbsp, SPCR1,
1102 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1104 dev_err(mcbsp->dev, "McBSP%d receiver not "
1105 "ready\n", mcbsp->id);
1110 /* Receiver is ready, let's read the dummy data */
1111 if (rx_word_length > OMAP_MCBSP_WORD_16)
1112 word_msb = MCBSP_READ(mcbsp, DRR2);
1113 word_lsb = MCBSP_READ(mcbsp, DRR1);
1117 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1119 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1121 struct omap_mcbsp *mcbsp;
1123 omap_mcbsp_word_length tx_word_length;
1124 omap_mcbsp_word_length rx_word_length;
1125 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1127 if (!omap_mcbsp_check_valid_id(id)) {
1128 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1132 mcbsp = id_to_mcbsp_ptr(id);
1134 tx_word_length = mcbsp->tx_word_length;
1135 rx_word_length = mcbsp->rx_word_length;
1137 if (tx_word_length != rx_word_length)
1140 /* First we wait for the transmitter to be ready */
1141 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1142 while (!(spcr2 & XRDY)) {
1143 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1144 if (attempts++ > 1000) {
1145 /* We must reset the transmitter */
1146 MCBSP_WRITE(mcbsp, SPCR2,
1147 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1149 MCBSP_WRITE(mcbsp, SPCR2,
1150 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1152 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1153 "ready\n", mcbsp->id);
1158 /* We first need to enable the bus clock */
1159 if (tx_word_length > OMAP_MCBSP_WORD_16)
1160 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1161 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1163 /* We wait for the receiver to be ready */
1164 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1165 while (!(spcr1 & RRDY)) {
1166 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1167 if (attempts++ > 1000) {
1168 /* We must reset the receiver */
1169 MCBSP_WRITE(mcbsp, SPCR1,
1170 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1172 MCBSP_WRITE(mcbsp, SPCR1,
1173 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1175 dev_err(mcbsp->dev, "McBSP%d receiver not "
1176 "ready\n", mcbsp->id);
1181 /* Receiver is ready, there is something for us */
1182 if (rx_word_length > OMAP_MCBSP_WORD_16)
1183 word_msb = MCBSP_READ(mcbsp, DRR2);
1184 word_lsb = MCBSP_READ(mcbsp, DRR1);
1186 word[0] = (word_lsb | (word_msb << 16));
1190 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1193 * Simple DMA based buffer rx/tx routines.
1194 * Nothing fancy, just a single buffer tx/rx through DMA.
1195 * The DMA resources are released once the transfer is done.
1196 * For anything fancier, you should use your own customized DMA
1197 * routines and callbacks.
1199 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1200 unsigned int length)
1202 struct omap_mcbsp *mcbsp;
1208 if (!omap_mcbsp_check_valid_id(id)) {
1209 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1212 mcbsp = id_to_mcbsp_ptr(id);
1214 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1215 omap_mcbsp_tx_dma_callback,
1218 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1219 "McBSP%d TX. Trying IRQ based TX\n",
1223 mcbsp->dma_tx_lch = dma_tx_ch;
1225 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1228 init_completion(&mcbsp->tx_dma_completion);
1230 if (cpu_class_is_omap1()) {
1231 src_port = OMAP_DMA_PORT_TIPB;
1232 dest_port = OMAP_DMA_PORT_EMIFF;
1234 if (cpu_class_is_omap2())
1235 sync_dev = mcbsp->dma_tx_sync;
1237 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1238 OMAP_DMA_DATA_TYPE_S16,
1240 OMAP_DMA_SYNC_ELEMENT,
1243 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1245 OMAP_DMA_AMODE_CONSTANT,
1246 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1249 omap_set_dma_src_params(mcbsp->dma_tx_lch,
1251 OMAP_DMA_AMODE_POST_INC,
1255 omap_start_dma(mcbsp->dma_tx_lch);
1256 wait_for_completion(&mcbsp->tx_dma_completion);
1260 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1262 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1263 unsigned int length)
1265 struct omap_mcbsp *mcbsp;
1271 if (!omap_mcbsp_check_valid_id(id)) {
1272 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1275 mcbsp = id_to_mcbsp_ptr(id);
1277 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1278 omap_mcbsp_rx_dma_callback,
1281 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1282 "McBSP%d RX. Trying IRQ based RX\n",
1286 mcbsp->dma_rx_lch = dma_rx_ch;
1288 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1291 init_completion(&mcbsp->rx_dma_completion);
1293 if (cpu_class_is_omap1()) {
1294 src_port = OMAP_DMA_PORT_TIPB;
1295 dest_port = OMAP_DMA_PORT_EMIFF;
1297 if (cpu_class_is_omap2())
1298 sync_dev = mcbsp->dma_rx_sync;
1300 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1301 OMAP_DMA_DATA_TYPE_S16,
1303 OMAP_DMA_SYNC_ELEMENT,
1306 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1308 OMAP_DMA_AMODE_CONSTANT,
1309 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1312 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1314 OMAP_DMA_AMODE_POST_INC,
1318 omap_start_dma(mcbsp->dma_rx_lch);
1319 wait_for_completion(&mcbsp->rx_dma_completion);
1323 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1327 * Since SPI setup is much simpler than the generic McBSP one,
1328 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1329 * Once this is done, you can call omap_mcbsp_start().
1331 void omap_mcbsp_set_spi_mode(unsigned int id,
1332 const struct omap_mcbsp_spi_cfg *spi_cfg)
1334 struct omap_mcbsp *mcbsp;
1335 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1337 if (!omap_mcbsp_check_valid_id(id)) {
1338 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1341 mcbsp = id_to_mcbsp_ptr(id);
1343 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1345 /* SPI has only one frame */
1346 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1347 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1349 /* Clock stop mode */
1350 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1351 mcbsp_cfg.spcr1 |= (1 << 12);
1353 mcbsp_cfg.spcr1 |= (3 << 11);
1355 /* Set clock parities */
1356 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1357 mcbsp_cfg.pcr0 |= CLKRP;
1359 mcbsp_cfg.pcr0 &= ~CLKRP;
1361 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1362 mcbsp_cfg.pcr0 &= ~CLKXP;
1364 mcbsp_cfg.pcr0 |= CLKXP;
1366 /* Set SCLKME to 0 and CLKSM to 1 */
1367 mcbsp_cfg.pcr0 &= ~SCLKME;
1368 mcbsp_cfg.srgr2 |= CLKSM;
1371 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1372 mcbsp_cfg.pcr0 &= ~FSXP;
1374 mcbsp_cfg.pcr0 |= FSXP;
1376 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1377 mcbsp_cfg.pcr0 |= CLKXM;
1378 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1379 mcbsp_cfg.pcr0 |= FSXM;
1380 mcbsp_cfg.srgr2 &= ~FSGM;
1381 mcbsp_cfg.xcr2 |= XDATDLY(1);
1382 mcbsp_cfg.rcr2 |= RDATDLY(1);
1384 mcbsp_cfg.pcr0 &= ~CLKXM;
1385 mcbsp_cfg.srgr1 |= CLKGDV(1);
1386 mcbsp_cfg.pcr0 &= ~FSXM;
1387 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1388 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1391 mcbsp_cfg.xcr2 &= ~XPHASE;
1392 mcbsp_cfg.rcr2 &= ~RPHASE;
1394 omap_mcbsp_config(id, &mcbsp_cfg);
1396 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1398 #ifdef CONFIG_ARCH_OMAP3
1399 #define max_thres(m) (mcbsp->pdata->buffer_size)
1400 #define valid_threshold(m, val) ((val) <= max_thres(m))
1401 #define THRESHOLD_PROP_BUILDER(prop) \
1402 static ssize_t prop##_show(struct device *dev, \
1403 struct device_attribute *attr, char *buf) \
1405 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1407 return sprintf(buf, "%u\n", mcbsp->prop); \
1410 static ssize_t prop##_store(struct device *dev, \
1411 struct device_attribute *attr, \
1412 const char *buf, size_t size) \
1414 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1415 unsigned long val; \
1418 status = strict_strtoul(buf, 0, &val); \
1422 if (!valid_threshold(mcbsp, val)) \
1425 mcbsp->prop = val; \
1429 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1431 THRESHOLD_PROP_BUILDER(max_tx_thres);
1432 THRESHOLD_PROP_BUILDER(max_rx_thres);
1434 static const char *dma_op_modes[] = {
1435 "element", "threshold", "frame",
1438 static ssize_t dma_op_mode_show(struct device *dev,
1439 struct device_attribute *attr, char *buf)
1441 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1442 int dma_op_mode, i = 0;
1444 const char * const *s;
1446 dma_op_mode = mcbsp->dma_op_mode;
1448 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1449 if (dma_op_mode == i)
1450 len += sprintf(buf + len, "[%s] ", *s);
1452 len += sprintf(buf + len, "%s ", *s);
1454 len += sprintf(buf + len, "\n");
1459 static ssize_t dma_op_mode_store(struct device *dev,
1460 struct device_attribute *attr,
1461 const char *buf, size_t size)
1463 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1464 const char * const *s;
1467 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1468 if (sysfs_streq(buf, *s))
1471 if (i == ARRAY_SIZE(dma_op_modes))
1474 spin_lock_irq(&mcbsp->lock);
1479 mcbsp->dma_op_mode = i;
1482 spin_unlock_irq(&mcbsp->lock);
1487 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1489 static ssize_t st_taps_show(struct device *dev,
1490 struct device_attribute *attr, char *buf)
1492 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1493 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1497 spin_lock_irq(&mcbsp->lock);
1498 for (i = 0; i < st_data->nr_taps; i++)
1499 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1502 status += sprintf(&buf[status], "\n");
1503 spin_unlock_irq(&mcbsp->lock);
1508 static ssize_t st_taps_store(struct device *dev,
1509 struct device_attribute *attr,
1510 const char *buf, size_t size)
1512 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1513 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1514 int val, tmp, status, i = 0;
1516 spin_lock_irq(&mcbsp->lock);
1517 memset(st_data->taps, 0, sizeof(st_data->taps));
1518 st_data->nr_taps = 0;
1521 status = sscanf(buf, "%d%n", &val, &tmp);
1522 if (status < 0 || status == 0) {
1526 if (val < -32768 || val > 32767) {
1530 st_data->taps[i++] = val;
1537 st_data->nr_taps = i;
1540 spin_unlock_irq(&mcbsp->lock);
1545 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1547 static const struct attribute *additional_attrs[] = {
1548 &dev_attr_max_tx_thres.attr,
1549 &dev_attr_max_rx_thres.attr,
1550 &dev_attr_dma_op_mode.attr,
1554 static const struct attribute_group additional_attr_group = {
1555 .attrs = (struct attribute **)additional_attrs,
1558 static inline int __devinit omap_additional_add(struct device *dev)
1560 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1563 static inline void __devexit omap_additional_remove(struct device *dev)
1565 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1568 static const struct attribute *sidetone_attrs[] = {
1569 &dev_attr_st_taps.attr,
1573 static const struct attribute_group sidetone_attr_group = {
1574 .attrs = (struct attribute **)sidetone_attrs,
1577 int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1579 struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1580 struct omap_mcbsp_st_data *st_data;
1583 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1589 st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1590 if (!st_data->io_base_st) {
1595 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1599 mcbsp->st_data = st_data;
1603 iounmap(st_data->io_base_st);
1611 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1613 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1616 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1617 iounmap(st_data->io_base_st);
1622 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1624 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1625 if (cpu_is_omap34xx()) {
1626 mcbsp->max_tx_thres = max_thres(mcbsp);
1627 mcbsp->max_rx_thres = max_thres(mcbsp);
1629 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1630 * for mcbsp2 instances.
1632 if (omap_additional_add(mcbsp->dev))
1633 dev_warn(mcbsp->dev,
1634 "Unable to create additional controls\n");
1636 if (mcbsp->id == 2 || mcbsp->id == 3)
1637 if (omap_st_add(mcbsp))
1638 dev_warn(mcbsp->dev,
1639 "Unable to create sidetone controls\n");
1642 mcbsp->max_tx_thres = -EINVAL;
1643 mcbsp->max_rx_thres = -EINVAL;
1647 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1649 if (cpu_is_omap34xx()) {
1650 omap_additional_remove(mcbsp->dev);
1652 if (mcbsp->id == 2 || mcbsp->id == 3)
1653 omap_st_remove(mcbsp);
1657 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1658 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1659 #endif /* CONFIG_ARCH_OMAP3 */
1662 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1663 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1665 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1667 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1668 struct omap_mcbsp *mcbsp;
1669 int id = pdev->id - 1;
1673 dev_err(&pdev->dev, "McBSP device initialized without"
1679 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1681 if (id >= omap_mcbsp_count) {
1682 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1687 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1693 spin_lock_init(&mcbsp->lock);
1696 mcbsp->dma_tx_lch = -1;
1697 mcbsp->dma_rx_lch = -1;
1699 mcbsp->phys_base = pdata->phys_base;
1700 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1701 if (!mcbsp->io_base) {
1706 /* Default I/O is IRQ based */
1707 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1708 mcbsp->tx_irq = pdata->tx_irq;
1709 mcbsp->rx_irq = pdata->rx_irq;
1710 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1711 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1713 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1714 if (IS_ERR(mcbsp->iclk)) {
1715 ret = PTR_ERR(mcbsp->iclk);
1716 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1720 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1721 if (IS_ERR(mcbsp->fclk)) {
1722 ret = PTR_ERR(mcbsp->fclk);
1723 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1727 mcbsp->pdata = pdata;
1728 mcbsp->dev = &pdev->dev;
1729 mcbsp_ptr[id] = mcbsp;
1730 platform_set_drvdata(pdev, mcbsp);
1732 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1733 omap34xx_device_init(mcbsp);
1738 clk_put(mcbsp->iclk);
1740 iounmap(mcbsp->io_base);
1747 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1749 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1751 platform_set_drvdata(pdev, NULL);
1754 if (mcbsp->pdata && mcbsp->pdata->ops &&
1755 mcbsp->pdata->ops->free)
1756 mcbsp->pdata->ops->free(mcbsp->id);
1758 omap34xx_device_exit(mcbsp);
1760 clk_disable(mcbsp->fclk);
1761 clk_disable(mcbsp->iclk);
1762 clk_put(mcbsp->fclk);
1763 clk_put(mcbsp->iclk);
1765 iounmap(mcbsp->io_base);
1776 static struct platform_driver omap_mcbsp_driver = {
1777 .probe = omap_mcbsp_probe,
1778 .remove = __devexit_p(omap_mcbsp_remove),
1780 .name = "omap-mcbsp",
1784 int __init omap_mcbsp_init(void)
1786 /* Register the McBSP driver */
1787 return platform_driver_register(&omap_mcbsp_driver);