2 * arch/arm/plat-omap/include/mach/io.h
4 * IO definitions for TI OMAP processors and boards
6 * Copied from arch/arm/mach-sa1100/include/mach/io.h
7 * Copyright (C) 1997-1999 Russell King
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 * 06-12-1997 RMK Created.
34 * 07-04-1999 RMK Major cleanup
37 #ifndef __ASM_ARM_ARCH_IO_H
38 #define __ASM_ARM_ARCH_IO_H
40 #include <mach/hardware.h>
42 #define IO_SPACE_LIMIT 0xffffffff
45 * We don't actually have real ISA nor PCI buses, but there is so many
46 * drivers out there that might just work if we fake them...
48 #define __io(a) __typesafe_io(a)
49 #define __mem_pci(a) (a)
52 * ----------------------------------------------------------------------------
54 * ----------------------------------------------------------------------------
60 #define IOMEM(x) ((void __force __iomem *)(x))
63 #define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
64 #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
66 #define OMAP2_IO_OFFSET 0x90000000
67 #define OMAP2_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */
70 * ----------------------------------------------------------------------------
71 * Omap1 specific IO mapping
72 * ----------------------------------------------------------------------------
75 #define OMAP1_IO_PHYS 0xFFFB0000
76 #define OMAP1_IO_SIZE 0x40000
77 #define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
80 * ----------------------------------------------------------------------------
81 * Omap2 specific IO mapping
82 * ----------------------------------------------------------------------------
85 /* We map both L3 and L4 on OMAP2 */
86 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */
87 #define L3_24XX_VIRT 0xf8000000
88 #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
89 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */
90 #define L4_24XX_VIRT 0xd8000000
91 #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
93 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
94 #define L4_WK_243X_VIRT 0xd9000000
95 #define L4_WK_243X_SIZE SZ_1M
96 #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
97 #define OMAP243X_GPMC_VIRT 0xFE000000
98 #define OMAP243X_GPMC_SIZE SZ_1M
99 #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
100 #define OMAP243X_SDRC_VIRT 0xFD000000
101 #define OMAP243X_SDRC_SIZE SZ_1M
102 #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
103 #define OMAP243X_SMS_VIRT 0xFC000000
104 #define OMAP243X_SMS_SIZE SZ_1M
107 #define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
108 #define DSP_MEM_24XX_VIRT 0xe0000000
109 #define DSP_MEM_24XX_SIZE 0x28000
110 #define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
111 #define DSP_IPI_24XX_VIRT 0xe1000000
112 #define DSP_IPI_24XX_SIZE SZ_4K
113 #define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
114 #define DSP_MMU_24XX_VIRT 0xe2000000
115 #define DSP_MMU_24XX_SIZE SZ_4K
118 * ----------------------------------------------------------------------------
119 * Omap3 specific IO mapping
120 * ----------------------------------------------------------------------------
123 /* We map both L3 and L4 on OMAP3 */
124 #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */
125 #define L3_34XX_VIRT 0xf8000000
126 #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
128 #define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */
129 #define L4_34XX_VIRT 0xd8000000
130 #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
133 * Need to look at the Size 4M for L4.
134 * VPOM3430 was not working for Int controller
137 #define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */
138 #define L4_WK_34XX_VIRT 0xd8300000
139 #define L4_WK_34XX_SIZE SZ_1M
141 #define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */
142 #define L4_PER_34XX_VIRT 0xd9000000
143 #define L4_PER_34XX_SIZE SZ_1M
145 #define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */
146 #define L4_EMU_34XX_VIRT 0xe4000000
147 #define L4_EMU_34XX_SIZE SZ_64M
149 #define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */
150 #define OMAP34XX_GPMC_VIRT 0xFE000000
151 #define OMAP34XX_GPMC_SIZE SZ_1M
153 #define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */
154 #define OMAP343X_SMS_VIRT 0xFC000000
155 #define OMAP343X_SMS_SIZE SZ_1M
157 #define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */
158 #define OMAP343X_SDRC_VIRT 0xFD000000
159 #define OMAP343X_SDRC_SIZE SZ_1M
162 #define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
163 #define DSP_MEM_34XX_VIRT 0xe0000000
164 #define DSP_MEM_34XX_SIZE 0x28000
165 #define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
166 #define DSP_IPI_34XX_VIRT 0xe1000000
167 #define DSP_IPI_34XX_SIZE SZ_4K
168 #define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
169 #define DSP_MMU_34XX_VIRT 0xe2000000
170 #define DSP_MMU_34XX_SIZE SZ_4K
173 * ----------------------------------------------------------------------------
174 * Omap4 specific IO mapping
175 * ----------------------------------------------------------------------------
178 /* We map both L3 and L4 on OMAP4 */
179 #define L3_44XX_PHYS L3_44XX_BASE
180 #define L3_44XX_VIRT 0xd4000000
181 #define L3_44XX_SIZE SZ_1M
183 #define L4_44XX_PHYS L4_44XX_BASE
184 #define L4_44XX_VIRT 0xda000000
185 #define L4_44XX_SIZE SZ_4M
188 #define L4_WK_44XX_PHYS L4_WK_44XX_BASE
189 #define L4_WK_44XX_VIRT 0xda300000
190 #define L4_WK_44XX_SIZE SZ_1M
192 #define L4_PER_44XX_PHYS L4_PER_44XX_BASE
193 #define L4_PER_44XX_VIRT 0xd8000000
194 #define L4_PER_44XX_SIZE SZ_4M
196 #define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
197 #define L4_EMU_44XX_VIRT 0xe4000000
198 #define L4_EMU_44XX_SIZE SZ_64M
200 #define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
201 #define OMAP44XX_GPMC_VIRT 0xe0000000
202 #define OMAP44XX_GPMC_SIZE SZ_1M
206 * ----------------------------------------------------------------------------
207 * Omap specific register access
208 * ----------------------------------------------------------------------------
211 #ifndef __ASSEMBLER__
214 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
217 extern u8 omap_readb(u32 pa);
218 extern u16 omap_readw(u32 pa);
219 extern u32 omap_readl(u32 pa);
220 extern void omap_writeb(u8 v, u32 pa);
221 extern void omap_writew(u16 v, u32 pa);
222 extern void omap_writel(u32 v, u32 pa);
224 struct omap_sdrc_params;
226 extern void omap1_map_common_io(void);
227 extern void omap1_init_common_hw(void);
229 extern void omap2_map_common_io(void);
230 extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
231 struct omap_sdrc_params *sdrc_cs1);
233 #define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
234 #define __arch_iounmap(v) omap_iounmap(v)
236 void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
237 void omap_iounmap(volatile void __iomem *addr);