2 * arch/arm/plat-omap/include/mach/clock.h
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ARCH_ARM_OMAP_CLOCK_H
14 #define __ARCH_ARM_OMAP_CLOCK_H
21 int (*enable)(struct clk *);
22 void (*disable)(struct clk *);
25 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
35 const struct clksel_rate *rates;
39 void __iomem *mult_div1_reg;
44 unsigned long last_rounded_rate;
45 unsigned int rate_tolerance;
49 # if defined(CONFIG_ARCH_OMAP3)
51 void __iomem *control_reg;
56 void __iomem *autoidle_reg;
58 void __iomem *idlest_reg;
66 struct list_head node;
67 const struct clkops *ops;
74 void __iomem *enable_reg;
77 void (*recalc)(struct clk *);
78 int (*set_rate)(struct clk *, unsigned long);
79 long (*round_rate)(struct clk *, unsigned long);
80 void (*init)(struct clk *);
81 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
83 void __iomem *clksel_reg;
85 const struct clksel *clksel;
86 struct dpll_data *dpll_data;
87 const char *clkdm_name;
88 struct clockdomain *clkdm;
93 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
94 struct dentry *dent; /* For visible tree hierarchy */
98 struct cpufreq_frequency_table;
100 struct clk_functions {
101 int (*clk_enable)(struct clk *clk);
102 void (*clk_disable)(struct clk *clk);
103 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
104 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
105 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
106 struct clk * (*clk_get_parent)(struct clk *clk);
107 void (*clk_allow_idle)(struct clk *clk);
108 void (*clk_deny_idle)(struct clk *clk);
109 void (*clk_disable_unused)(struct clk *clk);
110 #ifdef CONFIG_CPU_FREQ
111 void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
115 extern unsigned int mpurate;
117 extern int clk_init(struct clk_functions * custom_clocks);
118 extern int clk_register(struct clk *clk);
119 extern void clk_unregister(struct clk *clk);
120 extern void propagate_rate(struct clk *clk);
121 extern void recalculate_root_clocks(void);
122 extern void followparent_recalc(struct clk * clk);
123 extern void clk_allow_idle(struct clk *clk);
124 extern void clk_deny_idle(struct clk *clk);
125 extern int clk_get_usecount(struct clk *clk);
126 extern void clk_enable_init_clocks(void);
129 #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
130 #define RATE_FIXED (1 << 1) /* Fixed clock rate */
131 #define RATE_PROPAGATES (1 << 2) /* Program children too */
132 #define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */
133 #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
134 #define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */
135 #define CLOCK_IDLE_CONTROL (1 << 7)
136 #define CLOCK_NO_IDLE_PARENT (1 << 8)
137 #define DELAYED_APP (1 << 9) /* Delay application of clock */
138 #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
139 #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
140 #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
141 /* bits 13-20 are currently free */
142 #define CLOCK_IN_OMAP310 (1 << 21)
143 #define CLOCK_IN_OMAP730 (1 << 22)
144 #define CLOCK_IN_OMAP1510 (1 << 23)
145 #define CLOCK_IN_OMAP16XX (1 << 24)
146 #define CLOCK_IN_OMAP242X (1 << 25)
147 #define CLOCK_IN_OMAP243X (1 << 26)
148 #define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
149 #define PARENT_CONTROLS_CLOCK (1 << 28)
150 #define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
151 #define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
153 /* Clksel_rate flags */
154 #define DEFAULT_RATE (1 << 0)
155 #define RATE_IN_242X (1 << 1)
156 #define RATE_IN_243X (1 << 2)
157 #define RATE_IN_343X (1 << 3) /* rates common to all 343X */
158 #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
160 #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
163 /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
164 #define CORE_CLK_SRC_32K 0
165 #define CORE_CLK_SRC_DPLL 1
166 #define CORE_CLK_SRC_DPLL_X2 2