2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE 0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE 0xfffbe400
49 #define OMAP1610_GPIO2_BASE 0xfffbec00
50 #define OMAP1610_GPIO3_BASE 0xfffbb400
51 #define OMAP1610_GPIO4_BASE 0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP7XX specific GPIO registers
73 #define OMAP7XX_GPIO1_BASE 0xfffbc000
74 #define OMAP7XX_GPIO2_BASE 0xfffbc800
75 #define OMAP7XX_GPIO3_BASE 0xfffbd000
76 #define OMAP7XX_GPIO4_BASE 0xfffbd800
77 #define OMAP7XX_GPIO5_BASE 0xfffbe000
78 #define OMAP7XX_GPIO6_BASE 0xfffbe800
79 #define OMAP7XX_GPIO_DATA_INPUT 0x00
80 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
82 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
83 #define OMAP7XX_GPIO_INT_MASK 0x10
84 #define OMAP7XX_GPIO_INT_STATUS 0x14
86 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
89 * omap24xx specific GPIO registers
91 #define OMAP242X_GPIO1_BASE 0x48018000
92 #define OMAP242X_GPIO2_BASE 0x4801a000
93 #define OMAP242X_GPIO3_BASE 0x4801c000
94 #define OMAP242X_GPIO4_BASE 0x4801e000
96 #define OMAP243X_GPIO1_BASE 0x4900C000
97 #define OMAP243X_GPIO2_BASE 0x4900E000
98 #define OMAP243X_GPIO3_BASE 0x49010000
99 #define OMAP243X_GPIO4_BASE 0x49012000
100 #define OMAP243X_GPIO5_BASE 0x480B6000
102 #define OMAP24XX_GPIO_REVISION 0x0000
103 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
104 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
105 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
106 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
107 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
108 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
109 #define OMAP24XX_GPIO_WAKE_EN 0x0020
110 #define OMAP24XX_GPIO_CTRL 0x0030
111 #define OMAP24XX_GPIO_OE 0x0034
112 #define OMAP24XX_GPIO_DATAIN 0x0038
113 #define OMAP24XX_GPIO_DATAOUT 0x003c
114 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
115 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
116 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
117 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
118 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
119 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
120 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
121 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
122 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
123 #define OMAP24XX_GPIO_SETWKUENA 0x0084
124 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
125 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
127 #define OMAP4_GPIO_REVISION 0x0000
128 #define OMAP4_GPIO_SYSCONFIG 0x0010
129 #define OMAP4_GPIO_EOI 0x0020
130 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
131 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
132 #define OMAP4_GPIO_IRQSTATUS0 0x002c
133 #define OMAP4_GPIO_IRQSTATUS1 0x0030
134 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
135 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
136 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
137 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138 #define OMAP4_GPIO_IRQWAKEN0 0x0044
139 #define OMAP4_GPIO_IRQWAKEN1 0x0048
140 #define OMAP4_GPIO_SYSSTATUS 0x0104
141 #define OMAP4_GPIO_CTRL 0x0130
142 #define OMAP4_GPIO_OE 0x0134
143 #define OMAP4_GPIO_DATAIN 0x0138
144 #define OMAP4_GPIO_DATAOUT 0x013c
145 #define OMAP4_GPIO_LEVELDETECT0 0x0140
146 #define OMAP4_GPIO_LEVELDETECT1 0x0144
147 #define OMAP4_GPIO_RISINGDETECT 0x0148
148 #define OMAP4_GPIO_FALLINGDETECT 0x014c
149 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
152 #define OMAP4_GPIO_SETDATAOUT 0x0194
154 * omap34xx specific GPIO registers
157 #define OMAP34XX_GPIO1_BASE 0x48310000
158 #define OMAP34XX_GPIO2_BASE 0x49050000
159 #define OMAP34XX_GPIO3_BASE 0x49052000
160 #define OMAP34XX_GPIO4_BASE 0x49054000
161 #define OMAP34XX_GPIO5_BASE 0x49056000
162 #define OMAP34XX_GPIO6_BASE 0x49058000
165 * OMAP44XX specific GPIO registers
167 #define OMAP44XX_GPIO1_BASE 0x4a310000
168 #define OMAP44XX_GPIO2_BASE 0x48055000
169 #define OMAP44XX_GPIO3_BASE 0x48057000
170 #define OMAP44XX_GPIO4_BASE 0x48059000
171 #define OMAP44XX_GPIO5_BASE 0x4805B000
172 #define OMAP44XX_GPIO6_BASE 0x4805D000
178 u16 virtual_irq_start;
180 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
184 #ifdef CONFIG_ARCH_OMAP2PLUS
185 u32 non_wakeup_gpios;
186 u32 enabled_non_wakeup_gpios;
189 u32 saved_fallingdetect;
190 u32 saved_risingdetect;
195 struct gpio_chip chip;
200 #define METHOD_MPUIO 0
201 #define METHOD_GPIO_1510 1
202 #define METHOD_GPIO_1610 2
203 #define METHOD_GPIO_7XX 3
204 #define METHOD_GPIO_24XX 5
205 #define METHOD_GPIO_44XX 6
207 #ifdef CONFIG_ARCH_OMAP16XX
208 static struct gpio_bank gpio_bank_1610[5] = {
209 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
211 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
213 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
215 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
217 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
222 #ifdef CONFIG_ARCH_OMAP15XX
223 static struct gpio_bank gpio_bank_1510[2] = {
224 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
226 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
231 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
232 static struct gpio_bank gpio_bank_7xx[7] = {
233 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
235 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
237 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
239 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
241 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
243 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
245 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
250 #ifdef CONFIG_ARCH_OMAP2
252 static struct gpio_bank gpio_bank_242x[4] = {
253 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
255 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
257 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
259 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
263 static struct gpio_bank gpio_bank_243x[5] = {
264 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
266 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
268 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
270 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
272 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
278 #ifdef CONFIG_ARCH_OMAP3
279 static struct gpio_bank gpio_bank_34xx[6] = {
280 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
282 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
284 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
286 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
288 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
290 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
294 struct omap3_gpio_regs {
310 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
313 #ifdef CONFIG_ARCH_OMAP4
314 static struct gpio_bank gpio_bank_44xx[6] = {
315 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
317 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
319 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
321 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
323 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
325 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
331 static struct gpio_bank *gpio_bank;
332 static int gpio_bank_count;
334 static inline struct gpio_bank *get_gpio_bank(int gpio)
336 if (cpu_is_omap15xx()) {
337 if (OMAP_GPIO_IS_MPUIO(gpio))
338 return &gpio_bank[0];
339 return &gpio_bank[1];
341 if (cpu_is_omap16xx()) {
342 if (OMAP_GPIO_IS_MPUIO(gpio))
343 return &gpio_bank[0];
344 return &gpio_bank[1 + (gpio >> 4)];
346 if (cpu_is_omap7xx()) {
347 if (OMAP_GPIO_IS_MPUIO(gpio))
348 return &gpio_bank[0];
349 return &gpio_bank[1 + (gpio >> 5)];
351 if (cpu_is_omap24xx())
352 return &gpio_bank[gpio >> 5];
353 if (cpu_is_omap34xx() || cpu_is_omap44xx())
354 return &gpio_bank[gpio >> 5];
359 static inline int get_gpio_index(int gpio)
361 if (cpu_is_omap7xx())
363 if (cpu_is_omap24xx())
365 if (cpu_is_omap34xx() || cpu_is_omap44xx())
370 static inline int gpio_valid(int gpio)
374 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
375 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
379 if (cpu_is_omap15xx() && gpio < 16)
381 if ((cpu_is_omap16xx()) && gpio < 64)
383 if (cpu_is_omap7xx() && gpio < 192)
385 if (cpu_is_omap24xx() && gpio < 128)
387 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
392 static int check_gpio(int gpio)
394 if (unlikely(gpio_valid(gpio) < 0)) {
395 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
402 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
404 void __iomem *reg = bank->base;
407 switch (bank->method) {
408 #ifdef CONFIG_ARCH_OMAP1
410 reg += OMAP_MPUIO_IO_CNTL;
413 #ifdef CONFIG_ARCH_OMAP15XX
414 case METHOD_GPIO_1510:
415 reg += OMAP1510_GPIO_DIR_CONTROL;
418 #ifdef CONFIG_ARCH_OMAP16XX
419 case METHOD_GPIO_1610:
420 reg += OMAP1610_GPIO_DIRECTION;
423 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
424 case METHOD_GPIO_7XX:
425 reg += OMAP7XX_GPIO_DIR_CONTROL;
428 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
429 case METHOD_GPIO_24XX:
430 reg += OMAP24XX_GPIO_OE;
433 #if defined(CONFIG_ARCH_OMAP4)
434 case METHOD_GPIO_44XX:
435 reg += OMAP4_GPIO_OE;
442 l = __raw_readl(reg);
447 __raw_writel(l, reg);
450 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
452 void __iomem *reg = bank->base;
455 switch (bank->method) {
456 #ifdef CONFIG_ARCH_OMAP1
458 reg += OMAP_MPUIO_OUTPUT;
459 l = __raw_readl(reg);
466 #ifdef CONFIG_ARCH_OMAP15XX
467 case METHOD_GPIO_1510:
468 reg += OMAP1510_GPIO_DATA_OUTPUT;
469 l = __raw_readl(reg);
476 #ifdef CONFIG_ARCH_OMAP16XX
477 case METHOD_GPIO_1610:
479 reg += OMAP1610_GPIO_SET_DATAOUT;
481 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
485 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
486 case METHOD_GPIO_7XX:
487 reg += OMAP7XX_GPIO_DATA_OUTPUT;
488 l = __raw_readl(reg);
495 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
496 case METHOD_GPIO_24XX:
498 reg += OMAP24XX_GPIO_SETDATAOUT;
500 reg += OMAP24XX_GPIO_CLEARDATAOUT;
504 #ifdef CONFIG_ARCH_OMAP4
505 case METHOD_GPIO_44XX:
507 reg += OMAP4_GPIO_SETDATAOUT;
509 reg += OMAP4_GPIO_CLEARDATAOUT;
517 __raw_writel(l, reg);
520 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
524 if (check_gpio(gpio) < 0)
527 switch (bank->method) {
528 #ifdef CONFIG_ARCH_OMAP1
530 reg += OMAP_MPUIO_INPUT_LATCH;
533 #ifdef CONFIG_ARCH_OMAP15XX
534 case METHOD_GPIO_1510:
535 reg += OMAP1510_GPIO_DATA_INPUT;
538 #ifdef CONFIG_ARCH_OMAP16XX
539 case METHOD_GPIO_1610:
540 reg += OMAP1610_GPIO_DATAIN;
543 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
544 case METHOD_GPIO_7XX:
545 reg += OMAP7XX_GPIO_DATA_INPUT;
548 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
549 case METHOD_GPIO_24XX:
550 reg += OMAP24XX_GPIO_DATAIN;
553 #ifdef CONFIG_ARCH_OMAP4
554 case METHOD_GPIO_44XX:
555 reg += OMAP4_GPIO_DATAIN;
561 return (__raw_readl(reg)
562 & (1 << get_gpio_index(gpio))) != 0;
565 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
569 if (check_gpio(gpio) < 0)
573 switch (bank->method) {
574 #ifdef CONFIG_ARCH_OMAP1
576 reg += OMAP_MPUIO_OUTPUT;
579 #ifdef CONFIG_ARCH_OMAP15XX
580 case METHOD_GPIO_1510:
581 reg += OMAP1510_GPIO_DATA_OUTPUT;
584 #ifdef CONFIG_ARCH_OMAP16XX
585 case METHOD_GPIO_1610:
586 reg += OMAP1610_GPIO_DATAOUT;
589 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
590 case METHOD_GPIO_7XX:
591 reg += OMAP7XX_GPIO_DATA_OUTPUT;
594 #ifdef CONFIG_ARCH_OMAP2PLUS
595 case METHOD_GPIO_24XX:
596 case METHOD_GPIO_44XX:
597 reg += OMAP24XX_GPIO_DATAOUT;
604 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
607 #define MOD_REG_BIT(reg, bit_mask, set) \
609 int l = __raw_readl(base + reg); \
610 if (set) l |= bit_mask; \
611 else l &= ~bit_mask; \
612 __raw_writel(l, base + reg); \
615 void omap_set_gpio_debounce(int gpio, int enable)
617 struct gpio_bank *bank;
620 u32 val, l = 1 << get_gpio_index(gpio);
622 if (cpu_class_is_omap1())
625 bank = get_gpio_bank(gpio);
628 if (cpu_is_omap44xx())
629 reg += OMAP4_GPIO_DEBOUNCENABLE;
631 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
633 if (!(bank->mod_usage & l)) {
634 printk(KERN_ERR "GPIO %d not requested\n", gpio);
638 spin_lock_irqsave(&bank->lock, flags);
639 val = __raw_readl(reg);
641 if (enable && !(val & l))
643 else if (!enable && (val & l))
648 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
650 clk_enable(bank->dbck);
652 clk_disable(bank->dbck);
655 __raw_writel(val, reg);
657 spin_unlock_irqrestore(&bank->lock, flags);
659 EXPORT_SYMBOL(omap_set_gpio_debounce);
661 void omap_set_gpio_debounce_time(int gpio, int enc_time)
663 struct gpio_bank *bank;
666 if (cpu_class_is_omap1())
669 bank = get_gpio_bank(gpio);
672 if (!bank->mod_usage) {
673 printk(KERN_ERR "GPIO not requested\n");
679 if (cpu_is_omap44xx())
680 reg += OMAP4_GPIO_DEBOUNCINGTIME;
682 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
684 __raw_writel(enc_time, reg);
686 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
688 #ifdef CONFIG_ARCH_OMAP2PLUS
689 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
692 void __iomem *base = bank->base;
693 u32 gpio_bit = 1 << gpio;
696 if (cpu_is_omap44xx()) {
697 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
698 trigger & IRQ_TYPE_LEVEL_LOW);
699 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
700 trigger & IRQ_TYPE_LEVEL_HIGH);
701 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
702 trigger & IRQ_TYPE_EDGE_RISING);
703 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
704 trigger & IRQ_TYPE_EDGE_FALLING);
706 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
707 trigger & IRQ_TYPE_LEVEL_LOW);
708 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
709 trigger & IRQ_TYPE_LEVEL_HIGH);
710 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
711 trigger & IRQ_TYPE_EDGE_RISING);
712 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
713 trigger & IRQ_TYPE_EDGE_FALLING);
715 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
716 if (cpu_is_omap44xx()) {
718 __raw_writel(1 << gpio, bank->base+
719 OMAP4_GPIO_IRQWAKEN0);
721 val = __raw_readl(bank->base +
722 OMAP4_GPIO_IRQWAKEN0);
723 __raw_writel(val & (~(1 << gpio)), bank->base +
724 OMAP4_GPIO_IRQWAKEN0);
728 * GPIO wakeup request can only be generated on edge
731 if (trigger & IRQ_TYPE_EDGE_BOTH)
732 __raw_writel(1 << gpio, bank->base
733 + OMAP24XX_GPIO_SETWKUENA);
735 __raw_writel(1 << gpio, bank->base
736 + OMAP24XX_GPIO_CLEARWKUENA);
739 /* This part needs to be executed always for OMAP34xx */
740 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
742 * Log the edge gpio and manually trigger the IRQ
743 * after resume if the input level changes
744 * to avoid irq lost during PER RET/OFF mode
745 * Applies for omap2 non-wakeup gpio and all omap3 gpios
747 if (trigger & IRQ_TYPE_EDGE_BOTH)
748 bank->enabled_non_wakeup_gpios |= gpio_bit;
750 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
753 if (cpu_is_omap44xx()) {
755 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
756 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
759 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
760 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
765 #ifdef CONFIG_ARCH_OMAP1
767 * This only applies to chips that can't do both rising and falling edge
768 * detection at once. For all other chips, this function is a noop.
770 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
772 void __iomem *reg = bank->base;
775 switch (bank->method) {
777 reg += OMAP_MPUIO_GPIO_INT_EDGE;
779 #ifdef CONFIG_ARCH_OMAP15XX
780 case METHOD_GPIO_1510:
781 reg += OMAP1510_GPIO_INT_CONTROL;
784 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
785 case METHOD_GPIO_7XX:
786 reg += OMAP7XX_GPIO_INT_CONTROL;
793 l = __raw_readl(reg);
799 __raw_writel(l, reg);
803 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
805 void __iomem *reg = bank->base;
808 switch (bank->method) {
809 #ifdef CONFIG_ARCH_OMAP1
811 reg += OMAP_MPUIO_GPIO_INT_EDGE;
812 l = __raw_readl(reg);
813 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
814 bank->toggle_mask |= 1 << gpio;
815 if (trigger & IRQ_TYPE_EDGE_RISING)
817 else if (trigger & IRQ_TYPE_EDGE_FALLING)
823 #ifdef CONFIG_ARCH_OMAP15XX
824 case METHOD_GPIO_1510:
825 reg += OMAP1510_GPIO_INT_CONTROL;
826 l = __raw_readl(reg);
827 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
828 bank->toggle_mask |= 1 << gpio;
829 if (trigger & IRQ_TYPE_EDGE_RISING)
831 else if (trigger & IRQ_TYPE_EDGE_FALLING)
837 #ifdef CONFIG_ARCH_OMAP16XX
838 case METHOD_GPIO_1610:
840 reg += OMAP1610_GPIO_EDGE_CTRL2;
842 reg += OMAP1610_GPIO_EDGE_CTRL1;
844 l = __raw_readl(reg);
845 l &= ~(3 << (gpio << 1));
846 if (trigger & IRQ_TYPE_EDGE_RISING)
847 l |= 2 << (gpio << 1);
848 if (trigger & IRQ_TYPE_EDGE_FALLING)
849 l |= 1 << (gpio << 1);
851 /* Enable wake-up during idle for dynamic tick */
852 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
854 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
857 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
858 case METHOD_GPIO_7XX:
859 reg += OMAP7XX_GPIO_INT_CONTROL;
860 l = __raw_readl(reg);
861 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
862 bank->toggle_mask |= 1 << gpio;
863 if (trigger & IRQ_TYPE_EDGE_RISING)
865 else if (trigger & IRQ_TYPE_EDGE_FALLING)
871 #ifdef CONFIG_ARCH_OMAP2PLUS
872 case METHOD_GPIO_24XX:
873 case METHOD_GPIO_44XX:
874 set_24xx_gpio_triggering(bank, gpio, trigger);
880 __raw_writel(l, reg);
886 static int gpio_irq_type(unsigned irq, unsigned type)
888 struct gpio_bank *bank;
893 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
894 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
896 gpio = irq - IH_GPIO_BASE;
898 if (check_gpio(gpio) < 0)
901 if (type & ~IRQ_TYPE_SENSE_MASK)
904 /* OMAP1 allows only only edge triggering */
905 if (!cpu_class_is_omap2()
906 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
909 bank = get_irq_chip_data(irq);
910 spin_lock_irqsave(&bank->lock, flags);
911 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
913 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
914 irq_desc[irq].status |= type;
916 spin_unlock_irqrestore(&bank->lock, flags);
918 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
919 __set_irq_handler_unlocked(irq, handle_level_irq);
920 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
921 __set_irq_handler_unlocked(irq, handle_edge_irq);
926 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
928 void __iomem *reg = bank->base;
930 switch (bank->method) {
931 #ifdef CONFIG_ARCH_OMAP1
933 /* MPUIO irqstatus is reset by reading the status register,
934 * so do nothing here */
937 #ifdef CONFIG_ARCH_OMAP15XX
938 case METHOD_GPIO_1510:
939 reg += OMAP1510_GPIO_INT_STATUS;
942 #ifdef CONFIG_ARCH_OMAP16XX
943 case METHOD_GPIO_1610:
944 reg += OMAP1610_GPIO_IRQSTATUS1;
947 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
948 case METHOD_GPIO_7XX:
949 reg += OMAP7XX_GPIO_INT_STATUS;
952 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
953 case METHOD_GPIO_24XX:
954 reg += OMAP24XX_GPIO_IRQSTATUS1;
957 #if defined(CONFIG_ARCH_OMAP4)
958 case METHOD_GPIO_44XX:
959 reg += OMAP4_GPIO_IRQSTATUS0;
966 __raw_writel(gpio_mask, reg);
968 /* Workaround for clearing DSP GPIO interrupts to allow retention */
969 if (cpu_is_omap24xx() || cpu_is_omap34xx())
970 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
971 else if (cpu_is_omap44xx())
972 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
974 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
975 __raw_writel(gpio_mask, reg);
977 /* Flush posted write for the irq status to avoid spurious interrupts */
982 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
984 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
987 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
989 void __iomem *reg = bank->base;
994 switch (bank->method) {
995 #ifdef CONFIG_ARCH_OMAP1
997 reg += OMAP_MPUIO_GPIO_MASKIT;
1002 #ifdef CONFIG_ARCH_OMAP15XX
1003 case METHOD_GPIO_1510:
1004 reg += OMAP1510_GPIO_INT_MASK;
1009 #ifdef CONFIG_ARCH_OMAP16XX
1010 case METHOD_GPIO_1610:
1011 reg += OMAP1610_GPIO_IRQENABLE1;
1015 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1016 case METHOD_GPIO_7XX:
1017 reg += OMAP7XX_GPIO_INT_MASK;
1022 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1023 case METHOD_GPIO_24XX:
1024 reg += OMAP24XX_GPIO_IRQENABLE1;
1028 #if defined(CONFIG_ARCH_OMAP4)
1029 case METHOD_GPIO_44XX:
1030 reg += OMAP4_GPIO_IRQSTATUSSET0;
1039 l = __raw_readl(reg);
1046 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1048 void __iomem *reg = bank->base;
1051 switch (bank->method) {
1052 #ifdef CONFIG_ARCH_OMAP1
1054 reg += OMAP_MPUIO_GPIO_MASKIT;
1055 l = __raw_readl(reg);
1062 #ifdef CONFIG_ARCH_OMAP15XX
1063 case METHOD_GPIO_1510:
1064 reg += OMAP1510_GPIO_INT_MASK;
1065 l = __raw_readl(reg);
1072 #ifdef CONFIG_ARCH_OMAP16XX
1073 case METHOD_GPIO_1610:
1075 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1077 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1081 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1082 case METHOD_GPIO_7XX:
1083 reg += OMAP7XX_GPIO_INT_MASK;
1084 l = __raw_readl(reg);
1091 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1092 case METHOD_GPIO_24XX:
1094 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1096 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1100 #ifdef CONFIG_ARCH_OMAP4
1101 case METHOD_GPIO_44XX:
1103 reg += OMAP4_GPIO_IRQSTATUSSET0;
1105 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1113 __raw_writel(l, reg);
1116 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1118 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1122 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1123 * 1510 does not seem to have a wake-up register. If JTAG is connected
1124 * to the target, system will wake up always on GPIO events. While
1125 * system is running all registered GPIO interrupts need to have wake-up
1126 * enabled. When system is suspended, only selected GPIO interrupts need
1127 * to have wake-up enabled.
1129 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1131 unsigned long uninitialized_var(flags);
1133 switch (bank->method) {
1134 #ifdef CONFIG_ARCH_OMAP16XX
1136 case METHOD_GPIO_1610:
1137 spin_lock_irqsave(&bank->lock, flags);
1139 bank->suspend_wakeup |= (1 << gpio);
1141 bank->suspend_wakeup &= ~(1 << gpio);
1142 spin_unlock_irqrestore(&bank->lock, flags);
1145 #ifdef CONFIG_ARCH_OMAP2PLUS
1146 case METHOD_GPIO_24XX:
1147 case METHOD_GPIO_44XX:
1148 if (bank->non_wakeup_gpios & (1 << gpio)) {
1149 printk(KERN_ERR "Unable to modify wakeup on "
1150 "non-wakeup GPIO%d\n",
1151 (bank - gpio_bank) * 32 + gpio);
1154 spin_lock_irqsave(&bank->lock, flags);
1156 bank->suspend_wakeup |= (1 << gpio);
1158 bank->suspend_wakeup &= ~(1 << gpio);
1159 spin_unlock_irqrestore(&bank->lock, flags);
1163 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1169 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1171 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1172 _set_gpio_irqenable(bank, gpio, 0);
1173 _clear_gpio_irqstatus(bank, gpio);
1174 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1177 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1178 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1180 unsigned int gpio = irq - IH_GPIO_BASE;
1181 struct gpio_bank *bank;
1184 if (check_gpio(gpio) < 0)
1186 bank = get_irq_chip_data(irq);
1187 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1192 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1194 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1195 unsigned long flags;
1197 spin_lock_irqsave(&bank->lock, flags);
1199 /* Set trigger to none. You need to enable the desired trigger with
1200 * request_irq() or set_irq_type().
1202 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1204 #ifdef CONFIG_ARCH_OMAP15XX
1205 if (bank->method == METHOD_GPIO_1510) {
1208 /* Claim the pin for MPU */
1209 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1210 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1213 if (!cpu_class_is_omap1()) {
1214 if (!bank->mod_usage) {
1216 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1218 /* Module is enabled, clocks are not gated */
1219 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1221 bank->mod_usage |= 1 << offset;
1223 spin_unlock_irqrestore(&bank->lock, flags);
1228 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1230 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1231 unsigned long flags;
1233 spin_lock_irqsave(&bank->lock, flags);
1234 #ifdef CONFIG_ARCH_OMAP16XX
1235 if (bank->method == METHOD_GPIO_1610) {
1236 /* Disable wake-up during idle for dynamic tick */
1237 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1238 __raw_writel(1 << offset, reg);
1241 #ifdef CONFIG_ARCH_OMAP2PLUS
1242 if ((bank->method == METHOD_GPIO_24XX) ||
1243 (bank->method == METHOD_GPIO_44XX)) {
1244 /* Disable wake-up during idle for dynamic tick */
1245 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1246 __raw_writel(1 << offset, reg);
1249 if (!cpu_class_is_omap1()) {
1250 bank->mod_usage &= ~(1 << offset);
1251 if (!bank->mod_usage) {
1253 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1254 /* Module is disabled, clocks are gated */
1256 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1259 _reset_gpio(bank, bank->chip.base + offset);
1260 spin_unlock_irqrestore(&bank->lock, flags);
1264 * We need to unmask the GPIO bank interrupt as soon as possible to
1265 * avoid missing GPIO interrupts for other lines in the bank.
1266 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1267 * in the bank to avoid missing nested interrupts for a GPIO line.
1268 * If we wait to unmask individual GPIO lines in the bank after the
1269 * line's interrupt handler has been run, we may miss some nested
1272 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1274 void __iomem *isr_reg = NULL;
1276 unsigned int gpio_irq, gpio_index;
1277 struct gpio_bank *bank;
1281 desc->chip->ack(irq);
1283 bank = get_irq_data(irq);
1284 #ifdef CONFIG_ARCH_OMAP1
1285 if (bank->method == METHOD_MPUIO)
1286 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1288 #ifdef CONFIG_ARCH_OMAP15XX
1289 if (bank->method == METHOD_GPIO_1510)
1290 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1292 #if defined(CONFIG_ARCH_OMAP16XX)
1293 if (bank->method == METHOD_GPIO_1610)
1294 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1296 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1297 if (bank->method == METHOD_GPIO_7XX)
1298 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1300 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1301 if (bank->method == METHOD_GPIO_24XX)
1302 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1304 #if defined(CONFIG_ARCH_OMAP4)
1305 if (bank->method == METHOD_GPIO_44XX)
1306 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1309 u32 isr_saved, level_mask = 0;
1312 enabled = _get_gpio_irqbank_mask(bank);
1313 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1315 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1318 if (cpu_class_is_omap2()) {
1319 level_mask = bank->level_mask & enabled;
1322 /* clear edge sensitive interrupts before handler(s) are
1323 called so that we don't miss any interrupt occurred while
1325 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1326 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1327 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1329 /* if there is only edge sensitive GPIO pin interrupts
1330 configured, we could unmask GPIO bank interrupt immediately */
1331 if (!level_mask && !unmasked) {
1333 desc->chip->unmask(irq);
1341 gpio_irq = bank->virtual_irq_start;
1342 for (; isr != 0; isr >>= 1, gpio_irq++) {
1343 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1348 #ifdef CONFIG_ARCH_OMAP1
1350 * Some chips can't respond to both rising and falling
1351 * at the same time. If this irq was requested with
1352 * both flags, we need to flip the ICR data for the IRQ
1353 * to respond to the IRQ for the opposite direction.
1354 * This will be indicated in the bank toggle_mask.
1356 if (bank->toggle_mask & (1 << gpio_index))
1357 _toggle_gpio_edge_triggering(bank, gpio_index);
1360 generic_handle_irq(gpio_irq);
1363 /* if bank has any level sensitive GPIO pin interrupt
1364 configured, we must unmask the bank interrupt only after
1365 handler(s) are executed in order to avoid spurious bank
1368 desc->chip->unmask(irq);
1372 static void gpio_irq_shutdown(unsigned int irq)
1374 unsigned int gpio = irq - IH_GPIO_BASE;
1375 struct gpio_bank *bank = get_irq_chip_data(irq);
1377 _reset_gpio(bank, gpio);
1380 static void gpio_ack_irq(unsigned int irq)
1382 unsigned int gpio = irq - IH_GPIO_BASE;
1383 struct gpio_bank *bank = get_irq_chip_data(irq);
1385 _clear_gpio_irqstatus(bank, gpio);
1388 static void gpio_mask_irq(unsigned int irq)
1390 unsigned int gpio = irq - IH_GPIO_BASE;
1391 struct gpio_bank *bank = get_irq_chip_data(irq);
1393 _set_gpio_irqenable(bank, gpio, 0);
1394 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1397 static void gpio_unmask_irq(unsigned int irq)
1399 unsigned int gpio = irq - IH_GPIO_BASE;
1400 struct gpio_bank *bank = get_irq_chip_data(irq);
1401 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1402 struct irq_desc *desc = irq_to_desc(irq);
1403 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1406 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1408 /* For level-triggered GPIOs, the clearing must be done after
1409 * the HW source is cleared, thus after the handler has run */
1410 if (bank->level_mask & irq_mask) {
1411 _set_gpio_irqenable(bank, gpio, 0);
1412 _clear_gpio_irqstatus(bank, gpio);
1415 _set_gpio_irqenable(bank, gpio, 1);
1418 static struct irq_chip gpio_irq_chip = {
1420 .shutdown = gpio_irq_shutdown,
1421 .ack = gpio_ack_irq,
1422 .mask = gpio_mask_irq,
1423 .unmask = gpio_unmask_irq,
1424 .set_type = gpio_irq_type,
1425 .set_wake = gpio_wake_enable,
1428 /*---------------------------------------------------------------------*/
1430 #ifdef CONFIG_ARCH_OMAP1
1432 /* MPUIO uses the always-on 32k clock */
1434 static void mpuio_ack_irq(unsigned int irq)
1436 /* The ISR is reset automatically, so do nothing here. */
1439 static void mpuio_mask_irq(unsigned int irq)
1441 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1442 struct gpio_bank *bank = get_irq_chip_data(irq);
1444 _set_gpio_irqenable(bank, gpio, 0);
1447 static void mpuio_unmask_irq(unsigned int irq)
1449 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1450 struct gpio_bank *bank = get_irq_chip_data(irq);
1452 _set_gpio_irqenable(bank, gpio, 1);
1455 static struct irq_chip mpuio_irq_chip = {
1457 .ack = mpuio_ack_irq,
1458 .mask = mpuio_mask_irq,
1459 .unmask = mpuio_unmask_irq,
1460 .set_type = gpio_irq_type,
1461 #ifdef CONFIG_ARCH_OMAP16XX
1462 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1463 .set_wake = gpio_wake_enable,
1468 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1471 #ifdef CONFIG_ARCH_OMAP16XX
1473 #include <linux/platform_device.h>
1475 static int omap_mpuio_suspend_noirq(struct device *dev)
1477 struct platform_device *pdev = to_platform_device(dev);
1478 struct gpio_bank *bank = platform_get_drvdata(pdev);
1479 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1480 unsigned long flags;
1482 spin_lock_irqsave(&bank->lock, flags);
1483 bank->saved_wakeup = __raw_readl(mask_reg);
1484 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1485 spin_unlock_irqrestore(&bank->lock, flags);
1490 static int omap_mpuio_resume_noirq(struct device *dev)
1492 struct platform_device *pdev = to_platform_device(dev);
1493 struct gpio_bank *bank = platform_get_drvdata(pdev);
1494 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1495 unsigned long flags;
1497 spin_lock_irqsave(&bank->lock, flags);
1498 __raw_writel(bank->saved_wakeup, mask_reg);
1499 spin_unlock_irqrestore(&bank->lock, flags);
1504 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1505 .suspend_noirq = omap_mpuio_suspend_noirq,
1506 .resume_noirq = omap_mpuio_resume_noirq,
1509 /* use platform_driver for this, now that there's no longer any
1510 * point to sys_device (other than not disturbing old code).
1512 static struct platform_driver omap_mpuio_driver = {
1515 .pm = &omap_mpuio_dev_pm_ops,
1519 static struct platform_device omap_mpuio_device = {
1523 .driver = &omap_mpuio_driver.driver,
1525 /* could list the /proc/iomem resources */
1528 static inline void mpuio_init(void)
1530 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1532 if (platform_driver_register(&omap_mpuio_driver) == 0)
1533 (void) platform_device_register(&omap_mpuio_device);
1537 static inline void mpuio_init(void) {}
1542 extern struct irq_chip mpuio_irq_chip;
1544 #define bank_is_mpuio(bank) 0
1545 static inline void mpuio_init(void) {}
1549 /*---------------------------------------------------------------------*/
1551 /* REVISIT these are stupid implementations! replace by ones that
1552 * don't switch on METHOD_* and which mostly avoid spinlocks
1555 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1557 struct gpio_bank *bank;
1558 unsigned long flags;
1560 bank = container_of(chip, struct gpio_bank, chip);
1561 spin_lock_irqsave(&bank->lock, flags);
1562 _set_gpio_direction(bank, offset, 1);
1563 spin_unlock_irqrestore(&bank->lock, flags);
1567 static int gpio_is_input(struct gpio_bank *bank, int mask)
1569 void __iomem *reg = bank->base;
1571 switch (bank->method) {
1573 reg += OMAP_MPUIO_IO_CNTL;
1575 case METHOD_GPIO_1510:
1576 reg += OMAP1510_GPIO_DIR_CONTROL;
1578 case METHOD_GPIO_1610:
1579 reg += OMAP1610_GPIO_DIRECTION;
1581 case METHOD_GPIO_7XX:
1582 reg += OMAP7XX_GPIO_DIR_CONTROL;
1584 case METHOD_GPIO_24XX:
1585 case METHOD_GPIO_44XX:
1586 reg += OMAP24XX_GPIO_OE;
1589 return __raw_readl(reg) & mask;
1592 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1594 struct gpio_bank *bank;
1599 gpio = chip->base + offset;
1600 bank = get_gpio_bank(gpio);
1602 mask = 1 << get_gpio_index(gpio);
1604 if (gpio_is_input(bank, mask))
1605 return _get_gpio_datain(bank, gpio);
1607 return _get_gpio_dataout(bank, gpio);
1610 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1612 struct gpio_bank *bank;
1613 unsigned long flags;
1615 bank = container_of(chip, struct gpio_bank, chip);
1616 spin_lock_irqsave(&bank->lock, flags);
1617 _set_gpio_dataout(bank, offset, value);
1618 _set_gpio_direction(bank, offset, 0);
1619 spin_unlock_irqrestore(&bank->lock, flags);
1623 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1625 struct gpio_bank *bank;
1626 unsigned long flags;
1628 bank = container_of(chip, struct gpio_bank, chip);
1629 spin_lock_irqsave(&bank->lock, flags);
1630 _set_gpio_dataout(bank, offset, value);
1631 spin_unlock_irqrestore(&bank->lock, flags);
1634 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1636 struct gpio_bank *bank;
1638 bank = container_of(chip, struct gpio_bank, chip);
1639 return bank->virtual_irq_start + offset;
1642 /*---------------------------------------------------------------------*/
1644 static int initialized;
1645 #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1646 static struct clk * gpio_ick;
1649 #if defined(CONFIG_ARCH_OMAP2)
1650 static struct clk * gpio_fck;
1653 #if defined(CONFIG_ARCH_OMAP2430)
1654 static struct clk * gpio5_ick;
1655 static struct clk * gpio5_fck;
1658 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1659 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1662 static void __init omap_gpio_show_rev(void)
1666 if (cpu_is_omap16xx())
1667 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1668 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1669 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1670 else if (cpu_is_omap44xx())
1671 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1675 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1676 (rev >> 4) & 0x0f, rev & 0x0f);
1679 /* This lock class tells lockdep that GPIO irqs are in a different
1680 * category than their parents, so it won't report false recursion.
1682 static struct lock_class_key gpio_lock_class;
1684 static int __init _omap_gpio_init(void)
1688 struct gpio_bank *bank;
1689 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1694 #if defined(CONFIG_ARCH_OMAP1)
1695 if (cpu_is_omap15xx()) {
1696 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1697 if (IS_ERR(gpio_ick))
1698 printk("Could not get arm_gpio_ck\n");
1700 clk_enable(gpio_ick);
1703 #if defined(CONFIG_ARCH_OMAP2)
1704 if (cpu_class_is_omap2()) {
1705 gpio_ick = clk_get(NULL, "gpios_ick");
1706 if (IS_ERR(gpio_ick))
1707 printk("Could not get gpios_ick\n");
1709 clk_enable(gpio_ick);
1710 gpio_fck = clk_get(NULL, "gpios_fck");
1711 if (IS_ERR(gpio_fck))
1712 printk("Could not get gpios_fck\n");
1714 clk_enable(gpio_fck);
1717 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1719 #if defined(CONFIG_ARCH_OMAP2430)
1720 if (cpu_is_omap2430()) {
1721 gpio5_ick = clk_get(NULL, "gpio5_ick");
1722 if (IS_ERR(gpio5_ick))
1723 printk("Could not get gpio5_ick\n");
1725 clk_enable(gpio5_ick);
1726 gpio5_fck = clk_get(NULL, "gpio5_fck");
1727 if (IS_ERR(gpio5_fck))
1728 printk("Could not get gpio5_fck\n");
1730 clk_enable(gpio5_fck);
1736 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1737 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1738 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1739 sprintf(clk_name, "gpio%d_ick", i + 1);
1740 gpio_iclks[i] = clk_get(NULL, clk_name);
1741 if (IS_ERR(gpio_iclks[i]))
1742 printk(KERN_ERR "Could not get %s\n", clk_name);
1744 clk_enable(gpio_iclks[i]);
1750 #ifdef CONFIG_ARCH_OMAP15XX
1751 if (cpu_is_omap15xx()) {
1752 gpio_bank_count = 2;
1753 gpio_bank = gpio_bank_1510;
1757 #if defined(CONFIG_ARCH_OMAP16XX)
1758 if (cpu_is_omap16xx()) {
1759 gpio_bank_count = 5;
1760 gpio_bank = gpio_bank_1610;
1764 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1765 if (cpu_is_omap7xx()) {
1766 gpio_bank_count = 7;
1767 gpio_bank = gpio_bank_7xx;
1771 #ifdef CONFIG_ARCH_OMAP2
1772 if (cpu_is_omap242x()) {
1773 gpio_bank_count = 4;
1774 gpio_bank = gpio_bank_242x;
1776 if (cpu_is_omap243x()) {
1777 gpio_bank_count = 5;
1778 gpio_bank = gpio_bank_243x;
1781 #ifdef CONFIG_ARCH_OMAP3
1782 if (cpu_is_omap34xx()) {
1783 gpio_bank_count = OMAP34XX_NR_GPIOS;
1784 gpio_bank = gpio_bank_34xx;
1787 #ifdef CONFIG_ARCH_OMAP4
1788 if (cpu_is_omap44xx()) {
1789 gpio_bank_count = OMAP34XX_NR_GPIOS;
1790 gpio_bank = gpio_bank_44xx;
1793 for (i = 0; i < gpio_bank_count; i++) {
1794 int j, gpio_count = 16;
1796 bank = &gpio_bank[i];
1797 spin_lock_init(&bank->lock);
1799 /* Static mapping, never released */
1800 bank->base = ioremap(bank->pbase, bank_size);
1802 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1806 if (bank_is_mpuio(bank))
1807 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1808 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1809 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1810 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1812 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1813 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1814 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1815 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1817 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1818 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1819 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1821 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1824 #ifdef CONFIG_ARCH_OMAP2PLUS
1825 if ((bank->method == METHOD_GPIO_24XX) ||
1826 (bank->method == METHOD_GPIO_44XX)) {
1827 static const u32 non_wakeup_gpios[] = {
1828 0xe203ffc0, 0x08700040
1831 if (cpu_is_omap44xx()) {
1832 __raw_writel(0xffffffff, bank->base +
1833 OMAP4_GPIO_IRQSTATUSCLR0);
1834 __raw_writew(0x0015, bank->base +
1835 OMAP4_GPIO_SYSCONFIG);
1836 __raw_writel(0x00000000, bank->base +
1837 OMAP4_GPIO_DEBOUNCENABLE);
1839 * Initialize interface clock ungated,
1842 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1844 __raw_writel(0x00000000, bank->base +
1845 OMAP24XX_GPIO_IRQENABLE1);
1846 __raw_writel(0xffffffff, bank->base +
1847 OMAP24XX_GPIO_IRQSTATUS1);
1848 __raw_writew(0x0015, bank->base +
1849 OMAP24XX_GPIO_SYSCONFIG);
1850 __raw_writel(0x00000000, bank->base +
1851 OMAP24XX_GPIO_DEBOUNCE_EN);
1854 * Initialize interface clock ungated,
1857 __raw_writel(0, bank->base +
1858 OMAP24XX_GPIO_CTRL);
1860 if (cpu_is_omap24xx() &&
1861 i < ARRAY_SIZE(non_wakeup_gpios))
1862 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1867 bank->mod_usage = 0;
1868 /* REVISIT eventually switch from OMAP-specific gpio structs
1869 * over to the generic ones
1871 bank->chip.request = omap_gpio_request;
1872 bank->chip.free = omap_gpio_free;
1873 bank->chip.direction_input = gpio_input;
1874 bank->chip.get = gpio_get;
1875 bank->chip.direction_output = gpio_output;
1876 bank->chip.set = gpio_set;
1877 bank->chip.to_irq = gpio_2irq;
1878 if (bank_is_mpuio(bank)) {
1879 bank->chip.label = "mpuio";
1880 #ifdef CONFIG_ARCH_OMAP16XX
1881 bank->chip.dev = &omap_mpuio_device.dev;
1883 bank->chip.base = OMAP_MPUIO(0);
1885 bank->chip.label = "gpio";
1886 bank->chip.base = gpio;
1889 bank->chip.ngpio = gpio_count;
1891 gpiochip_add(&bank->chip);
1893 for (j = bank->virtual_irq_start;
1894 j < bank->virtual_irq_start + gpio_count; j++) {
1895 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1896 set_irq_chip_data(j, bank);
1897 if (bank_is_mpuio(bank))
1898 set_irq_chip(j, &mpuio_irq_chip);
1900 set_irq_chip(j, &gpio_irq_chip);
1901 set_irq_handler(j, handle_simple_irq);
1902 set_irq_flags(j, IRQF_VALID);
1904 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1905 set_irq_data(bank->irq, bank);
1907 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1908 sprintf(clk_name, "gpio%d_dbck", i + 1);
1909 bank->dbck = clk_get(NULL, clk_name);
1910 if (IS_ERR(bank->dbck))
1911 printk(KERN_ERR "Could not get %s\n", clk_name);
1915 /* Enable system clock for GPIO module.
1916 * The CAM_CLK_CTRL *is* really the right place. */
1917 if (cpu_is_omap16xx())
1918 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1920 /* Enable autoidle for the OCP interface */
1921 if (cpu_is_omap24xx())
1922 omap_writel(1 << 0, 0x48019010);
1923 if (cpu_is_omap34xx())
1924 omap_writel(1 << 0, 0x48306814);
1926 omap_gpio_show_rev();
1931 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1932 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1936 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1939 for (i = 0; i < gpio_bank_count; i++) {
1940 struct gpio_bank *bank = &gpio_bank[i];
1941 void __iomem *wake_status;
1942 void __iomem *wake_clear;
1943 void __iomem *wake_set;
1944 unsigned long flags;
1946 switch (bank->method) {
1947 #ifdef CONFIG_ARCH_OMAP16XX
1948 case METHOD_GPIO_1610:
1949 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1950 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1951 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1954 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1955 case METHOD_GPIO_24XX:
1956 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1957 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1958 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1961 #ifdef CONFIG_ARCH_OMAP4
1962 case METHOD_GPIO_44XX:
1963 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1964 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1965 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1972 spin_lock_irqsave(&bank->lock, flags);
1973 bank->saved_wakeup = __raw_readl(wake_status);
1974 __raw_writel(0xffffffff, wake_clear);
1975 __raw_writel(bank->suspend_wakeup, wake_set);
1976 spin_unlock_irqrestore(&bank->lock, flags);
1982 static int omap_gpio_resume(struct sys_device *dev)
1986 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1989 for (i = 0; i < gpio_bank_count; i++) {
1990 struct gpio_bank *bank = &gpio_bank[i];
1991 void __iomem *wake_clear;
1992 void __iomem *wake_set;
1993 unsigned long flags;
1995 switch (bank->method) {
1996 #ifdef CONFIG_ARCH_OMAP16XX
1997 case METHOD_GPIO_1610:
1998 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1999 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
2002 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
2003 case METHOD_GPIO_24XX:
2004 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
2005 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
2008 #ifdef CONFIG_ARCH_OMAP4
2009 case METHOD_GPIO_44XX:
2010 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
2011 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
2018 spin_lock_irqsave(&bank->lock, flags);
2019 __raw_writel(0xffffffff, wake_clear);
2020 __raw_writel(bank->saved_wakeup, wake_set);
2021 spin_unlock_irqrestore(&bank->lock, flags);
2027 static struct sysdev_class omap_gpio_sysclass = {
2029 .suspend = omap_gpio_suspend,
2030 .resume = omap_gpio_resume,
2033 static struct sys_device omap_gpio_device = {
2035 .cls = &omap_gpio_sysclass,
2040 #ifdef CONFIG_ARCH_OMAP2PLUS
2042 static int workaround_enabled;
2044 void omap2_gpio_prepare_for_retention(void)
2049 if (cpu_is_omap34xx())
2051 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
2052 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
2053 for (i = min; i < gpio_bank_count; i++) {
2054 struct gpio_bank *bank = &gpio_bank[i];
2057 if (!(bank->enabled_non_wakeup_gpios))
2060 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2061 bank->saved_datain = __raw_readl(bank->base +
2062 OMAP24XX_GPIO_DATAIN);
2063 l1 = __raw_readl(bank->base +
2064 OMAP24XX_GPIO_FALLINGDETECT);
2065 l2 = __raw_readl(bank->base +
2066 OMAP24XX_GPIO_RISINGDETECT);
2069 if (cpu_is_omap44xx()) {
2070 bank->saved_datain = __raw_readl(bank->base +
2072 l1 = __raw_readl(bank->base +
2073 OMAP4_GPIO_FALLINGDETECT);
2074 l2 = __raw_readl(bank->base +
2075 OMAP4_GPIO_RISINGDETECT);
2078 bank->saved_fallingdetect = l1;
2079 bank->saved_risingdetect = l2;
2080 l1 &= ~bank->enabled_non_wakeup_gpios;
2081 l2 &= ~bank->enabled_non_wakeup_gpios;
2083 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2084 __raw_writel(l1, bank->base +
2085 OMAP24XX_GPIO_FALLINGDETECT);
2086 __raw_writel(l2, bank->base +
2087 OMAP24XX_GPIO_RISINGDETECT);
2090 if (cpu_is_omap44xx()) {
2091 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2092 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2098 workaround_enabled = 0;
2101 workaround_enabled = 1;
2104 void omap2_gpio_resume_after_retention(void)
2109 if (!workaround_enabled)
2111 if (cpu_is_omap34xx())
2113 for (i = min; i < gpio_bank_count; i++) {
2114 struct gpio_bank *bank = &gpio_bank[i];
2115 u32 l, gen, gen0, gen1;
2117 if (!(bank->enabled_non_wakeup_gpios))
2120 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2121 __raw_writel(bank->saved_fallingdetect,
2122 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2123 __raw_writel(bank->saved_risingdetect,
2124 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2125 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2128 if (cpu_is_omap44xx()) {
2129 __raw_writel(bank->saved_fallingdetect,
2130 bank->base + OMAP4_GPIO_FALLINGDETECT);
2131 __raw_writel(bank->saved_risingdetect,
2132 bank->base + OMAP4_GPIO_RISINGDETECT);
2133 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2136 /* Check if any of the non-wakeup interrupt GPIOs have changed
2137 * state. If so, generate an IRQ by software. This is
2138 * horribly racy, but it's the best we can do to work around
2139 * this silicon bug. */
2140 l ^= bank->saved_datain;
2141 l &= bank->enabled_non_wakeup_gpios;
2144 * No need to generate IRQs for the rising edge for gpio IRQs
2145 * configured with falling edge only; and vice versa.
2147 gen0 = l & bank->saved_fallingdetect;
2148 gen0 &= bank->saved_datain;
2150 gen1 = l & bank->saved_risingdetect;
2151 gen1 &= ~(bank->saved_datain);
2153 /* FIXME: Consider GPIO IRQs with level detections properly! */
2154 gen = l & (~(bank->saved_fallingdetect) &
2155 ~(bank->saved_risingdetect));
2156 /* Consider all GPIO IRQs needed to be updated */
2162 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
2163 old0 = __raw_readl(bank->base +
2164 OMAP24XX_GPIO_LEVELDETECT0);
2165 old1 = __raw_readl(bank->base +
2166 OMAP24XX_GPIO_LEVELDETECT1);
2167 __raw_writel(old0 | gen, bank->base +
2168 OMAP24XX_GPIO_LEVELDETECT0);
2169 __raw_writel(old1 | gen, bank->base +
2170 OMAP24XX_GPIO_LEVELDETECT1);
2171 __raw_writel(old0, bank->base +
2172 OMAP24XX_GPIO_LEVELDETECT0);
2173 __raw_writel(old1, bank->base +
2174 OMAP24XX_GPIO_LEVELDETECT1);
2177 if (cpu_is_omap44xx()) {
2178 old0 = __raw_readl(bank->base +
2179 OMAP4_GPIO_LEVELDETECT0);
2180 old1 = __raw_readl(bank->base +
2181 OMAP4_GPIO_LEVELDETECT1);
2182 __raw_writel(old0 | l, bank->base +
2183 OMAP4_GPIO_LEVELDETECT0);
2184 __raw_writel(old1 | l, bank->base +
2185 OMAP4_GPIO_LEVELDETECT1);
2186 __raw_writel(old0, bank->base +
2187 OMAP4_GPIO_LEVELDETECT0);
2188 __raw_writel(old1, bank->base +
2189 OMAP4_GPIO_LEVELDETECT1);
2198 #ifdef CONFIG_ARCH_OMAP3
2199 /* save the registers of bank 2-6 */
2200 void omap_gpio_save_context(void)
2204 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2205 for (i = 1; i < gpio_bank_count; i++) {
2206 struct gpio_bank *bank = &gpio_bank[i];
2207 gpio_context[i].sysconfig =
2208 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2209 gpio_context[i].irqenable1 =
2210 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2211 gpio_context[i].irqenable2 =
2212 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2213 gpio_context[i].wake_en =
2214 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2215 gpio_context[i].ctrl =
2216 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2217 gpio_context[i].oe =
2218 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2219 gpio_context[i].leveldetect0 =
2220 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2221 gpio_context[i].leveldetect1 =
2222 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2223 gpio_context[i].risingdetect =
2224 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2225 gpio_context[i].fallingdetect =
2226 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2227 gpio_context[i].dataout =
2228 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2229 gpio_context[i].setwkuena =
2230 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2231 gpio_context[i].setdataout =
2232 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2236 /* restore the required registers of bank 2-6 */
2237 void omap_gpio_restore_context(void)
2241 for (i = 1; i < gpio_bank_count; i++) {
2242 struct gpio_bank *bank = &gpio_bank[i];
2243 __raw_writel(gpio_context[i].sysconfig,
2244 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2245 __raw_writel(gpio_context[i].irqenable1,
2246 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2247 __raw_writel(gpio_context[i].irqenable2,
2248 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2249 __raw_writel(gpio_context[i].wake_en,
2250 bank->base + OMAP24XX_GPIO_WAKE_EN);
2251 __raw_writel(gpio_context[i].ctrl,
2252 bank->base + OMAP24XX_GPIO_CTRL);
2253 __raw_writel(gpio_context[i].oe,
2254 bank->base + OMAP24XX_GPIO_OE);
2255 __raw_writel(gpio_context[i].leveldetect0,
2256 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2257 __raw_writel(gpio_context[i].leveldetect1,
2258 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2259 __raw_writel(gpio_context[i].risingdetect,
2260 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2261 __raw_writel(gpio_context[i].fallingdetect,
2262 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2263 __raw_writel(gpio_context[i].dataout,
2264 bank->base + OMAP24XX_GPIO_DATAOUT);
2265 __raw_writel(gpio_context[i].setwkuena,
2266 bank->base + OMAP24XX_GPIO_SETWKUENA);
2267 __raw_writel(gpio_context[i].setdataout,
2268 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2274 * This may get called early from board specific init
2275 * for boards that have interrupts routed via FPGA.
2277 int __init omap_gpio_init(void)
2280 return _omap_gpio_init();
2285 static int __init omap_gpio_sysinit(void)
2290 ret = _omap_gpio_init();
2294 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2295 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2297 ret = sysdev_class_register(&omap_gpio_sysclass);
2299 ret = sysdev_register(&omap_gpio_device);
2307 arch_initcall(omap_gpio_sysinit);
2310 #ifdef CONFIG_DEBUG_FS
2312 #include <linux/debugfs.h>
2313 #include <linux/seq_file.h>
2315 static int dbg_gpio_show(struct seq_file *s, void *unused)
2317 unsigned i, j, gpio;
2319 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2320 struct gpio_bank *bank = gpio_bank + i;
2321 unsigned bankwidth = 16;
2324 if (bank_is_mpuio(bank))
2325 gpio = OMAP_MPUIO(0);
2326 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2329 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2330 unsigned irq, value, is_in, irqstat;
2333 label = gpiochip_is_requested(&bank->chip, j);
2337 irq = bank->virtual_irq_start + j;
2338 value = gpio_get_value(gpio);
2339 is_in = gpio_is_input(bank, mask);
2341 if (bank_is_mpuio(bank))
2342 seq_printf(s, "MPUIO %2d ", j);
2344 seq_printf(s, "GPIO %3d ", gpio);
2345 seq_printf(s, "(%-20.20s): %s %s",
2347 is_in ? "in " : "out",
2348 value ? "hi" : "lo");
2350 /* FIXME for at least omap2, show pullup/pulldown state */
2352 irqstat = irq_desc[irq].status;
2353 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2354 if (is_in && ((bank->suspend_wakeup & mask)
2355 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2356 char *trigger = NULL;
2358 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2359 case IRQ_TYPE_EDGE_FALLING:
2360 trigger = "falling";
2362 case IRQ_TYPE_EDGE_RISING:
2365 case IRQ_TYPE_EDGE_BOTH:
2366 trigger = "bothedge";
2368 case IRQ_TYPE_LEVEL_LOW:
2371 case IRQ_TYPE_LEVEL_HIGH:
2378 seq_printf(s, ", irq-%d %-8s%s",
2380 (bank->suspend_wakeup & mask)
2384 seq_printf(s, "\n");
2387 if (bank_is_mpuio(bank)) {
2388 seq_printf(s, "\n");
2395 static int dbg_gpio_open(struct inode *inode, struct file *file)
2397 return single_open(file, dbg_gpio_show, &inode->i_private);
2400 static const struct file_operations debug_fops = {
2401 .open = dbg_gpio_open,
2403 .llseek = seq_lseek,
2404 .release = single_release,
2407 static int __init omap_gpio_debuginit(void)
2409 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2410 NULL, NULL, &debug_fops);
2413 late_initcall(omap_gpio_debuginit);