2 * linux/arch/arm/plat-omap/dmtimer.c
4 * OMAP Dual-Mode Timers
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Tarun Kanti DebBarma <tarun.kanti@ti.com>
8 * Thara Gopinath <thara@ti.com>
10 * dmtimer adaptation to platform_driver.
12 * Copyright (C) 2005 Nokia Corporation
13 * OMAP2 support by Juha Yrjola
14 * API improvements and OMAP2 clock framework support by Timo Teras
16 * Copyright (C) 2009 Texas Instruments
17 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 #include <linux/clk.h>
39 #include <linux/module.h>
41 #include <linux/device.h>
42 #include <linux/err.h>
43 #include <linux/pm_runtime.h>
45 #include <linux/of_device.h>
46 #include <linux/platform_device.h>
47 #include <linux/platform_data/dmtimer-omap.h>
49 #include <plat/dmtimer.h>
51 static u32 omap_reserved_systimers;
52 static LIST_HEAD(omap_timer_list);
53 static DEFINE_SPINLOCK(dm_timer_lock);
56 * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
57 * @timer: timer pointer over which read operation to perform
58 * @reg: lowest byte holds the register offset
60 * The posted mode bit is encoded in reg. Note that in posted mode write
61 * pending bit must be checked. Otherwise a read of a non completed write
62 * will produce an error.
64 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
66 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
67 return __omap_dm_timer_read(timer, reg, timer->posted);
71 * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
72 * @timer: timer pointer over which write operation is to perform
73 * @reg: lowest byte holds the register offset
74 * @value: data to write into the register
76 * The posted mode bit is encoded in reg. Note that in posted mode the write
77 * pending bit must be checked. Otherwise a write on a register which has a
78 * pending write will be lost.
80 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
83 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
84 __omap_dm_timer_write(timer, reg, value, timer->posted);
87 static void omap_timer_restore_context(struct omap_dm_timer *timer)
89 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
91 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
93 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
95 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
97 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
98 timer->context.tsicr);
99 __raw_writel(timer->context.tier, timer->irq_ena);
100 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
101 timer->context.tclr);
104 static int omap_dm_timer_reset(struct omap_dm_timer *timer)
106 u32 l, timeout = 100000;
108 if (timer->revision != 1)
111 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
114 l = __omap_dm_timer_read(timer,
115 OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
116 } while (!l && timeout--);
119 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
123 /* Configure timer for smart-idle mode */
124 l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
126 __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
133 static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
138 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
139 * do not call clk_get() for these devices.
141 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
142 timer->fclk = clk_get(&timer->pdev->dev, "fck");
143 if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
145 dev_err(&timer->pdev->dev, ": No fclk handle.\n");
150 omap_dm_timer_enable(timer);
152 if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
153 rc = omap_dm_timer_reset(timer);
155 omap_dm_timer_disable(timer);
160 __omap_dm_timer_enable_posted(timer);
161 omap_dm_timer_disable(timer);
163 return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
166 static inline u32 omap_dm_timer_reserved_systimer(int id)
168 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
171 int omap_dm_timer_reserve_systimer(int id)
173 if (omap_dm_timer_reserved_systimer(id))
176 omap_reserved_systimers |= (1 << (id - 1));
181 struct omap_dm_timer *omap_dm_timer_request(void)
183 struct omap_dm_timer *timer = NULL, *t;
187 spin_lock_irqsave(&dm_timer_lock, flags);
188 list_for_each_entry(t, &omap_timer_list, node) {
196 spin_unlock_irqrestore(&dm_timer_lock, flags);
199 ret = omap_dm_timer_prepare(timer);
207 pr_debug("%s: timer request failed!\n", __func__);
211 EXPORT_SYMBOL_GPL(omap_dm_timer_request);
213 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
215 struct omap_dm_timer *timer = NULL, *t;
219 /* Requesting timer by ID is not supported when device tree is used */
220 if (of_have_populated_dt()) {
221 pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n",
226 spin_lock_irqsave(&dm_timer_lock, flags);
227 list_for_each_entry(t, &omap_timer_list, node) {
228 if (t->pdev->id == id && !t->reserved) {
234 spin_unlock_irqrestore(&dm_timer_lock, flags);
237 ret = omap_dm_timer_prepare(timer);
245 pr_debug("%s: timer%d request failed!\n", __func__, id);
249 EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
252 * omap_dm_timer_request_by_cap - Request a timer by capability
253 * @cap: Bit mask of capabilities to match
255 * Find a timer based upon capabilities bit mask. Callers of this function
256 * should use the definitions found in the plat/dmtimer.h file under the
257 * comment "timer capabilities used in hwmod database". Returns pointer to
258 * timer handle on success and a NULL pointer on failure.
260 struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
262 struct omap_dm_timer *timer = NULL, *t;
268 spin_lock_irqsave(&dm_timer_lock, flags);
269 list_for_each_entry(t, &omap_timer_list, node) {
270 if ((!t->reserved) && ((t->capability & cap) == cap)) {
272 * If timer is not NULL, we have already found one timer
273 * but it was not an exact match because it had more
274 * capabilites that what was required. Therefore,
275 * unreserve the last timer found and see if this one
284 /* Exit loop early if we find an exact match */
285 if (t->capability == cap)
289 spin_unlock_irqrestore(&dm_timer_lock, flags);
291 if (timer && omap_dm_timer_prepare(timer)) {
297 pr_debug("%s: timer request failed!\n", __func__);
301 EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
303 int omap_dm_timer_free(struct omap_dm_timer *timer)
305 if (unlikely(!timer))
308 clk_put(timer->fclk);
310 WARN_ON(!timer->reserved);
314 EXPORT_SYMBOL_GPL(omap_dm_timer_free);
316 void omap_dm_timer_enable(struct omap_dm_timer *timer)
318 pm_runtime_get_sync(&timer->pdev->dev);
320 EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
322 void omap_dm_timer_disable(struct omap_dm_timer *timer)
324 pm_runtime_put_sync(&timer->pdev->dev);
326 EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
328 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
334 EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
336 #if defined(CONFIG_ARCH_OMAP1)
337 #include <mach/hardware.h>
339 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
340 * @inputmask: current value of idlect mask
342 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
345 struct omap_dm_timer *timer = NULL;
348 /* If ARMXOR cannot be idled this function call is unnecessary */
349 if (!(inputmask & (1 << 1)))
352 /* If any active timer is using ARMXOR return modified mask */
353 spin_lock_irqsave(&dm_timer_lock, flags);
354 list_for_each_entry(timer, &omap_timer_list, node) {
357 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
358 if (l & OMAP_TIMER_CTRL_ST) {
359 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
360 inputmask &= ~(1 << 1);
362 inputmask &= ~(1 << 2);
366 spin_unlock_irqrestore(&dm_timer_lock, flags);
370 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
374 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
380 EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
382 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
388 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
392 int omap_dm_timer_trigger(struct omap_dm_timer *timer)
394 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
395 pr_err("%s: timer not available or enabled.\n", __func__);
399 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
402 EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
404 int omap_dm_timer_start(struct omap_dm_timer *timer)
408 if (unlikely(!timer))
411 omap_dm_timer_enable(timer);
413 if (!(timer->capability & OMAP_TIMER_ALWON)) {
414 if (timer->get_context_loss_count &&
415 timer->get_context_loss_count(&timer->pdev->dev) !=
416 timer->ctx_loss_count)
417 omap_timer_restore_context(timer);
420 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
421 if (!(l & OMAP_TIMER_CTRL_ST)) {
422 l |= OMAP_TIMER_CTRL_ST;
423 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
426 /* Save the context */
427 timer->context.tclr = l;
430 EXPORT_SYMBOL_GPL(omap_dm_timer_start);
432 int omap_dm_timer_stop(struct omap_dm_timer *timer)
434 unsigned long rate = 0;
436 if (unlikely(!timer))
439 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
440 rate = clk_get_rate(timer->fclk);
442 __omap_dm_timer_stop(timer, timer->posted, rate);
444 if (!(timer->capability & OMAP_TIMER_ALWON)) {
445 if (timer->get_context_loss_count)
446 timer->ctx_loss_count =
447 timer->get_context_loss_count(&timer->pdev->dev);
451 * Since the register values are computed and written within
452 * __omap_dm_timer_stop, we need to use read to retrieve the
455 timer->context.tclr =
456 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
457 omap_dm_timer_disable(timer);
460 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
462 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
465 char *parent_name = NULL;
467 struct dmtimer_platform_data *pdata;
469 if (unlikely(!timer))
472 pdata = timer->pdev->dev.platform_data;
474 if (source < 0 || source >= 3)
478 * FIXME: Used for OMAP1 devices only because they do not currently
479 * use the clock framework to set the parent clock. To be removed
480 * once OMAP1 migrated to using clock framework for dmtimers
482 if (pdata && pdata->set_timer_src)
483 return pdata->set_timer_src(timer->pdev, source);
489 case OMAP_TIMER_SRC_SYS_CLK:
490 parent_name = "timer_sys_ck";
493 case OMAP_TIMER_SRC_32_KHZ:
494 parent_name = "timer_32k_ck";
497 case OMAP_TIMER_SRC_EXT_CLK:
498 parent_name = "timer_ext_ck";
502 parent = clk_get(&timer->pdev->dev, parent_name);
503 if (IS_ERR_OR_NULL(parent)) {
504 pr_err("%s: %s not found\n", __func__, parent_name);
508 ret = clk_set_parent(timer->fclk, parent);
509 if (IS_ERR_VALUE(ret))
510 pr_err("%s: failed to set %s as parent\n", __func__,
517 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
519 int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
524 if (unlikely(!timer))
527 omap_dm_timer_enable(timer);
528 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
530 l |= OMAP_TIMER_CTRL_AR;
532 l &= ~OMAP_TIMER_CTRL_AR;
533 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
534 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
536 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
537 /* Save the context */
538 timer->context.tclr = l;
539 timer->context.tldr = load;
540 omap_dm_timer_disable(timer);
543 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
545 /* Optimized set_load which removes costly spin wait in timer_start */
546 int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
551 if (unlikely(!timer))
554 omap_dm_timer_enable(timer);
556 if (!(timer->capability & OMAP_TIMER_ALWON)) {
557 if (timer->get_context_loss_count &&
558 timer->get_context_loss_count(&timer->pdev->dev) !=
559 timer->ctx_loss_count)
560 omap_timer_restore_context(timer);
563 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
565 l |= OMAP_TIMER_CTRL_AR;
566 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
568 l &= ~OMAP_TIMER_CTRL_AR;
570 l |= OMAP_TIMER_CTRL_ST;
572 __omap_dm_timer_load_start(timer, l, load, timer->posted);
574 /* Save the context */
575 timer->context.tclr = l;
576 timer->context.tldr = load;
577 timer->context.tcrr = load;
580 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
582 int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
587 if (unlikely(!timer))
590 omap_dm_timer_enable(timer);
591 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
593 l |= OMAP_TIMER_CTRL_CE;
595 l &= ~OMAP_TIMER_CTRL_CE;
596 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
597 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
599 /* Save the context */
600 timer->context.tclr = l;
601 timer->context.tmar = match;
602 omap_dm_timer_disable(timer);
605 EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
607 int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
608 int toggle, int trigger)
612 if (unlikely(!timer))
615 omap_dm_timer_enable(timer);
616 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
617 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
618 OMAP_TIMER_CTRL_PT | (0x03 << 10));
620 l |= OMAP_TIMER_CTRL_SCPWM;
622 l |= OMAP_TIMER_CTRL_PT;
624 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
626 /* Save the context */
627 timer->context.tclr = l;
628 omap_dm_timer_disable(timer);
631 EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
633 int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
637 if (unlikely(!timer))
640 omap_dm_timer_enable(timer);
641 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
642 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
643 if (prescaler >= 0x00 && prescaler <= 0x07) {
644 l |= OMAP_TIMER_CTRL_PRE;
647 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
649 /* Save the context */
650 timer->context.tclr = l;
651 omap_dm_timer_disable(timer);
654 EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
656 int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
659 if (unlikely(!timer))
662 omap_dm_timer_enable(timer);
663 __omap_dm_timer_int_enable(timer, value);
665 /* Save the context */
666 timer->context.tier = value;
667 timer->context.twer = value;
668 omap_dm_timer_disable(timer);
671 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
674 * omap_dm_timer_set_int_disable - disable timer interrupts
675 * @timer: pointer to timer handle
676 * @mask: bit mask of interrupts to be disabled
678 * Disables the specified timer interrupts for a timer.
680 int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
684 if (unlikely(!timer))
687 omap_dm_timer_enable(timer);
689 if (timer->revision == 1)
690 l = __raw_readl(timer->irq_ena) & ~mask;
692 __raw_writel(l, timer->irq_dis);
693 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
694 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
696 /* Save the context */
697 timer->context.tier &= ~mask;
698 timer->context.twer &= ~mask;
699 omap_dm_timer_disable(timer);
702 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);
704 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
708 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
709 pr_err("%s: timer not available or enabled.\n", __func__);
713 l = __raw_readl(timer->irq_stat);
717 EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
719 int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
721 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
724 __omap_dm_timer_write_status(timer, value);
728 EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
730 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
732 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
733 pr_err("%s: timer not iavailable or enabled.\n", __func__);
737 return __omap_dm_timer_read_counter(timer, timer->posted);
739 EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
741 int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
743 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
744 pr_err("%s: timer not available or enabled.\n", __func__);
748 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
750 /* Save the context */
751 timer->context.tcrr = value;
754 EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
756 int omap_dm_timers_active(void)
758 struct omap_dm_timer *timer;
760 list_for_each_entry(timer, &omap_timer_list, node) {
761 if (!timer->reserved)
764 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
765 OMAP_TIMER_CTRL_ST) {
771 EXPORT_SYMBOL_GPL(omap_dm_timers_active);
774 * omap_dm_timer_probe - probe function called for every registered device
775 * @pdev: pointer to current timer platform device
777 * Called by driver framework at the end of device registration for all
780 static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
783 struct omap_dm_timer *timer;
784 struct resource *mem, *irq;
785 struct device *dev = &pdev->dev;
786 struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
788 if (!pdata && !dev->of_node) {
789 dev_err(dev, "%s: no platform data.\n", __func__);
793 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
794 if (unlikely(!irq)) {
795 dev_err(dev, "%s: no IRQ resource.\n", __func__);
799 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
800 if (unlikely(!mem)) {
801 dev_err(dev, "%s: no memory resource.\n", __func__);
805 timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL);
807 dev_err(dev, "%s: memory alloc failed!\n", __func__);
811 timer->io_base = devm_request_and_ioremap(dev, mem);
812 if (!timer->io_base) {
813 dev_err(dev, "%s: region already claimed.\n", __func__);
818 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
819 timer->capability |= OMAP_TIMER_ALWON;
820 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
821 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
822 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
823 timer->capability |= OMAP_TIMER_HAS_PWM;
824 if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
825 timer->capability |= OMAP_TIMER_SECURE;
827 timer->id = pdev->id;
828 timer->errata = pdata->timer_errata;
829 timer->capability = pdata->timer_capability;
830 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
831 timer->get_context_loss_count = pdata->get_context_loss_count;
834 timer->irq = irq->start;
837 /* Skip pm_runtime_enable for OMAP1 */
838 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
839 pm_runtime_enable(dev);
840 pm_runtime_irq_safe(dev);
843 if (!timer->reserved) {
844 pm_runtime_get_sync(dev);
845 __omap_dm_timer_init_regs(timer);
849 /* add the timer element to the list */
850 spin_lock_irqsave(&dm_timer_lock, flags);
851 list_add_tail(&timer->node, &omap_timer_list);
852 spin_unlock_irqrestore(&dm_timer_lock, flags);
854 dev_dbg(dev, "Device Probed.\n");
860 * omap_dm_timer_remove - cleanup a registered timer device
861 * @pdev: pointer to current timer platform device
863 * Called by driver framework whenever a timer device is unregistered.
864 * In addition to freeing platform resources it also deletes the timer
865 * entry from the local list.
867 static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
869 struct omap_dm_timer *timer;
873 spin_lock_irqsave(&dm_timer_lock, flags);
874 list_for_each_entry(timer, &omap_timer_list, node)
875 if (!strcmp(dev_name(&timer->pdev->dev),
876 dev_name(&pdev->dev))) {
877 list_del(&timer->node);
881 spin_unlock_irqrestore(&dm_timer_lock, flags);
886 static const struct of_device_id omap_timer_match[] = {
887 { .compatible = "ti,omap2-timer", },
890 MODULE_DEVICE_TABLE(of, omap_timer_match);
892 static struct platform_driver omap_dm_timer_driver = {
893 .probe = omap_dm_timer_probe,
894 .remove = __devexit_p(omap_dm_timer_remove),
896 .name = "omap_timer",
897 .of_match_table = of_match_ptr(omap_timer_match),
901 early_platform_init("earlytimer", &omap_dm_timer_driver);
902 module_platform_driver(omap_dm_timer_driver);
904 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
905 MODULE_LICENSE("GPL");
906 MODULE_ALIAS("platform:" DRIVER_NAME);
907 MODULE_AUTHOR("Texas Instruments Inc");