2 * OMAP 32ksynctimer/counter_32k-related code
4 * Copyright (C) 2009 Texas Instruments
5 * Copyright (C) 2010 Nokia Corporation
6 * Tony Lindgren <tony@atomide.com>
7 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
20 #include <linux/clocksource.h>
22 #include <asm/mach/time.h>
23 #include <asm/sched_clock.h>
25 #include <plat/common.h>
26 #include <plat/clock.h>
28 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
29 #define OMAP2_32KSYNCNT_REV_OFF 0x0
30 #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
31 #define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
32 #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
35 * 32KHz clocksource ... always available, on pretty most chips except
36 * OMAP 730 and 1510. Other timers could be used as clocksources, with
37 * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
38 * but systems won't necessarily want to spend resources that way.
40 static void __iomem *sync32k_cnt_reg;
42 static u32 notrace omap_32k_read_sched_clock(void)
44 return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
48 * omap_read_persistent_clock - Return time from a persistent clock.
50 * Reads the time from a source which isn't disabled during PM, the
51 * 32k sync timer. Convert the cycles elapsed since last read into
52 * nsecs and adds to a monotonically increasing timespec.
54 static struct timespec persistent_ts;
55 static cycles_t cycles;
56 static unsigned int persistent_mult, persistent_shift;
57 static DEFINE_SPINLOCK(read_persistent_clock_lock);
59 static void omap_read_persistent_clock(struct timespec *ts)
61 unsigned long long nsecs;
65 spin_lock_irqsave(&read_persistent_clock_lock, flags);
68 cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
70 nsecs = clocksource_cyc2ns(cycles - last_cycles,
71 persistent_mult, persistent_shift);
73 timespec_add_ns(&persistent_ts, nsecs);
77 spin_unlock_irqrestore(&read_persistent_clock_lock, flags);
81 * omap_init_clocksource_32k - setup and register counter 32k as a
83 * @pbase: base addr of counter_32k module
84 * @size: size of counter_32k to map
86 * Returns 0 upon success or negative error code upon failure.
89 int __init omap_init_clocksource_32k(void __iomem *vbase)
94 * 32k sync Counter IP register offsets vary between the
95 * highlander version and the legacy ones.
96 * The 'SCHEME' bits(30-31) of the revision register is used
97 * to identify the version.
99 if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
100 OMAP2_32KSYNCNT_REV_SCHEME)
101 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
103 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
106 * 120000 rough estimate from the calculations in
107 * __clocksource_updatefreq_scale.
109 clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
110 32768, NSEC_PER_SEC, 120000);
112 ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
113 250, 32, clocksource_mmio_readl_up);
115 pr_err("32k_counter: can't register clocksource\n");
119 setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
120 register_persistent_clock(NULL, omap_read_persistent_clock);
121 pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");