2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
12 #include <linux/dmaengine.h>
13 #include <linux/workqueue.h>
14 #include <linux/interrupt.h>
16 /* dev types for memcpy */
17 #define STEDMA40_DEV_DST_MEMORY (-1)
18 #define STEDMA40_DEV_SRC_MEMORY (-1)
21 STEDMA40_MODE_LOGICAL = 0,
22 STEDMA40_MODE_PHYSICAL,
23 STEDMA40_MODE_OPERATION,
26 enum stedma40_mode_opt {
27 STEDMA40_PCHAN_BASIC_MODE = 0,
28 STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
29 STEDMA40_PCHAN_MODULO_MODE,
30 STEDMA40_PCHAN_DOUBLE_DST_MODE,
31 STEDMA40_LCHAN_SRC_PHY_DST_LOG,
32 STEDMA40_LCHAN_SRC_LOG_DST_PHY,
35 #define STEDMA40_ESIZE_8_BIT 0x0
36 #define STEDMA40_ESIZE_16_BIT 0x1
37 #define STEDMA40_ESIZE_32_BIT 0x2
38 #define STEDMA40_ESIZE_64_BIT 0x3
40 /* The value 4 indicates that PEN-reg shall be set to 0 */
41 #define STEDMA40_PSIZE_PHY_1 0x4
42 #define STEDMA40_PSIZE_PHY_2 0x0
43 #define STEDMA40_PSIZE_PHY_4 0x1
44 #define STEDMA40_PSIZE_PHY_8 0x2
45 #define STEDMA40_PSIZE_PHY_16 0x3
48 * The number of elements differ in logical and
51 #define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
52 #define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
53 #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
54 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
56 /* Maximum number of possible physical channels */
57 #define STEDMA40_MAX_PHYS 32
59 enum stedma40_flow_ctrl {
60 STEDMA40_NO_FLOW_CTRL,
64 enum stedma40_periph_data_width {
65 STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
66 STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
67 STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
68 STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
71 enum stedma40_xfer_dir {
72 STEDMA40_MEM_TO_MEM = 1,
73 STEDMA40_MEM_TO_PERIPH,
74 STEDMA40_PERIPH_TO_MEM,
75 STEDMA40_PERIPH_TO_PERIPH
80 * struct stedma40_chan_cfg - dst/src channel configuration
82 * @big_endian: true if the src/dst should be read as big endian
83 * @data_width: Data width of the src/dst hardware
85 * @flow_ctrl: Flow control on/off.
87 struct stedma40_half_channel_info {
89 enum stedma40_periph_data_width data_width;
91 enum stedma40_flow_ctrl flow_ctrl;
95 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
97 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
98 * @high_priority: true if high-priority
99 * @mode: channel mode: physical, logical, or operation
100 * @mode_opt: options for the chosen channel mode
101 * @src_dev_type: Src device type
102 * @dst_dev_type: Dst device type
103 * @src_info: Parameters for dst half channel
104 * @dst_info: Parameters for dst half channel
107 * This structure has to be filled by the client drivers.
108 * It is recommended to do all dma configurations for clients in the machine.
111 struct stedma40_chan_cfg {
112 enum stedma40_xfer_dir dir;
114 enum stedma40_mode mode;
115 enum stedma40_mode_opt mode_opt;
118 struct stedma40_half_channel_info src_info;
119 struct stedma40_half_channel_info dst_info;
123 * struct stedma40_platform_data - Configuration struct for the dma device.
125 * @dev_len: length of dev_tx and dev_rx
126 * @dev_tx: mapping between destination event line and io address
127 * @dev_rx: mapping between source event line and io address
128 * @memcpy: list of memcpy event lines
129 * @memcpy_len: length of memcpy
130 * @memcpy_conf_phy: default configuration of physical channel memcpy
131 * @memcpy_conf_log: default configuration of logical channel memcpy
132 * @disabled_channels: A vector, ending with -1, that marks physical channels
133 * that are for different reasons not available for the driver.
135 struct stedma40_platform_data {
137 const dma_addr_t *dev_tx;
138 const dma_addr_t *dev_rx;
141 struct stedma40_chan_cfg *memcpy_conf_phy;
142 struct stedma40_chan_cfg *memcpy_conf_log;
143 int disabled_channels[STEDMA40_MAX_PHYS];
146 #ifdef CONFIG_STE_DMA40
149 * stedma40_filter() - Provides stedma40_chan_cfg to the
150 * ste_dma40 dma driver via the dmaengine framework.
151 * does some checking of what's provided.
153 * Never directly called by client. It used by dmaengine.
154 * @chan: dmaengine handle.
155 * @data: Must be of type: struct stedma40_chan_cfg and is
156 * the configuration of the framework.
161 bool stedma40_filter(struct dma_chan *chan, void *data);
164 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
165 * scattergatter lists.
167 * @chan: dmaengine handle
168 * @sgl_dst: Destination scatter list
169 * @sgl_src: Source scatter list
170 * @sgl_len: The length of each scatterlist. Both lists must be of equal length
171 * and each element must match the corresponding element in the other scatter
173 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
176 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
177 struct scatterlist *sgl_dst,
178 struct scatterlist *sgl_src,
179 unsigned int sgl_len,
180 unsigned long flags);
183 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
186 * @chan: dmaengine handle
187 * @addr: source or destination physicall address.
188 * @size: bytes to transfer
189 * @direction: direction of transfer
190 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
194 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
197 enum dma_data_direction direction,
200 struct scatterlist sg;
201 sg_init_table(&sg, 1);
202 sg.dma_address = addr;
205 return chan->device->device_prep_slave_sg(chan, &sg, 1,
210 static inline bool stedma40_filter(struct dma_chan *chan, void *data)
216 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
219 enum dma_data_direction direction,