2 * Copyright (C) 1997,1998 Russell King
3 * Copyright (C) 1999 ARM Limited
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #ifndef __ASM_ARCH_MXC_MX1_H__
13 #define __ASM_ARCH_MXC_MX1_H__
15 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
16 #error "Do not include directly."
19 #include <mach/vmalloc.h>
22 * defines the hardware clock tick rate
24 #define CLOCK_TICK_RATE 16000000
26 #define PHYS_OFFSET UL(0x08000000)
31 #define IMX_IO_PHYS 0x00200000
32 #define IMX_IO_SIZE 0x00100000
33 #define IMX_IO_BASE VMALLOC_END
35 #define IMX_CS0_PHYS 0x10000000
36 #define IMX_CS0_SIZE 0x02000000
38 #define IMX_CS1_PHYS 0x12000000
39 #define IMX_CS1_SIZE 0x01000000
41 #define IMX_CS2_PHYS 0x13000000
42 #define IMX_CS2_SIZE 0x01000000
44 #define IMX_CS3_PHYS 0x14000000
45 #define IMX_CS3_SIZE 0x01000000
47 #define IMX_CS4_PHYS 0x15000000
48 #define IMX_CS4_SIZE 0x01000000
50 #define IMX_CS5_PHYS 0x16000000
51 #define IMX_CS5_SIZE 0x01000000
54 * Register BASEs, based on OFFSETs
56 #define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS)
57 #define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS)
58 #define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS)
59 #define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS)
60 #define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS)
61 #define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS)
62 #define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS)
63 #define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS)
64 #define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS)
65 #define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS)
66 #define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS)
67 #define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS)
68 #define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS)
69 #define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS)
70 #define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS)
71 #define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS)
72 #define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS)
73 #define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS)
74 #define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS)
75 #define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS)
76 #define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS)
77 #define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS)
78 #define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS)
79 #define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS)
80 #define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS)
81 #define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS)
82 #define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS)
83 #define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS)
84 #define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS)
86 /* macro to get at IO space when running virtually */
87 #define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE)
89 /* define macros needed for entry-macro.S */
90 #define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
92 /* fixed interrput numbers */
95 #define DSPA_MAC_INT 7
99 #define GPIO_INT_PORTA 11
100 #define GPIO_INT_PORTB 12
101 #define GPIO_INT_PORTC 13
104 #define SIM_DATA_INT 16
106 #define RTC_SAMINT 18
107 #define UART2_MINT_PFERR 19
108 #define UART2_MINT_RTS 20
109 #define UART2_MINT_DTR 21
110 #define UART2_MINT_UARTC 22
111 #define UART2_MINT_TX 23
112 #define UART2_MINT_RX 24
113 #define UART1_MINT_PFERR 25
114 #define UART1_MINT_RTS 26
115 #define UART1_MINT_DTR 27
116 #define UART1_MINT_UARTC 28
117 #define UART1_MINT_TX 29
118 #define UART1_MINT_RX 30
119 #define VOICE_DAC_INT 31
120 #define VOICE_ADC_INT 32
121 #define PEN_DATA_INT 33
126 #define SSI_TX_INT 42
127 #define SSI_TX_ERR_INT 43
128 #define SSI_RX_INT 44
129 #define SSI_RX_ERR_INT 45
145 #define GPIO_INT_PORTD 62
148 #define MXC_MAX_INT_LINES 64
152 /* gpio and gpio based interrupt handling */
154 #define GPIO_GDIR 0x00
155 #define GPIO_PSR 0x24
156 #define GPIO_ICR1 0x28
157 #define GPIO_ICR2 0x2C
158 #define GPIO_IMR 0x30
159 #define GPIO_ISR 0x34
160 #define GPIO_INT_LOW_LEV 0x3
161 #define GPIO_INT_HIGH_LEV 0x2
162 #define GPIO_INT_RISE_EDGE 0x0
163 #define GPIO_INT_FALL_EDGE 0x1
164 #define GPIO_INT_NONE 0x4
167 #define DMA_REQ_UART3_T 2
168 #define DMA_REQ_UART3_R 3
169 #define DMA_REQ_SSI2_T 4
170 #define DMA_REQ_SSI2_R 5
171 #define DMA_REQ_CSI_STAT 6
172 #define DMA_REQ_CSI_R 7
173 #define DMA_REQ_MSHC 8
174 #define DMA_REQ_DSPA_DCT_DOUT 9
175 #define DMA_REQ_DSPA_DCT_DIN 10
176 #define DMA_REQ_DSPA_MAC 11
177 #define DMA_REQ_EXT 12
178 #define DMA_REQ_SDHC 13
179 #define DMA_REQ_SPI1_R 14
180 #define DMA_REQ_SPI1_T 15
181 #define DMA_REQ_SSI_T 16
182 #define DMA_REQ_SSI_R 17
183 #define DMA_REQ_ASP_DAC 18
184 #define DMA_REQ_ASP_ADC 19
185 #define DMA_REQ_USP_EP(x) (20 + (x))
186 #define DMA_REQ_SPI2_R 26
187 #define DMA_REQ_SPI2_T 27
188 #define DMA_REQ_UART2_T 28
189 #define DMA_REQ_UART2_R 29
190 #define DMA_REQ_UART1_T 30
191 #define DMA_REQ_UART1_R 31
193 /* mandatory for CONFIG_LL_DEBUG */
194 #define MXC_LL_UART_PADDR UART1_BASE_ADDR
195 #define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
197 #endif /* __ASM_ARCH_MXC_MX1_H__ */