arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18
  19 #include <asm/cputype.h>
  20 #include <asm/sections.h>
  21 #include <asm/cachetype.h>
  22 #include <asm/setup.h>
  23 #include <asm/sizes.h>
  24 #include <asm/smp_plat.h>
  25 #include <asm/tlb.h>
  26 #include <asm/highmem.h>
  27
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/map.h>
  30
  31 #include "mm.h"
  32
  33 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  34
  35 /*
  36  * empty_zero_page is a special page that is used for
  37  * zero-initialized data and COW.
  38  */
  39 struct page *empty_zero_page;
  40 EXPORT_SYMBOL(empty_zero_page);
  41
  42 /*
  43  * The pmd table for the upper-most set of pages.
  44  */
  45 pmd_t *top_pmd;
  46
  47 #define CPOLICY_UNCACHED        0
  48 #define CPOLICY_BUFFERED        1
  49 #define CPOLICY_WRITETHROUGH    2
  50 #define CPOLICY_WRITEBACK       3
  51 #define CPOLICY_WRITEALLOC      4
  52
  53 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  54 static unsigned int ecc_mask __initdata = 0;
  55 pgprot_t pgprot_user;
  56 pgprot_t pgprot_kernel;
  57
  58 EXPORT_SYMBOL(pgprot_user);
  59 EXPORT_SYMBOL(pgprot_kernel);
  60
  61 struct cachepolicy {
  62         const char      policy[16];
  63         unsigned int    cr_mask;
  64         unsigned int    pmd;
  65         pteval_t        pte;
  66 };
  67
  68 static struct cachepolicy cache_policies[] __initdata = {
  69         {
  70                 .policy         = "uncached",
  71                 .cr_mask        = CR_W|CR_C,
  72                 .pmd            = PMD_SECT_UNCACHED,
  73                 .pte            = L_PTE_MT_UNCACHED,
  74         }, {
  75                 .policy         = "buffered",
  76                 .cr_mask        = CR_C,
  77                 .pmd            = PMD_SECT_BUFFERED,
  78                 .pte            = L_PTE_MT_BUFFERABLE,
  79         }, {
  80                 .policy         = "writethrough",
  81                 .cr_mask        = 0,
  82                 .pmd            = PMD_SECT_WT,
  83                 .pte            = L_PTE_MT_WRITETHROUGH,
  84         }, {
  85                 .policy         = "writeback",
  86                 .cr_mask        = 0,
  87                 .pmd            = PMD_SECT_WB,
  88                 .pte            = L_PTE_MT_WRITEBACK,
  89         }, {
  90                 .policy         = "writealloc",
  91                 .cr_mask        = 0,
  92                 .pmd            = PMD_SECT_WBWA,
  93                 .pte            = L_PTE_MT_WRITEALLOC,
  94         }
  95 };
  96
  97 /*
  98  * These are useful for identifying cache coherency
  99  * problems by allowing the cache or the cache and
 100  * writebuffer to be turned off.  (Note: the write
 101  * buffer should not be on and the cache off).
 102  */
 103 static int __init early_cachepolicy(char *p)
 104 {
 105         int i;
 106
 107         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 108                 int len = strlen(cache_policies[i].policy);
 109
 110                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 111                         cachepolicy = i;
 112                         cr_alignment &= ~cache_policies[i].cr_mask;
 113                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 114                         break;
 115                 }
 116         }
 117         if (i == ARRAY_SIZE(cache_policies))
 118                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 119         /*
 120          * This restriction is partly to do with the way we boot; it is
 121          * unpredictable to have memory mapped using two different sets of
 122          * memory attributes (shared, type, and cache attribs).  We can not
 123          * change these attributes once the initial assembly has setup the
 124          * page tables.
 125          */
 126         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 127                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 128                 cachepolicy = CPOLICY_WRITEBACK;
 129         }
 130         flush_cache_all();
 131         set_cr(cr_alignment);
 132         return 0;
 133 }
 134 early_param("cachepolicy", early_cachepolicy);
 135
 136 static int __init early_nocache(char *__unused)
 137 {
 138         char *p = "buffered";
 139         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 140         early_cachepolicy(p);
 141         return 0;
 142 }
 143 early_param("nocache", early_nocache);
 144
 145 static int __init early_nowrite(char *__unused)
 146 {
 147         char *p = "uncached";
 148         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 149         early_cachepolicy(p);
 150         return 0;
 151 }
 152 early_param("nowb", early_nowrite);
 153
 154 static int __init early_ecc(char *p)
 155 {
 156         if (memcmp(p, "on", 2) == 0)
 157                 ecc_mask = PMD_PROTECTION;
 158         else if (memcmp(p, "off", 3) == 0)
 159                 ecc_mask = 0;
 160         return 0;
 161 }
 162 early_param("ecc", early_ecc);
 163
 164 static int __init noalign_setup(char *__unused)
 165 {
 166         cr_alignment &= ~CR_A;
 167         cr_no_alignment &= ~CR_A;
 168         set_cr(cr_alignment);
 169         return 1;
 170 }
 171 __setup("noalign", noalign_setup);
 172
 173 #ifndef CONFIG_SMP
 174 void adjust_cr(unsigned long mask, unsigned long set)
 175 {
 176         unsigned long flags;
 177
 178         mask &= ~CR_A;
 179
 180         set &= mask;
 181
 182         local_irq_save(flags);
 183
 184         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 185         cr_alignment = (cr_alignment & ~mask) | set;
 186
 187         set_cr((get_cr() & ~mask) | set);
 188
 189         local_irq_restore(flags);
 190 }
 191 #endif
 192
 193 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 194 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 195
 196 static struct mem_type mem_types[] = {
 197         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 198                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 199                                   L_PTE_SHARED,
 200                 .prot_l1        = PMD_TYPE_TABLE,
 201                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 202                 .domain         = DOMAIN_IO,
 203         },
 204         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 205                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 206                 .prot_l1        = PMD_TYPE_TABLE,
 207                 .prot_sect      = PROT_SECT_DEVICE,
 208                 .domain         = DOMAIN_IO,
 209         },
 210         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 211                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 212                 .prot_l1        = PMD_TYPE_TABLE,
 213                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 214                 .domain         = DOMAIN_IO,
 215         },
 216         [MT_DEVICE_WC] = {      /* ioremap_wc */
 217                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 218                 .prot_l1        = PMD_TYPE_TABLE,
 219                 .prot_sect      = PROT_SECT_DEVICE,
 220                 .domain         = DOMAIN_IO,
 221         },
 222         [MT_UNCACHED] = {
 223                 .prot_pte       = PROT_PTE_DEVICE,
 224                 .prot_l1        = PMD_TYPE_TABLE,
 225                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 226                 .domain         = DOMAIN_IO,
 227         },
 228         [MT_CACHECLEAN] = {
 229                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 230                 .domain    = DOMAIN_KERNEL,
 231         },
 232         [MT_MINICLEAN] = {
 233                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 234                 .domain    = DOMAIN_KERNEL,
 235         },
 236         [MT_LOW_VECTORS] = {
 237                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 238                                 L_PTE_RDONLY,
 239                 .prot_l1   = PMD_TYPE_TABLE,
 240                 .domain    = DOMAIN_USER,
 241         },
 242         [MT_HIGH_VECTORS] = {
 243                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 244                                 L_PTE_USER | L_PTE_RDONLY,
 245                 .prot_l1   = PMD_TYPE_TABLE,
 246                 .domain    = DOMAIN_USER,
 247         },
 248         [MT_MEMORY] = {
 249                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 250                 .prot_l1   = PMD_TYPE_TABLE,
 251                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 252                 .domain    = DOMAIN_KERNEL,
 253         },
 254         [MT_ROM] = {
 255                 .prot_sect = PMD_TYPE_SECT,
 256                 .domain    = DOMAIN_KERNEL,
 257         },
 258         [MT_MEMORY_NONCACHED] = {
 259                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 260                                 L_PTE_MT_BUFFERABLE,
 261                 .prot_l1   = PMD_TYPE_TABLE,
 262                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 263                 .domain    = DOMAIN_KERNEL,
 264         },
 265         [MT_MEMORY_DTCM] = {
 266                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 267                                 L_PTE_XN,
 268                 .prot_l1   = PMD_TYPE_TABLE,
 269                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 270                 .domain    = DOMAIN_KERNEL,
 271         },
 272         [MT_MEMORY_ITCM] = {
 273                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 274                 .prot_l1   = PMD_TYPE_TABLE,
 275                 .domain    = DOMAIN_KERNEL,
 276         },
 277 };
 278
 279 const struct mem_type *get_mem_type(unsigned int type)
 280 {
 281         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 282 }
 283 EXPORT_SYMBOL(get_mem_type);
 284
 285 /*
 286  * Adjust the PMD section entries according to the CPU in use.
 287  */
 288 static void __init build_mem_type_table(void)
 289 {
 290         struct cachepolicy *cp;
 291         unsigned int cr = get_cr();
 292         unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
 293         int cpu_arch = cpu_architecture();
 294         int i;
 295
 296         if (cpu_arch < CPU_ARCH_ARMv6) {
 297 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 298                 if (cachepolicy > CPOLICY_BUFFERED)
 299                         cachepolicy = CPOLICY_BUFFERED;
 300 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 301                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 302                         cachepolicy = CPOLICY_WRITETHROUGH;
 303 #endif
 304         }
 305         if (cpu_arch < CPU_ARCH_ARMv5) {
 306                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 307                         cachepolicy = CPOLICY_WRITEBACK;
 308                 ecc_mask = 0;
 309         }
 310         if (is_smp())
 311                 cachepolicy = CPOLICY_WRITEALLOC;
 312
 313         /*
 314          * Strip out features not present on earlier architectures.
 315          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 316          * without extended page tables don't have the 'Shared' bit.
 317          */
 318         if (cpu_arch < CPU_ARCH_ARMv5)
 319                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 320                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 321         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 322                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 323                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 324
 325         /*
 326          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 327          * "update-able on write" bit on ARM610).  However, Xscale and
 328          * Xscale3 require this bit to be cleared.
 329          */
 330         if (cpu_is_xscale() || cpu_is_xsc3()) {
 331                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 332                         mem_types[i].prot_sect &= ~PMD_BIT4;
 333                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 334                 }
 335         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 336                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 337                         if (mem_types[i].prot_l1)
 338                                 mem_types[i].prot_l1 |= PMD_BIT4;
 339                         if (mem_types[i].prot_sect)
 340                                 mem_types[i].prot_sect |= PMD_BIT4;
 341                 }
 342         }
 343
 344         /*
 345          * Mark the device areas according to the CPU/architecture.
 346          */
 347         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 348                 if (!cpu_is_xsc3()) {
 349                         /*
 350                          * Mark device regions on ARMv6+ as execute-never
 351                          * to prevent speculative instruction fetches.
 352                          */
 353                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 354                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 355                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 356                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 357                 }
 358                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 359                         /*
 360                          * For ARMv7 with TEX remapping,
 361                          * - shared device is SXCB=1100
 362                          * - nonshared device is SXCB=0100
 363                          * - write combine device mem is SXCB=0001
 364                          * (Uncached Normal memory)
 365                          */
 366                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 367                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 368                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 369                 } else if (cpu_is_xsc3()) {
 370                         /*
 371                          * For Xscale3,
 372                          * - shared device is TEXCB=00101
 373                          * - nonshared device is TEXCB=01000
 374                          * - write combine device mem is TEXCB=00100
 375                          * (Inner/Outer Uncacheable in xsc3 parlance)
 376                          */
 377                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 378                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 379                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 380                 } else {
 381                         /*
 382                          * For ARMv6 and ARMv7 without TEX remapping,
 383                          * - shared device is TEXCB=00001
 384                          * - nonshared device is TEXCB=01000
 385                          * - write combine device mem is TEXCB=00100
 386                          * (Uncached Normal in ARMv6 parlance).
 387                          */
 388                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 389                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 390                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 391                 }
 392         } else {
 393                 /*
 394                  * On others, write combining is "Uncached/Buffered"
 395                  */
 396                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 397         }
 398
 399         /*
 400          * Now deal with the memory-type mappings
 401          */
 402         cp = &cache_policies[cachepolicy];
 403         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 404
 405         /*
 406          * Only use write-through for non-SMP systems
 407          */
 408         if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 409                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
 410
 411         /*
 412          * Enable CPU-specific coherency if supported.
 413          * (Only available on XSC3 at the moment.)
 414          */
 415         if (arch_is_coherent() && cpu_is_xsc3()) {
 416                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 417                 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 418                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 419                 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 420         }
 421         /*
 422          * ARMv6 and above have extended page tables.
 423          */
 424         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 425                 /*
 426                  * Mark cache clean areas and XIP ROM read only
 427                  * from SVC mode and no access from userspace.
 428                  */
 429                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 430                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 431                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 432
 433                 if (is_smp()) {
 434                         /*
 435                          * Mark memory with the "shared" attribute
 436                          * for SMP systems
 437                          */
 438                         user_pgprot |= L_PTE_SHARED;
 439                         kern_pgprot |= L_PTE_SHARED;
 440                         vecs_pgprot |= L_PTE_SHARED;
 441                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 442                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 443                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 444                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 445                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 446                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 447                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 448                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 449                 }
 450         }
 451
 452         /*
 453          * Non-cacheable Normal - intended for memory areas that must
 454          * not cause dirty cache line writebacks when used
 455          */
 456         if (cpu_arch >= CPU_ARCH_ARMv6) {
 457                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 458                         /* Non-cacheable Normal is XCB = 001 */
 459                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 460                                 PMD_SECT_BUFFERED;
 461                 } else {
 462                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 463                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 464                                 PMD_SECT_TEX(1);
 465                 }
 466         } else {
 467                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 468         }
 469
 470         for (i = 0; i < 16; i++) {
 471                 unsigned long v = pgprot_val(protection_map[i]);
 472                 protection_map[i] = __pgprot(v | user_pgprot);
 473         }
 474
 475         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 476         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 477
 478         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 479         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 480                                  L_PTE_DIRTY | kern_pgprot);
 481
 482         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 483         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 484         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 485         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 486         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 487         mem_types[MT_ROM].prot_sect |= cp->pmd;
 488
 489         switch (cp->pmd) {
 490         case PMD_SECT_WT:
 491                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 492                 break;
 493         case PMD_SECT_WB:
 494         case PMD_SECT_WBWA:
 495                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 496                 break;
 497         }
 498         printk("Memory policy: ECC %sabled, Data cache %s\n",
 499                 ecc_mask ? "en" : "dis", cp->policy);
 500
 501         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 502                 struct mem_type *t = &mem_types[i];
 503                 if (t->prot_l1)
 504                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 505                 if (t->prot_sect)
 506                         t->prot_sect |= PMD_DOMAIN(t->domain);
 507         }
 508 }
 509
 510 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 511 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 512                               unsigned long size, pgprot_t vma_prot)
 513 {
 514         if (!pfn_valid(pfn))
 515                 return pgprot_noncached(vma_prot);
 516         else if (file->f_flags & O_SYNC)
 517                 return pgprot_writecombine(vma_prot);
 518         return vma_prot;
 519 }
 520 EXPORT_SYMBOL(phys_mem_access_prot);
 521 #endif
 522
 523 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 524
 525 static void __init *early_alloc(unsigned long sz)
 526 {
 527         void *ptr = __va(memblock_alloc(sz, sz));
 528         memset(ptr, 0, sz);
 529         return ptr;
 530 }
 531
 532 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 533 {
 534         if (pmd_none(*pmd)) {
 535                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 536                 __pmd_populate(pmd, __pa(pte), prot);
 537         }
 538         BUG_ON(pmd_bad(*pmd));
 539         return pte_offset_kernel(pmd, addr);
 540 }
 541
 542 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 543                                   unsigned long end, unsigned long pfn,
 544                                   const struct mem_type *type)
 545 {
 546         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 547         do {
 548                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 549                 pfn++;
 550         } while (pte++, addr += PAGE_SIZE, addr != end);
 551 }
 552
 553 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
 554                                       unsigned long end, phys_addr_t phys,
 555                                       const struct mem_type *type)
 556 {
 557         pmd_t *pmd = pmd_offset(pgd, addr);
 558
 559         /*
 560          * Try a section mapping - end, addr and phys must all be aligned
 561          * to a section boundary.  Note that PMDs refer to the individual
 562          * L1 entries, whereas PGDs refer to a group of L1 entries making
 563          * up one logical pointer to an L2 table.
 564          */
 565         if (((addr | end | phys) & ~SECTION_MASK) == 0) {
 566                 pmd_t *p = pmd;
 567
 568                 if (addr & SECTION_SIZE)
 569                         pmd++;
 570
 571                 do {
 572                         *pmd = __pmd(phys | type->prot_sect);
 573                         phys += SECTION_SIZE;
 574                 } while (pmd++, addr += SECTION_SIZE, addr != end);
 575
 576                 flush_pmd_entry(p);
 577         } else {
 578                 /*
 579                  * No need to loop; pte's aren't interested in the
 580                  * individual L1 entries.
 581                  */
 582                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
 583         }
 584 }
 585
 586 static void __init create_36bit_mapping(struct map_desc *md,
 587                                         const struct mem_type *type)
 588 {
 589         unsigned long addr, length, end;
 590         phys_addr_t phys;
 591         pgd_t *pgd;
 592
 593         addr = md->virtual;
 594         phys = (unsigned long)__pfn_to_phys(md->pfn);
 595         length = PAGE_ALIGN(md->length);
 596
 597         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 598                 printk(KERN_ERR "MM: CPU does not support supersection "
 599                        "mapping for 0x%08llx at 0x%08lx\n",
 600                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 601                 return;
 602         }
 603
 604         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 605          *      Since domain assignments can in fact be arbitrary, the
 606          *      'domain == 0' check below is required to insure that ARMv6
 607          *      supersections are only allocated for domain 0 regardless
 608          *      of the actual domain assignments in use.
 609          */
 610         if (type->domain) {
 611                 printk(KERN_ERR "MM: invalid domain in supersection "
 612                        "mapping for 0x%08llx at 0x%08lx\n",
 613                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 614                 return;
 615         }
 616
 617         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 618                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
 619                        " at 0x%08lx invalid alignment\n",
 620                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 621                 return;
 622         }
 623
 624         /*
 625          * Shift bits [35:32] of address into bits [23:20] of PMD
 626          * (See ARMv6 spec).
 627          */
 628         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 629
 630         pgd = pgd_offset_k(addr);
 631         end = addr + length;
 632         do {
 633                 pmd_t *pmd = pmd_offset(pgd, addr);
 634                 int i;
 635
 636                 for (i = 0; i < 16; i++)
 637                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 638
 639                 addr += SUPERSECTION_SIZE;
 640                 phys += SUPERSECTION_SIZE;
 641                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 642         } while (addr != end);
 643 }
 644
 645 /*
 646  * Create the page directory entries and any necessary
 647  * page tables for the mapping specified by `md'.  We
 648  * are able to cope here with varying sizes and address
 649  * offsets, and we take full advantage of sections and
 650  * supersections.
 651  */
 652 static void __init create_mapping(struct map_desc *md)
 653 {
 654         unsigned long phys, addr, length, end;
 655         const struct mem_type *type;
 656         pgd_t *pgd;
 657
 658         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 659                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
 660                        " at 0x%08lx in user region\n",
 661                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 662                 return;
 663         }
 664
 665         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 666             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 667                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
 668                        " at 0x%08lx overlaps vmalloc space\n",
 669                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 670         }
 671
 672         type = &mem_types[md->type];
 673
 674         /*
 675          * Catch 36-bit addresses
 676          */
 677         if (md->pfn >= 0x100000) {
 678                 create_36bit_mapping(md, type);
 679                 return;
 680         }
 681
 682         addr = md->virtual & PAGE_MASK;
 683         phys = (unsigned long)__pfn_to_phys(md->pfn);
 684         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 685
 686         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 687                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
 688                        "be mapped using pages, ignoring.\n",
 689                        (long long)__pfn_to_phys(md->pfn), addr);
 690                 return;
 691         }
 692
 693         pgd = pgd_offset_k(addr);
 694         end = addr + length;
 695         do {
 696                 unsigned long next = pgd_addr_end(addr, end);
 697
 698                 alloc_init_section(pgd, addr, next, phys, type);
 699
 700                 phys += next - addr;
 701                 addr = next;
 702         } while (pgd++, addr != end);
 703 }
 704
 705 /*
 706  * Create the architecture specific mappings
 707  */
 708 void __init iotable_init(struct map_desc *io_desc, int nr)
 709 {
 710         int i;
 711
 712         for (i = 0; i < nr; i++)
 713                 create_mapping(io_desc + i);
 714 }
 715
 716 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
 717
 718 /*
 719  * vmalloc=size forces the vmalloc area to be exactly 'size'
 720  * bytes. This can be used to increase (or decrease) the vmalloc
 721  * area - the default is 128m.
 722  */
 723 static int __init early_vmalloc(char *arg)
 724 {
 725         unsigned long vmalloc_reserve = memparse(arg, NULL);
 726
 727         if (vmalloc_reserve < SZ_16M) {
 728                 vmalloc_reserve = SZ_16M;
 729                 printk(KERN_WARNING
 730                         "vmalloc area too small, limiting to %luMB\n",
 731                         vmalloc_reserve >> 20);
 732         }
 733
 734         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 735                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 736                 printk(KERN_WARNING
 737                         "vmalloc area is too big, limiting to %luMB\n",
 738                         vmalloc_reserve >> 20);
 739         }
 740
 741         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 742         return 0;
 743 }
 744 early_param("vmalloc", early_vmalloc);
 745
 746 static phys_addr_t lowmem_limit __initdata = 0;
 747
 748 static void __init sanity_check_meminfo(void)
 749 {
 750         int i, j, highmem = 0;
 751
 752         lowmem_limit = __pa(vmalloc_min - 1) + 1;
 753         memblock_set_current_limit(lowmem_limit);
 754
 755         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 756                 struct membank *bank = &meminfo.bank[j];
 757                 *bank = meminfo.bank[i];
 758
 759 #ifdef CONFIG_HIGHMEM
 760                 if (__va(bank->start) > vmalloc_min ||
 761                     __va(bank->start) < (void *)PAGE_OFFSET)
 762                         highmem = 1;
 763
 764                 bank->highmem = highmem;
 765
 766                 /*
 767                  * Split those memory banks which are partially overlapping
 768                  * the vmalloc area greatly simplifying things later.
 769                  */
 770                 if (__va(bank->start) < vmalloc_min &&
 771                     bank->size > vmalloc_min - __va(bank->start)) {
 772                         if (meminfo.nr_banks >= NR_BANKS) {
 773                                 printk(KERN_CRIT "NR_BANKS too low, "
 774                                                  "ignoring high memory\n");
 775                         } else {
 776                                 memmove(bank + 1, bank,
 777                                         (meminfo.nr_banks - i) * sizeof(*bank));
 778                                 meminfo.nr_banks++;
 779                                 i++;
 780                                 bank[1].size -= vmalloc_min - __va(bank->start);
 781                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
 782                                 bank[1].highmem = highmem = 1;
 783                                 j++;
 784                         }
 785                         bank->size = vmalloc_min - __va(bank->start);
 786                 }
 787 #else
 788                 bank->highmem = highmem;
 789
 790                 /*
 791                  * Check whether this memory bank would entirely overlap
 792                  * the vmalloc area.
 793                  */
 794                 if (__va(bank->start) >= vmalloc_min ||
 795                     __va(bank->start) < (void *)PAGE_OFFSET) {
 796                         printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
 797                                "(vmalloc region overlap).\n",
 798                                bank->start, bank->start + bank->size - 1);
 799                         continue;
 800                 }
 801
 802                 /*
 803                  * Check whether this memory bank would partially overlap
 804                  * the vmalloc area.
 805                  */
 806                 if (__va(bank->start + bank->size) > vmalloc_min ||
 807                     __va(bank->start + bank->size) < __va(bank->start)) {
 808                         unsigned long newsize = vmalloc_min - __va(bank->start);
 809                         printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
 810                                "to -%.8lx (vmalloc region overlap).\n",
 811                                bank->start, bank->start + bank->size - 1,
 812                                bank->start + newsize - 1);
 813                         bank->size = newsize;
 814                 }
 815 #endif
 816                 j++;
 817         }
 818 #ifdef CONFIG_HIGHMEM
 819         if (highmem) {
 820                 const char *reason = NULL;
 821
 822                 if (cache_is_vipt_aliasing()) {
 823                         /*
 824                          * Interactions between kmap and other mappings
 825                          * make highmem support with aliasing VIPT caches
 826                          * rather difficult.
 827                          */
 828                         reason = "with VIPT aliasing cache";
 829                 } else if (is_smp() && tlb_ops_need_broadcast()) {
 830                         /*
 831                          * kmap_high needs to occasionally flush TLB entries,
 832                          * however, if the TLB entries need to be broadcast
 833                          * we may deadlock:
 834                          *  kmap_high(irqs off)->flush_all_zero_pkmaps->
 835                          *  flush_tlb_kernel_range->smp_call_function_many
 836                          *   (must not be called with irqs off)
 837                          */
 838                         reason = "without hardware TLB ops broadcasting";
 839                 }
 840                 if (reason) {
 841                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
 842                                 reason);
 843                         while (j > 0 && meminfo.bank[j - 1].highmem)
 844                                 j--;
 845                 }
 846         }
 847 #endif
 848         meminfo.nr_banks = j;
 849 }
 850
 851 static inline void prepare_page_table(void)
 852 {
 853         unsigned long addr;
 854         phys_addr_t end;
 855
 856         /*
 857          * Clear out all the mappings below the kernel image.
 858          */
 859         for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
 860                 pmd_clear(pmd_off_k(addr));
 861
 862 #ifdef CONFIG_XIP_KERNEL
 863         /* The XIP kernel is mapped in the module area -- skip over it */
 864         addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
 865 #endif
 866         for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
 867                 pmd_clear(pmd_off_k(addr));
 868
 869         /*
 870          * Find the end of the first block of lowmem.
 871          */
 872         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
 873         if (end >= lowmem_limit)
 874                 end = lowmem_limit;
 875
 876         /*
 877          * Clear out all the kernel space mappings, except for the first
 878          * memory bank, up to the end of the vmalloc region.
 879          */
 880         for (addr = __phys_to_virt(end);
 881              addr < VMALLOC_END; addr += PGDIR_SIZE)
 882                 pmd_clear(pmd_off_k(addr));
 883 }
 884
 885 /*
 886  * Reserve the special regions of memory
 887  */
 888 void __init arm_mm_memblock_reserve(void)
 889 {
 890         /*
 891          * Reserve the page tables.  These are already in use,
 892          * and can only be in node 0.
 893          */
 894         memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
 895
 896 #ifdef CONFIG_SA1111
 897         /*
 898          * Because of the SA1111 DMA bug, we want to preserve our
 899          * precious DMA-able memory...
 900          */
 901         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 902 #endif
 903 }
 904
 905 /*
 906  * Set up device the mappings.  Since we clear out the page tables for all
 907  * mappings above VMALLOC_END, we will remove any debug device mappings.
 908  * This means you have to be careful how you debug this function, or any
 909  * called function.  This means you can't use any function or debugging
 910  * method which may touch any device, otherwise the kernel _will_ crash.
 911  */
 912 static void __init devicemaps_init(struct machine_desc *mdesc)
 913 {
 914         struct map_desc map;
 915         unsigned long addr;
 916         void *vectors;
 917
 918         /*
 919          * Allocate the vector page early.
 920          */
 921         vectors = early_alloc(PAGE_SIZE);
 922
 923         for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
 924                 pmd_clear(pmd_off_k(addr));
 925
 926         /*
 927          * Map the kernel if it is XIP.
 928          * It is always first in the modulearea.
 929          */
 930 #ifdef CONFIG_XIP_KERNEL
 931         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
 932         map.virtual = MODULES_VADDR;
 933         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
 934         map.type = MT_ROM;
 935         create_mapping(&map);
 936 #endif
 937
 938         /*
 939          * Map the cache flushing regions.
 940          */
 941 #ifdef FLUSH_BASE
 942         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
 943         map.virtual = FLUSH_BASE;
 944         map.length = SZ_1M;
 945         map.type = MT_CACHECLEAN;
 946         create_mapping(&map);
 947 #endif
 948 #ifdef FLUSH_BASE_MINICACHE
 949         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
 950         map.virtual = FLUSH_BASE_MINICACHE;
 951         map.length = SZ_1M;
 952         map.type = MT_MINICLEAN;
 953         create_mapping(&map);
 954 #endif
 955
 956         /*
 957          * Create a mapping for the machine vectors at the high-vectors
 958          * location (0xffff0000).  If we aren't using high-vectors, also
 959          * create a mapping at the low-vectors virtual address.
 960          */
 961         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
 962         map.virtual = 0xffff0000;
 963         map.length = PAGE_SIZE;
 964         map.type = MT_HIGH_VECTORS;
 965         create_mapping(&map);
 966
 967         if (!vectors_high()) {
 968                 map.virtual = 0;
 969                 map.type = MT_LOW_VECTORS;
 970                 create_mapping(&map);
 971         }
 972
 973         /*
 974          * Ask the machine support to map in the statically mapped devices.
 975          */
 976         if (mdesc->map_io)
 977                 mdesc->map_io();
 978
 979         /*
 980          * Finally flush the caches and tlb to ensure that we're in a
 981          * consistent state wrt the writebuffer.  This also ensures that
 982          * any write-allocated cache lines in the vector page are written
 983          * back.  After this point, we can start to touch devices again.
 984          */
 985         local_flush_tlb_all();
 986         flush_cache_all();
 987 }
 988
 989 static void __init kmap_init(void)
 990 {
 991 #ifdef CONFIG_HIGHMEM
 992         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
 993                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
 994 #endif
 995 }
 996
 997 static void __init map_lowmem(void)
 998 {
 999         struct memblock_region *reg;
1000
1001         /* Map all the lowmem memory banks. */
1002         for_each_memblock(memory, reg) {
1003                 phys_addr_t start = reg->base;
1004                 phys_addr_t end = start + reg->size;
1005                 struct map_desc map;
1006
1007                 if (end > lowmem_limit)
1008                         end = lowmem_limit;
1009                 if (start >= end)
1010                         break;
1011
1012                 map.pfn = __phys_to_pfn(start);
1013                 map.virtual = __phys_to_virt(start);
1014                 map.length = end - start;
1015                 map.type = MT_MEMORY;
1016
1017                 create_mapping(&map);
1018         }
1019 }
1020
1021 /*
1022  * paging_init() sets up the page tables, initialises the zone memory
1023  * maps, and sets up the zero page, bad page and bad page tables.
1024  */
1025 void __init paging_init(struct machine_desc *mdesc)
1026 {
1027         void *zero_page;
1028
1029         build_mem_type_table();
1030         sanity_check_meminfo();
1031         prepare_page_table();
1032         map_lowmem();
1033         devicemaps_init(mdesc);
1034         kmap_init();
1035
1036         top_pmd = pmd_off_k(0xffff0000);
1037
1038         /* allocate the zero page. */
1039         zero_page = early_alloc(PAGE_SIZE);
1040
1041         bootmem_init();
1042
1043         empty_zero_page = virt_to_page(zero_page);
1044         __flush_dcache_page(NULL, empty_zero_page);
1045 }