1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on linux/arch/arm/mm/dma-mapping.c
5 * Copyright (C) 2000-2004 Russell King
8 #include <linux/export.h>
10 #include <linux/dma-direct.h>
11 #include <linux/scatterlist.h>
13 #include <asm/cachetype.h>
14 #include <asm/cacheflush.h>
15 #include <asm/outercache.h>
21 * The generic direct mapping code is used if
23 * - cpu is v7m w/o cache support
24 * - device is coherent
25 * otherwise arm_nommu_dma_ops is used.
27 * arm_nommu_dma_ops rely on consistent DMA memory (please, refer to
28 * [1] on how to declare such memory).
30 * [1] Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
33 static void *arm_nommu_dma_alloc(struct device *dev, size_t size,
34 dma_addr_t *dma_handle, gfp_t gfp,
41 * Try generic allocator first if we are advertised that
42 * consistency is not required.
45 if (attrs & DMA_ATTR_NON_CONSISTENT)
46 return dma_direct_alloc_pages(dev, size, dma_handle, gfp,
49 ret = dma_alloc_from_global_coherent(size, dma_handle);
52 * dma_alloc_from_global_coherent() may fail because:
54 * - no consistent DMA region has been defined, so we can't
56 * - there is no space left in consistent DMA region, so we
57 * only can fallback to generic allocator if we are
58 * advertised that consistency is not required.
61 WARN_ON_ONCE(ret == NULL);
65 static void arm_nommu_dma_free(struct device *dev, size_t size,
66 void *cpu_addr, dma_addr_t dma_addr,
69 if (attrs & DMA_ATTR_NON_CONSISTENT) {
70 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);
72 int ret = dma_release_from_global_coherent(get_order(size),
75 WARN_ON_ONCE(ret == 0);
81 static int arm_nommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
82 void *cpu_addr, dma_addr_t dma_addr, size_t size,
87 if (dma_mmap_from_global_coherent(vma, cpu_addr, size, &ret))
90 return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
94 static void __dma_page_cpu_to_dev(phys_addr_t paddr, size_t size,
95 enum dma_data_direction dir)
97 dmac_map_area(__va(paddr), size, dir);
99 if (dir == DMA_FROM_DEVICE)
100 outer_inv_range(paddr, paddr + size);
102 outer_clean_range(paddr, paddr + size);
105 static void __dma_page_dev_to_cpu(phys_addr_t paddr, size_t size,
106 enum dma_data_direction dir)
108 if (dir != DMA_TO_DEVICE) {
109 outer_inv_range(paddr, paddr + size);
110 dmac_unmap_area(__va(paddr), size, dir);
114 static dma_addr_t arm_nommu_dma_map_page(struct device *dev, struct page *page,
115 unsigned long offset, size_t size,
116 enum dma_data_direction dir,
119 dma_addr_t handle = page_to_phys(page) + offset;
121 __dma_page_cpu_to_dev(handle, size, dir);
126 static void arm_nommu_dma_unmap_page(struct device *dev, dma_addr_t handle,
127 size_t size, enum dma_data_direction dir,
130 __dma_page_dev_to_cpu(handle, size, dir);
134 static int arm_nommu_dma_map_sg(struct device *dev, struct scatterlist *sgl,
135 int nents, enum dma_data_direction dir,
139 struct scatterlist *sg;
141 for_each_sg(sgl, sg, nents, i) {
142 sg_dma_address(sg) = sg_phys(sg);
143 sg_dma_len(sg) = sg->length;
144 __dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir);
150 static void arm_nommu_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
151 int nents, enum dma_data_direction dir,
154 struct scatterlist *sg;
157 for_each_sg(sgl, sg, nents, i)
158 __dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir);
161 static void arm_nommu_dma_sync_single_for_device(struct device *dev,
162 dma_addr_t handle, size_t size, enum dma_data_direction dir)
164 __dma_page_cpu_to_dev(handle, size, dir);
167 static void arm_nommu_dma_sync_single_for_cpu(struct device *dev,
168 dma_addr_t handle, size_t size, enum dma_data_direction dir)
170 __dma_page_cpu_to_dev(handle, size, dir);
173 static void arm_nommu_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
174 int nents, enum dma_data_direction dir)
176 struct scatterlist *sg;
179 for_each_sg(sgl, sg, nents, i)
180 __dma_page_cpu_to_dev(sg_dma_address(sg), sg_dma_len(sg), dir);
183 static void arm_nommu_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
184 int nents, enum dma_data_direction dir)
186 struct scatterlist *sg;
189 for_each_sg(sgl, sg, nents, i)
190 __dma_page_dev_to_cpu(sg_dma_address(sg), sg_dma_len(sg), dir);
193 const struct dma_map_ops arm_nommu_dma_ops = {
194 .alloc = arm_nommu_dma_alloc,
195 .free = arm_nommu_dma_free,
196 .mmap = arm_nommu_dma_mmap,
197 .map_page = arm_nommu_dma_map_page,
198 .unmap_page = arm_nommu_dma_unmap_page,
199 .map_sg = arm_nommu_dma_map_sg,
200 .unmap_sg = arm_nommu_dma_unmap_sg,
201 .sync_single_for_device = arm_nommu_dma_sync_single_for_device,
202 .sync_single_for_cpu = arm_nommu_dma_sync_single_for_cpu,
203 .sync_sg_for_device = arm_nommu_dma_sync_sg_for_device,
204 .sync_sg_for_cpu = arm_nommu_dma_sync_sg_for_cpu,
206 EXPORT_SYMBOL(arm_nommu_dma_ops);
208 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
209 const struct iommu_ops *iommu, bool coherent)
211 if (IS_ENABLED(CONFIG_CPU_V7M)) {
213 * Cache support for v7m is optional, so can be treated as
214 * coherent if no cache has been detected. Note that it is not
215 * enough to check if MPU is in use or not since in absense of
216 * MPU system memory map is used.
218 dev->archdata.dma_coherent = (cacheid) ? coherent : true;
221 * Assume coherent DMA in case MMU/MPU has not been set up.
223 dev->archdata.dma_coherent = (get_cr() & CR_M) ? coherent : true;
226 if (!dev->archdata.dma_coherent)
227 set_dma_ops(dev, &arm_nommu_dma_ops);