2 * linux/arch/arm/lib/copypage-armv4mc.S
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This handles the mini data cache, as found on SA11x0 and XScale
11 * processors. When we copy a user page page, we map it in such a way
12 * that accesses to this page will not touch the main data cache, but
13 * will be cached in the mini data cache. This prevents us thrashing
14 * the main data cache on page faults.
16 #include <linux/init.h>
18 #include <linux/highmem.h>
20 #include <asm/pgtable.h>
21 #include <asm/tlbflush.h>
22 #include <asm/cacheflush.h>
26 #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
29 static DEFINE_RAW_SPINLOCK(minicache_lock);
32 * ARMv4 mini-dcache optimised copy_user_highpage
34 * We flush the destination cache lines just before we write the data into the
35 * corresponding address. Since the Dcache is read-allocate, this removes the
36 * Dcache aliasing issue. The writes will be forwarded to the write buffer,
37 * and merged as appropriate.
39 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
40 * instruction. If your processor does not supply this, you have to write your
41 * own copy_user_highpage that does the right thing.
43 static void mc_copy_user_page(void *from, void *to)
48 ldmia %0!, {r2, r3, ip, lr} @ 4\n\
49 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\
50 stmia %1!, {r2, r3, ip, lr} @ 4\n\
51 ldmia %0!, {r2, r3, ip, lr} @ 4+1\n\
52 stmia %1!, {r2, r3, ip, lr} @ 4\n\
53 ldmia %0!, {r2, r3, ip, lr} @ 4\n\
54 mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\
55 stmia %1!, {r2, r3, ip, lr} @ 4\n\
56 ldmia %0!, {r2, r3, ip, lr} @ 4\n\
57 subs %2, %2, #1 @ 1\n\
58 stmia %1!, {r2, r3, ip, lr} @ 4\n\
59 ldmneia %0!, {r2, r3, ip, lr} @ 4\n\
61 : "+&r" (from), "+&r" (to), "=&r" (tmp)
62 : "2" (PAGE_SIZE / 64)
63 : "r2", "r3", "ip", "lr");
66 void v4_mc_copy_user_highpage(struct page *to, struct page *from,
67 unsigned long vaddr, struct vm_area_struct *vma)
69 void *kto = kmap_atomic(to);
71 if (!test_and_set_bit(PG_dcache_clean, &from->flags))
72 __flush_dcache_page(page_mapping_file(from), from);
74 raw_spin_lock(&minicache_lock);
76 set_top_pte(COPYPAGE_MINICACHE, mk_pte(from, minicache_pgprot));
78 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
80 raw_spin_unlock(&minicache_lock);
86 * ARMv4 optimised clear_user_page
88 void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
90 void *ptr, *kaddr = kmap_atomic(page);
97 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
98 stmia %0!, {r2, r3, ip, lr} @ 4\n\
99 stmia %0!, {r2, r3, ip, lr} @ 4\n\
100 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
101 stmia %0!, {r2, r3, ip, lr} @ 4\n\
102 stmia %0!, {r2, r3, ip, lr} @ 4\n\
103 subs r1, r1, #1 @ 1\n\
106 : "0" (kaddr), "I" (PAGE_SIZE / 64)
107 : "r1", "r2", "r3", "ip", "lr");
108 kunmap_atomic(kaddr);
111 struct cpu_user_fns v4_mc_user_fns __initdata = {
112 .cpu_clear_user_highpage = v4_mc_clear_user_highpage,
113 .cpu_copy_user_highpage = v4_mc_copy_user_highpage,