arch/arm/mm/alignment.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  linux/arch/arm/mm/alignment.c
   4  *
   5  *  Copyright (C) 1995  Linus Torvalds
   6  *  Modifications for ARM processor (c) 1995-2001 Russell King
   7  *  Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
   8  *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
   9  *    Copyright (C) 1996, Cygnus Software Technologies Ltd.
  10  */
  11 #include <linux/moduleparam.h>
  12 #include <linux/compiler.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched/debug.h>
  15 #include <linux/errno.h>
  16 #include <linux/string.h>
  17 #include <linux/proc_fs.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/init.h>
  20 #include <linux/sched/signal.h>
  21 #include <linux/uaccess.h>
  22
  23 #include <asm/cp15.h>
  24 #include <asm/system_info.h>
  25 #include <asm/unaligned.h>
  26 #include <asm/opcodes.h>
  27
  28 #include "fault.h"
  29 #include "mm.h"
  30
  31 /*
  32  * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
  33  * /proc/sys/debug/alignment, modified and integrated into
  34  * Linux 2.1 by Russell King
  35  *
  36  * Speed optimisations and better fault handling by Russell King.
  37  *
  38  * *** NOTE ***
  39  * This code is not portable to processors with late data abort handling.
  40  */
  41 #define CODING_BITS(i)  (i & 0x0e000000)
  42 #define COND_BITS(i)    (i & 0xf0000000)
  43
  44 #define LDST_I_BIT(i)   (i & (1 << 26))         /* Immediate constant   */
  45 #define LDST_P_BIT(i)   (i & (1 << 24))         /* Preindex             */
  46 #define LDST_U_BIT(i)   (i & (1 << 23))         /* Add offset           */
  47 #define LDST_W_BIT(i)   (i & (1 << 21))         /* Writeback            */
  48 #define LDST_L_BIT(i)   (i & (1 << 20))         /* Load                 */
  49
  50 #define LDST_P_EQ_U(i)  ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
  51
  52 #define LDSTHD_I_BIT(i) (i & (1 << 22))         /* double/half-word immed */
  53 #define LDM_S_BIT(i)    (i & (1 << 22))         /* write CPSR from SPSR */
  54
  55 #define RN_BITS(i)      ((i >> 16) & 15)        /* Rn                   */
  56 #define RD_BITS(i)      ((i >> 12) & 15)        /* Rd                   */
  57 #define RM_BITS(i)      (i & 15)                /* Rm                   */
  58
  59 #define REGMASK_BITS(i) (i & 0xffff)
  60 #define OFFSET_BITS(i)  (i & 0x0fff)
  61
  62 #define IS_SHIFT(i)     (i & 0x0ff0)
  63 #define SHIFT_BITS(i)   ((i >> 7) & 0x1f)
  64 #define SHIFT_TYPE(i)   (i & 0x60)
  65 #define SHIFT_LSL       0x00
  66 #define SHIFT_LSR       0x20
  67 #define SHIFT_ASR       0x40
  68 #define SHIFT_RORRRX    0x60
  69
  70 #define BAD_INSTR       0xdeadc0de
  71
  72 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
  73 #define IS_T32(hi16) \
  74         (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
  75
  76 static unsigned long ai_user;
  77 static unsigned long ai_sys;
  78 static void *ai_sys_last_pc;
  79 static unsigned long ai_skipped;
  80 static unsigned long ai_half;
  81 static unsigned long ai_word;
  82 static unsigned long ai_dword;
  83 static unsigned long ai_multi;
  84 static int ai_usermode;
  85 static unsigned long cr_no_alignment;
  86
  87 core_param(alignment, ai_usermode, int, 0600);
  88
  89 #define UM_WARN         (1 << 0)
  90 #define UM_FIXUP        (1 << 1)
  91 #define UM_SIGNAL       (1 << 2)
  92
  93 /* Return true if and only if the ARMv6 unaligned access model is in use. */
  94 static bool cpu_is_v6_unaligned(void)
  95 {
  96         return cpu_architecture() >= CPU_ARCH_ARMv6 && get_cr() & CR_U;
  97 }
  98
  99 static int safe_usermode(int new_usermode, bool warn)
 100 {
 101         /*
 102          * ARMv6 and later CPUs can perform unaligned accesses for
 103          * most single load and store instructions up to word size.
 104          * LDM, STM, LDRD and STRD still need to be handled.
 105          *
 106          * Ignoring the alignment fault is not an option on these
 107          * CPUs since we spin re-faulting the instruction without
 108          * making any progress.
 109          */
 110         if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) {
 111                 new_usermode |= UM_FIXUP;
 112
 113                 if (warn)
 114                         pr_warn("alignment: ignoring faults is unsafe on this CPU.  Defaulting to fixup mode.\n");
 115         }
 116
 117         return new_usermode;
 118 }
 119
 120 #ifdef CONFIG_PROC_FS
 121 static const char *usermode_action[] = {
 122         "ignored",
 123         "warn",
 124         "fixup",
 125         "fixup+warn",
 126         "signal",
 127         "signal+warn"
 128 };
 129
 130 static int alignment_proc_show(struct seq_file *m, void *v)
 131 {
 132         seq_printf(m, "User:\t\t%lu\n", ai_user);
 133         seq_printf(m, "System:\t\t%lu (%pS)\n", ai_sys, ai_sys_last_pc);
 134         seq_printf(m, "Skipped:\t%lu\n", ai_skipped);
 135         seq_printf(m, "Half:\t\t%lu\n", ai_half);
 136         seq_printf(m, "Word:\t\t%lu\n", ai_word);
 137         if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
 138                 seq_printf(m, "DWord:\t\t%lu\n", ai_dword);
 139         seq_printf(m, "Multi:\t\t%lu\n", ai_multi);
 140         seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode,
 141                         usermode_action[ai_usermode]);
 142
 143         return 0;
 144 }
 145
 146 static int alignment_proc_open(struct inode *inode, struct file *file)
 147 {
 148         return single_open(file, alignment_proc_show, NULL);
 149 }
 150
 151 static ssize_t alignment_proc_write(struct file *file, const char __user *buffer,
 152                                     size_t count, loff_t *pos)
 153 {
 154         char mode;
 155
 156         if (count > 0) {
 157                 if (get_user(mode, buffer))
 158                         return -EFAULT;
 159                 if (mode >= '0' && mode <= '5')
 160                         ai_usermode = safe_usermode(mode - '0', true);
 161         }
 162         return count;
 163 }
 164
 165 static const struct file_operations alignment_proc_fops = {
 166         .open           = alignment_proc_open,
 167         .read           = seq_read,
 168         .llseek         = seq_lseek,
 169         .release        = single_release,
 170         .write          = alignment_proc_write,
 171 };
 172 #endif /* CONFIG_PROC_FS */
 173
 174 union offset_union {
 175         unsigned long un;
 176           signed long sn;
 177 };
 178
 179 #define TYPE_ERROR      0
 180 #define TYPE_FAULT      1
 181 #define TYPE_LDST       2
 182 #define TYPE_DONE       3
 183
 184 #ifdef __ARMEB__
 185 #define BE              1
 186 #define FIRST_BYTE_16   "mov    %1, %1, ror #8\n"
 187 #define FIRST_BYTE_32   "mov    %1, %1, ror #24\n"
 188 #define NEXT_BYTE       "ror #24"
 189 #else
 190 #define BE              0
 191 #define FIRST_BYTE_16
 192 #define FIRST_BYTE_32
 193 #define NEXT_BYTE       "lsr #8"
 194 #endif
 195
 196 #define __get8_unaligned_check(ins,val,addr,err)        \
 197         __asm__(                                        \
 198  ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 199  THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 200  THUMB( "       add     %2, %2, #1\n"   )               \
 201         "2:\n"                                          \
 202         "       .pushsection .text.fixup,\"ax\"\n"      \
 203         "       .align  2\n"                            \
 204         "3:     mov     %0, #1\n"                       \
 205         "       b       2b\n"                           \
 206         "       .popsection\n"                          \
 207         "       .pushsection __ex_table,\"a\"\n"        \
 208         "       .align  3\n"                            \
 209         "       .long   1b, 3b\n"                       \
 210         "       .popsection\n"                          \
 211         : "=r" (err), "=&r" (val), "=r" (addr)          \
 212         : "0" (err), "2" (addr))
 213
 214 #define __get16_unaligned_check(ins,val,addr)                   \
 215         do {                                                    \
 216                 unsigned int err = 0, v, a = addr;              \
 217                 __get8_unaligned_check(ins,v,a,err);            \
 218                 val =  v << ((BE) ? 8 : 0);                     \
 219                 __get8_unaligned_check(ins,v,a,err);            \
 220                 val |= v << ((BE) ? 0 : 8);                     \
 221                 if (err)                                        \
 222                         goto fault;                             \
 223         } while (0)
 224
 225 #define get16_unaligned_check(val,addr) \
 226         __get16_unaligned_check("ldrb",val,addr)
 227
 228 #define get16t_unaligned_check(val,addr) \
 229         __get16_unaligned_check("ldrbt",val,addr)
 230
 231 #define __get32_unaligned_check(ins,val,addr)                   \
 232         do {                                                    \
 233                 unsigned int err = 0, v, a = addr;              \
 234                 __get8_unaligned_check(ins,v,a,err);            \
 235                 val =  v << ((BE) ? 24 :  0);                   \
 236                 __get8_unaligned_check(ins,v,a,err);            \
 237                 val |= v << ((BE) ? 16 :  8);                   \
 238                 __get8_unaligned_check(ins,v,a,err);            \
 239                 val |= v << ((BE) ?  8 : 16);                   \
 240                 __get8_unaligned_check(ins,v,a,err);            \
 241                 val |= v << ((BE) ?  0 : 24);                   \
 242                 if (err)                                        \
 243                         goto fault;                             \
 244         } while (0)
 245
 246 #define get32_unaligned_check(val,addr) \
 247         __get32_unaligned_check("ldrb",val,addr)
 248
 249 #define get32t_unaligned_check(val,addr) \
 250         __get32_unaligned_check("ldrbt",val,addr)
 251
 252 #define __put16_unaligned_check(ins,val,addr)                   \
 253         do {                                                    \
 254                 unsigned int err = 0, v = val, a = addr;        \
 255                 __asm__( FIRST_BYTE_16                          \
 256          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 257          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 258          THUMB( "       add     %2, %2, #1\n"   )               \
 259                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 260                 "2:     "ins"   %1, [%2]\n"                     \
 261                 "3:\n"                                          \
 262                 "       .pushsection .text.fixup,\"ax\"\n"      \
 263                 "       .align  2\n"                            \
 264                 "4:     mov     %0, #1\n"                       \
 265                 "       b       3b\n"                           \
 266                 "       .popsection\n"                          \
 267                 "       .pushsection __ex_table,\"a\"\n"        \
 268                 "       .align  3\n"                            \
 269                 "       .long   1b, 4b\n"                       \
 270                 "       .long   2b, 4b\n"                       \
 271                 "       .popsection\n"                          \
 272                 : "=r" (err), "=&r" (v), "=&r" (a)              \
 273                 : "0" (err), "1" (v), "2" (a));                 \
 274                 if (err)                                        \
 275                         goto fault;                             \
 276         } while (0)
 277
 278 #define put16_unaligned_check(val,addr)  \
 279         __put16_unaligned_check("strb",val,addr)
 280
 281 #define put16t_unaligned_check(val,addr) \
 282         __put16_unaligned_check("strbt",val,addr)
 283
 284 #define __put32_unaligned_check(ins,val,addr)                   \
 285         do {                                                    \
 286                 unsigned int err = 0, v = val, a = addr;        \
 287                 __asm__( FIRST_BYTE_32                          \
 288          ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 289          THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 290          THUMB( "       add     %2, %2, #1\n"   )               \
 291                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 292          ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
 293          THUMB( "2:     "ins"   %1, [%2]\n"     )               \
 294          THUMB( "       add     %2, %2, #1\n"   )               \
 295                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 296          ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
 297          THUMB( "3:     "ins"   %1, [%2]\n"     )               \
 298          THUMB( "       add     %2, %2, #1\n"   )               \
 299                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
 300                 "4:     "ins"   %1, [%2]\n"                     \
 301                 "5:\n"                                          \
 302                 "       .pushsection .text.fixup,\"ax\"\n"      \
 303                 "       .align  2\n"                            \
 304                 "6:     mov     %0, #1\n"                       \
 305                 "       b       5b\n"                           \
 306                 "       .popsection\n"                          \
 307                 "       .pushsection __ex_table,\"a\"\n"        \
 308                 "       .align  3\n"                            \
 309                 "       .long   1b, 6b\n"                       \
 310                 "       .long   2b, 6b\n"                       \
 311                 "       .long   3b, 6b\n"                       \
 312                 "       .long   4b, 6b\n"                       \
 313                 "       .popsection\n"                          \
 314                 : "=r" (err), "=&r" (v), "=&r" (a)              \
 315                 : "0" (err), "1" (v), "2" (a));                 \
 316                 if (err)                                        \
 317                         goto fault;                             \
 318         } while (0)
 319
 320 #define put32_unaligned_check(val,addr) \
 321         __put32_unaligned_check("strb", val, addr)
 322
 323 #define put32t_unaligned_check(val,addr) \
 324         __put32_unaligned_check("strbt", val, addr)
 325
 326 static void
 327 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
 328 {
 329         if (!LDST_U_BIT(instr))
 330                 offset.un = -offset.un;
 331
 332         if (!LDST_P_BIT(instr))
 333                 addr += offset.un;
 334
 335         if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
 336                 regs->uregs[RN_BITS(instr)] = addr;
 337 }
 338
 339 static int
 340 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 341 {
 342         unsigned int rd = RD_BITS(instr);
 343
 344         ai_half += 1;
 345
 346         if (user_mode(regs))
 347                 goto user;
 348
 349         if (LDST_L_BIT(instr)) {
 350                 unsigned long val;
 351                 get16_unaligned_check(val, addr);
 352
 353                 /* signed half-word? */
 354                 if (instr & 0x40)
 355                         val = (signed long)((signed short) val);
 356
 357                 regs->uregs[rd] = val;
 358         } else
 359                 put16_unaligned_check(regs->uregs[rd], addr);
 360
 361         return TYPE_LDST;
 362
 363  user:
 364         if (LDST_L_BIT(instr)) {
 365                 unsigned long val;
 366                 unsigned int __ua_flags = uaccess_save_and_enable();
 367
 368                 get16t_unaligned_check(val, addr);
 369                 uaccess_restore(__ua_flags);
 370
 371                 /* signed half-word? */
 372                 if (instr & 0x40)
 373                         val = (signed long)((signed short) val);
 374
 375                 regs->uregs[rd] = val;
 376         } else {
 377                 unsigned int __ua_flags = uaccess_save_and_enable();
 378                 put16t_unaligned_check(regs->uregs[rd], addr);
 379                 uaccess_restore(__ua_flags);
 380         }
 381
 382         return TYPE_LDST;
 383
 384  fault:
 385         return TYPE_FAULT;
 386 }
 387
 388 static int
 389 do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
 390                       struct pt_regs *regs)
 391 {
 392         unsigned int rd = RD_BITS(instr);
 393         unsigned int rd2;
 394         int load;
 395
 396         if ((instr & 0xfe000000) == 0xe8000000) {
 397                 /* ARMv7 Thumb-2 32-bit LDRD/STRD */
 398                 rd2 = (instr >> 8) & 0xf;
 399                 load = !!(LDST_L_BIT(instr));
 400         } else if (((rd & 1) == 1) || (rd == 14))
 401                 goto bad;
 402         else {
 403                 load = ((instr & 0xf0) == 0xd0);
 404                 rd2 = rd + 1;
 405         }
 406
 407         ai_dword += 1;
 408
 409         if (user_mode(regs))
 410                 goto user;
 411
 412         if (load) {
 413                 unsigned long val;
 414                 get32_unaligned_check(val, addr);
 415                 regs->uregs[rd] = val;
 416                 get32_unaligned_check(val, addr + 4);
 417                 regs->uregs[rd2] = val;
 418         } else {
 419                 put32_unaligned_check(regs->uregs[rd], addr);
 420                 put32_unaligned_check(regs->uregs[rd2], addr + 4);
 421         }
 422
 423         return TYPE_LDST;
 424
 425  user:
 426         if (load) {
 427                 unsigned long val, val2;
 428                 unsigned int __ua_flags = uaccess_save_and_enable();
 429
 430                 get32t_unaligned_check(val, addr);
 431                 get32t_unaligned_check(val2, addr + 4);
 432
 433                 uaccess_restore(__ua_flags);
 434
 435                 regs->uregs[rd] = val;
 436                 regs->uregs[rd2] = val2;
 437         } else {
 438                 unsigned int __ua_flags = uaccess_save_and_enable();
 439                 put32t_unaligned_check(regs->uregs[rd], addr);
 440                 put32t_unaligned_check(regs->uregs[rd2], addr + 4);
 441                 uaccess_restore(__ua_flags);
 442         }
 443
 444         return TYPE_LDST;
 445  bad:
 446         return TYPE_ERROR;
 447  fault:
 448         return TYPE_FAULT;
 449 }
 450
 451 static int
 452 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 453 {
 454         unsigned int rd = RD_BITS(instr);
 455
 456         ai_word += 1;
 457
 458         if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
 459                 goto trans;
 460
 461         if (LDST_L_BIT(instr)) {
 462                 unsigned int val;
 463                 get32_unaligned_check(val, addr);
 464                 regs->uregs[rd] = val;
 465         } else
 466                 put32_unaligned_check(regs->uregs[rd], addr);
 467         return TYPE_LDST;
 468
 469  trans:
 470         if (LDST_L_BIT(instr)) {
 471                 unsigned int val;
 472                 unsigned int __ua_flags = uaccess_save_and_enable();
 473                 get32t_unaligned_check(val, addr);
 474                 uaccess_restore(__ua_flags);
 475                 regs->uregs[rd] = val;
 476         } else {
 477                 unsigned int __ua_flags = uaccess_save_and_enable();
 478                 put32t_unaligned_check(regs->uregs[rd], addr);
 479                 uaccess_restore(__ua_flags);
 480         }
 481         return TYPE_LDST;
 482
 483  fault:
 484         return TYPE_FAULT;
 485 }
 486
 487 /*
 488  * LDM/STM alignment handler.
 489  *
 490  * There are 4 variants of this instruction:
 491  *
 492  * B = rn pointer before instruction, A = rn pointer after instruction
 493  *              ------ increasing address ----->
 494  *              |    | r0 | r1 | ... | rx |    |
 495  * PU = 01             B                    A
 496  * PU = 11        B                    A
 497  * PU = 00        A                    B
 498  * PU = 10             A                    B
 499  */
 500 static int
 501 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 502 {
 503         unsigned int rd, rn, correction, nr_regs, regbits;
 504         unsigned long eaddr, newaddr;
 505
 506         if (LDM_S_BIT(instr))
 507                 goto bad;
 508
 509         correction = 4; /* processor implementation defined */
 510         regs->ARM_pc += correction;
 511
 512         ai_multi += 1;
 513
 514         /* count the number of registers in the mask to be transferred */
 515         nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
 516
 517         rn = RN_BITS(instr);
 518         newaddr = eaddr = regs->uregs[rn];
 519
 520         if (!LDST_U_BIT(instr))
 521                 nr_regs = -nr_regs;
 522         newaddr += nr_regs;
 523         if (!LDST_U_BIT(instr))
 524                 eaddr = newaddr;
 525
 526         if (LDST_P_EQ_U(instr)) /* U = P */
 527                 eaddr += 4;
 528
 529         /*
 530          * For alignment faults on the ARM922T/ARM920T the MMU  makes
 531          * the FSR (and hence addr) equal to the updated base address
 532          * of the multiple access rather than the restored value.
 533          * Switch this message off if we've got a ARM92[02], otherwise
 534          * [ls]dm alignment faults are noisy!
 535          */
 536 #if !(defined CONFIG_CPU_ARM922T)  && !(defined CONFIG_CPU_ARM920T)
 537         /*
 538          * This is a "hint" - we already have eaddr worked out by the
 539          * processor for us.
 540          */
 541         if (addr != eaddr) {
 542                 pr_err("LDMSTM: PC = %08lx, instr = %08lx, "
 543                         "addr = %08lx, eaddr = %08lx\n",
 544                          instruction_pointer(regs), instr, addr, eaddr);
 545                 show_regs(regs);
 546         }
 547 #endif
 548
 549         if (user_mode(regs)) {
 550                 unsigned int __ua_flags = uaccess_save_and_enable();
 551                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 552                      regbits >>= 1, rd += 1)
 553                         if (regbits & 1) {
 554                                 if (LDST_L_BIT(instr)) {
 555                                         unsigned int val;
 556                                         get32t_unaligned_check(val, eaddr);
 557                                         regs->uregs[rd] = val;
 558                                 } else
 559                                         put32t_unaligned_check(regs->uregs[rd], eaddr);
 560                                 eaddr += 4;
 561                         }
 562                 uaccess_restore(__ua_flags);
 563         } else {
 564                 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 565                      regbits >>= 1, rd += 1)
 566                         if (regbits & 1) {
 567                                 if (LDST_L_BIT(instr)) {
 568                                         unsigned int val;
 569                                         get32_unaligned_check(val, eaddr);
 570                                         regs->uregs[rd] = val;
 571                                 } else
 572                                         put32_unaligned_check(regs->uregs[rd], eaddr);
 573                                 eaddr += 4;
 574                         }
 575         }
 576
 577         if (LDST_W_BIT(instr))
 578                 regs->uregs[rn] = newaddr;
 579         if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
 580                 regs->ARM_pc -= correction;
 581         return TYPE_DONE;
 582
 583 fault:
 584         regs->ARM_pc -= correction;
 585         return TYPE_FAULT;
 586
 587 bad:
 588         pr_err("Alignment trap: not handling ldm with s-bit set\n");
 589         return TYPE_ERROR;
 590 }
 591
 592 /*
 593  * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
 594  * we can reuse ARM userland alignment fault fixups for Thumb.
 595  *
 596  * This implementation was initially based on the algorithm found in
 597  * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
 598  * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
 599  *
 600  * NOTES:
 601  * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
 602  * 2. If for some reason we're passed an non-ld/st Thumb instruction to
 603  *    decode, we return 0xdeadc0de. This should never happen under normal
 604  *    circumstances but if it does, we've got other problems to deal with
 605  *    elsewhere and we obviously can't fix those problems here.
 606  */
 607
 608 static unsigned long
 609 thumb2arm(u16 tinstr)
 610 {
 611         u32 L = (tinstr & (1<<11)) >> 11;
 612
 613         switch ((tinstr & 0xf800) >> 11) {
 614         /* 6.5.1 Format 1: */
 615         case 0x6000 >> 11:                              /* 7.1.52 STR(1) */
 616         case 0x6800 >> 11:                              /* 7.1.26 LDR(1) */
 617         case 0x7000 >> 11:                              /* 7.1.55 STRB(1) */
 618         case 0x7800 >> 11:                              /* 7.1.30 LDRB(1) */
 619                 return 0xe5800000 |
 620                         ((tinstr & (1<<12)) << (22-12)) |       /* fixup */
 621                         (L<<20) |                               /* L==1? */
 622                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 623                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 624                         ((tinstr & (31<<6)) >>                  /* immed_5 */
 625                                 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
 626         case 0x8000 >> 11:                              /* 7.1.57 STRH(1) */
 627         case 0x8800 >> 11:                              /* 7.1.32 LDRH(1) */
 628                 return 0xe1c000b0 |
 629                         (L<<20) |                               /* L==1? */
 630                         ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 631                         ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 632                         ((tinstr & (7<<6)) >> (6-1)) |   /* immed_5[2:0] */
 633                         ((tinstr & (3<<9)) >> (9-8));    /* immed_5[4:3] */
 634
 635         /* 6.5.1 Format 2: */
 636         case 0x5000 >> 11:
 637         case 0x5800 >> 11:
 638                 {
 639                         static const u32 subset[8] = {
 640                                 0xe7800000,             /* 7.1.53 STR(2) */
 641                                 0xe18000b0,             /* 7.1.58 STRH(2) */
 642                                 0xe7c00000,             /* 7.1.56 STRB(2) */
 643                                 0xe19000d0,             /* 7.1.34 LDRSB */
 644                                 0xe7900000,             /* 7.1.27 LDR(2) */
 645                                 0xe19000b0,             /* 7.1.33 LDRH(2) */
 646                                 0xe7d00000,             /* 7.1.31 LDRB(2) */
 647                                 0xe19000f0              /* 7.1.35 LDRSH */
 648                         };
 649                         return subset[(tinstr & (7<<9)) >> 9] |
 650                             ((tinstr & (7<<0)) << (12-0)) |     /* Rd */
 651                             ((tinstr & (7<<3)) << (16-3)) |     /* Rn */
 652                             ((tinstr & (7<<6)) >> (6-0));       /* Rm */
 653                 }
 654
 655         /* 6.5.1 Format 3: */
 656         case 0x4800 >> 11:                              /* 7.1.28 LDR(3) */
 657                 /* NOTE: This case is not technically possible. We're
 658                  *       loading 32-bit memory data via PC relative
 659                  *       addressing mode. So we can and should eliminate
 660                  *       this case. But I'll leave it here for now.
 661                  */
 662                 return 0xe59f0000 |
 663                     ((tinstr & (7<<8)) << (12-8)) |             /* Rd */
 664                     ((tinstr & 255) << (2-0));                  /* immed_8 */
 665
 666         /* 6.5.1 Format 4: */
 667         case 0x9000 >> 11:                              /* 7.1.54 STR(3) */
 668         case 0x9800 >> 11:                              /* 7.1.29 LDR(4) */
 669                 return 0xe58d0000 |
 670                         (L<<20) |                               /* L==1? */
 671                         ((tinstr & (7<<8)) << (12-8)) |         /* Rd */
 672                         ((tinstr & 255) << 2);                  /* immed_8 */
 673
 674         /* 6.6.1 Format 1: */
 675         case 0xc000 >> 11:                              /* 7.1.51 STMIA */
 676         case 0xc800 >> 11:                              /* 7.1.25 LDMIA */
 677                 {
 678                         u32 Rn = (tinstr & (7<<8)) >> 8;
 679                         u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
 680
 681                         return 0xe8800000 | W | (L<<20) | (Rn<<16) |
 682                                 (tinstr&255);
 683                 }
 684
 685         /* 6.6.1 Format 2: */
 686         case 0xb000 >> 11:                              /* 7.1.48 PUSH */
 687         case 0xb800 >> 11:                              /* 7.1.47 POP */
 688                 if ((tinstr & (3 << 9)) == 0x0400) {
 689                         static const u32 subset[4] = {
 690                                 0xe92d0000,     /* STMDB sp!,{registers} */
 691                                 0xe92d4000,     /* STMDB sp!,{registers,lr} */
 692                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
 693                                 0xe8bd8000      /* LDMIA sp!,{registers,pc} */
 694                         };
 695                         return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
 696                             (tinstr & 255);             /* register_list */
 697                 }
 698                 /* Else fall through for illegal instruction case */
 699
 700         default:
 701                 return BAD_INSTR;
 702         }
 703 }
 704
 705 /*
 706  * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
 707  * handlable by ARM alignment handler, also find the corresponding handler,
 708  * so that we can reuse ARM userland alignment fault fixups for Thumb.
 709  *
 710  * @pinstr: original Thumb-2 instruction; returns new handlable instruction
 711  * @regs: register context.
 712  * @poffset: return offset from faulted addr for later writeback
 713  *
 714  * NOTES:
 715  * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
 716  * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
 717  */
 718 static void *
 719 do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
 720                             union offset_union *poffset)
 721 {
 722         unsigned long instr = *pinstr;
 723         u16 tinst1 = (instr >> 16) & 0xffff;
 724         u16 tinst2 = instr & 0xffff;
 725
 726         switch (tinst1 & 0xffe0) {
 727         /* A6.3.5 Load/Store multiple */
 728         case 0xe880:            /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
 729         case 0xe8a0:            /* ...above writeback version */
 730         case 0xe900:            /* STMDB/STMFD, LDMDB/LDMEA */
 731         case 0xe920:            /* ...above writeback version */
 732                 /* no need offset decision since handler calculates it */
 733                 return do_alignment_ldmstm;
 734
 735         case 0xf840:            /* POP/PUSH T3 (single register) */
 736                 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
 737                         u32 L = !!(LDST_L_BIT(instr));
 738                         const u32 subset[2] = {
 739                                 0xe92d0000,     /* STMDB sp!,{registers} */
 740                                 0xe8bd0000,     /* LDMIA sp!,{registers} */
 741                         };
 742                         *pinstr = subset[L] | (1<<RD_BITS(instr));
 743                         return do_alignment_ldmstm;
 744                 }
 745                 /* Else fall through for illegal instruction case */
 746                 break;
 747
 748         /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
 749         case 0xe860:
 750         case 0xe960:
 751         case 0xe8e0:
 752         case 0xe9e0:
 753                 poffset->un = (tinst2 & 0xff) << 2;
 754         case 0xe940:
 755         case 0xe9c0:
 756                 return do_alignment_ldrdstrd;
 757
 758         /*
 759          * No need to handle load/store instructions up to word size
 760          * since ARMv6 and later CPUs can perform unaligned accesses.
 761          */
 762         default:
 763                 break;
 764         }
 765         return NULL;
 766 }
 767
 768 static int
 769 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 770 {
 771         union offset_union uninitialized_var(offset);
 772         unsigned long instr = 0, instrptr;
 773         int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
 774         unsigned int type;
 775         unsigned int fault;
 776         u16 tinstr = 0;
 777         int isize = 4;
 778         int thumb2_32b = 0;
 779
 780         if (interrupts_enabled(regs))
 781                 local_irq_enable();
 782
 783         instrptr = instruction_pointer(regs);
 784
 785         if (thumb_mode(regs)) {
 786                 u16 *ptr = (u16 *)(instrptr & ~1);
 787                 fault = probe_kernel_address(ptr, tinstr);
 788                 tinstr = __mem_to_opcode_thumb16(tinstr);
 789                 if (!fault) {
 790                         if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
 791                             IS_T32(tinstr)) {
 792                                 /* Thumb-2 32-bit */
 793                                 u16 tinst2 = 0;
 794                                 fault = probe_kernel_address(ptr + 1, tinst2);
 795                                 tinst2 = __mem_to_opcode_thumb16(tinst2);
 796                                 instr = __opcode_thumb32_compose(tinstr, tinst2);
 797                                 thumb2_32b = 1;
 798                         } else {
 799                                 isize = 2;
 800                                 instr = thumb2arm(tinstr);
 801                         }
 802                 }
 803         } else {
 804                 fault = probe_kernel_address((void *)instrptr, instr);
 805                 instr = __mem_to_opcode_arm(instr);
 806         }
 807
 808         if (fault) {
 809                 type = TYPE_FAULT;
 810                 goto bad_or_fault;
 811         }
 812
 813         if (user_mode(regs))
 814                 goto user;
 815
 816         ai_sys += 1;
 817         ai_sys_last_pc = (void *)instruction_pointer(regs);
 818
 819  fixup:
 820
 821         regs->ARM_pc += isize;
 822
 823         switch (CODING_BITS(instr)) {
 824         case 0x00000000:        /* 3.13.4 load/store instruction extensions */
 825                 if (LDSTHD_I_BIT(instr))
 826                         offset.un = (instr & 0xf00) >> 4 | (instr & 15);
 827                 else
 828                         offset.un = regs->uregs[RM_BITS(instr)];
 829
 830                 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
 831                     (instr & 0x001000f0) == 0x001000f0)   /* LDRSH */
 832                         handler = do_alignment_ldrhstrh;
 833                 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
 834                          (instr & 0x001000f0) == 0x000000f0)   /* STRD */
 835                         handler = do_alignment_ldrdstrd;
 836                 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
 837                         goto swp;
 838                 else
 839                         goto bad;
 840                 break;
 841
 842         case 0x04000000:        /* ldr or str immediate */
 843                 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
 844                         goto bad;
 845                 offset.un = OFFSET_BITS(instr);
 846                 handler = do_alignment_ldrstr;
 847                 break;
 848
 849         case 0x06000000:        /* ldr or str register */
 850                 offset.un = regs->uregs[RM_BITS(instr)];
 851
 852                 if (IS_SHIFT(instr)) {
 853                         unsigned int shiftval = SHIFT_BITS(instr);
 854
 855                         switch(SHIFT_TYPE(instr)) {
 856                         case SHIFT_LSL:
 857                                 offset.un <<= shiftval;
 858                                 break;
 859
 860                         case SHIFT_LSR:
 861                                 offset.un >>= shiftval;
 862                                 break;
 863
 864                         case SHIFT_ASR:
 865                                 offset.sn >>= shiftval;
 866                                 break;
 867
 868                         case SHIFT_RORRRX:
 869                                 if (shiftval == 0) {
 870                                         offset.un >>= 1;
 871                                         if (regs->ARM_cpsr & PSR_C_BIT)
 872                                                 offset.un |= 1 << 31;
 873                                 } else
 874                                         offset.un = offset.un >> shiftval |
 875                                                           offset.un << (32 - shiftval);
 876                                 break;
 877                         }
 878                 }
 879                 handler = do_alignment_ldrstr;
 880                 break;
 881
 882         case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
 883                 if (thumb2_32b) {
 884                         offset.un = 0;
 885                         handler = do_alignment_t32_to_handler(&instr, regs, &offset);
 886                 } else {
 887                         offset.un = 0;
 888                         handler = do_alignment_ldmstm;
 889                 }
 890                 break;
 891
 892         default:
 893                 goto bad;
 894         }
 895
 896         if (!handler)
 897                 goto bad;
 898         type = handler(addr, instr, regs);
 899
 900         if (type == TYPE_ERROR || type == TYPE_FAULT) {
 901                 regs->ARM_pc -= isize;
 902                 goto bad_or_fault;
 903         }
 904
 905         if (type == TYPE_LDST)
 906                 do_alignment_finish_ldst(addr, instr, regs, offset);
 907
 908         return 0;
 909
 910  bad_or_fault:
 911         if (type == TYPE_ERROR)
 912                 goto bad;
 913         /*
 914          * We got a fault - fix it up, or die.
 915          */
 916         do_bad_area(addr, fsr, regs);
 917         return 0;
 918
 919  swp:
 920         pr_err("Alignment trap: not handling swp instruction\n");
 921
 922  bad:
 923         /*
 924          * Oops, we didn't handle the instruction.
 925          */
 926         pr_err("Alignment trap: not handling instruction "
 927                 "%0*lx at [<%08lx>]\n",
 928                 isize << 1,
 929                 isize == 2 ? tinstr : instr, instrptr);
 930         ai_skipped += 1;
 931         return 1;
 932
 933  user:
 934         ai_user += 1;
 935
 936         if (ai_usermode & UM_WARN)
 937                 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
 938                        "Address=0x%08lx FSR 0x%03x\n", current->comm,
 939                         task_pid_nr(current), instrptr,
 940                         isize << 1,
 941                         isize == 2 ? tinstr : instr,
 942                         addr, fsr);
 943
 944         if (ai_usermode & UM_FIXUP)
 945                 goto fixup;
 946
 947         if (ai_usermode & UM_SIGNAL) {
 948                 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)addr);
 949         } else {
 950                 /*
 951                  * We're about to disable the alignment trap and return to
 952                  * user space.  But if an interrupt occurs before actually
 953                  * reaching user space, then the IRQ vector entry code will
 954                  * notice that we were still in kernel space and therefore
 955                  * the alignment trap won't be re-enabled in that case as it
 956                  * is presumed to be always on from kernel space.
 957                  * Let's prevent that race by disabling interrupts here (they
 958                  * are disabled on the way back to user space anyway in
 959                  * entry-common.S) and disable the alignment trap only if
 960                  * there is no work pending for this thread.
 961                  */
 962                 raw_local_irq_disable();
 963                 if (!(current_thread_info()->flags & _TIF_WORK_MASK))
 964                         set_cr(cr_no_alignment);
 965         }
 966
 967         return 0;
 968 }
 969
 970 static int __init noalign_setup(char *__unused)
 971 {
 972         set_cr(__clear_cr(CR_A));
 973         return 1;
 974 }
 975 __setup("noalign", noalign_setup);
 976
 977 /*
 978  * This needs to be done after sysctl_init, otherwise sys/ will be
 979  * overwritten.  Actually, this shouldn't be in sys/ at all since
 980  * it isn't a sysctl, and it doesn't contain sysctl information.
 981  * We now locate it in /proc/cpu/alignment instead.
 982  */
 983 static int __init alignment_init(void)
 984 {
 985 #ifdef CONFIG_PROC_FS
 986         struct proc_dir_entry *res;
 987
 988         res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
 989                           &alignment_proc_fops);
 990         if (!res)
 991                 return -ENOMEM;
 992 #endif
 993
 994         if (cpu_is_v6_unaligned()) {
 995                 set_cr(__clear_cr(CR_A));
 996                 ai_usermode = safe_usermode(ai_usermode, false);
 997         }
 998
 999         cr_no_alignment = get_cr() & ~CR_A;
1000
1001         hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
1002                         "alignment exception");
1003
1004         /*
1005          * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
1006          * fault, not as alignment error.
1007          *
1008          * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
1009          * needed.
1010          */
1011         if (cpu_architecture() <= CPU_ARCH_ARMv6) {
1012                 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
1013                                 "alignment exception");
1014         }
1015
1016         return 0;
1017 }
1018
1019 fs_initcall(alignment_init);