arch/arm/mach-vexpress/ct-ca9x4.c

   1 /*
   2  * Versatile Express Core Tile Cortex A9x4 Support
   3  */
   4 #include <linux/init.h>
   5 #include <linux/gfp.h>
   6 #include <linux/device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/amba/bus.h>
  10 #include <linux/amba/clcd.h>
  11 #include <linux/clkdev.h>
  12
  13 #include <asm/hardware/arm_timer.h>
  14 #include <asm/hardware/cache-l2x0.h>
  15 #include <asm/hardware/gic.h>
  16 #include <asm/pmu.h>
  17 #include <asm/smp_scu.h>
  18 #include <asm/smp_twd.h>
  19
  20 #include <mach/ct-ca9x4.h>
  21
  22 #include <asm/hardware/timer-sp.h>
  23
  24 #include <asm/mach/map.h>
  25 #include <asm/mach/time.h>
  26
  27 #include "core.h"
  28
  29 #include <mach/motherboard.h>
  30
  31 #include <plat/clcd.h>
  32
  33 #define V2M_PA_CS7      0x10000000
  34
  35 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
  36         {
  37                 .virtual        = __MMIO_P2V(CT_CA9X4_MPIC),
  38                 .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
  39                 .length         = SZ_16K,
  40                 .type           = MT_DEVICE,
  41         }, {
  42                 .virtual        = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
  43                 .pfn            = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
  44                 .length         = SZ_4K,
  45                 .type           = MT_DEVICE,
  46         }, {
  47                 .virtual        = __MMIO_P2V(CT_CA9X4_L2CC),
  48                 .pfn            = __phys_to_pfn(CT_CA9X4_L2CC),
  49                 .length         = SZ_4K,
  50                 .type           = MT_DEVICE,
  51         },
  52 };
  53
  54 static void __init ct_ca9x4_map_io(void)
  55 {
  56 #ifdef CONFIG_LOCAL_TIMERS
  57         twd_base = MMIO_P2V(A9_MPCORE_TWD);
  58 #endif
  59         iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
  60 }
  61
  62 static void __init ct_ca9x4_init_irq(void)
  63 {
  64         gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
  65                  MMIO_P2V(A9_MPCORE_GIC_CPU));
  66 }
  67
  68 #if 0
  69 static void __init ct_ca9x4_timer_init(void)
  70 {
  71         writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
  72         writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
  73
  74         sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
  75         sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
  76 }
  77
  78 static struct sys_timer ct_ca9x4_timer = {
  79         .init   = ct_ca9x4_timer_init,
  80 };
  81 #endif
  82
  83 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
  84 {
  85         v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
  86         v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
  87 }
  88
  89 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
  90 {
  91         unsigned long framesize = 1024 * 768 * 2;
  92
  93         fb->panel = versatile_clcd_get_panel("XVGA");
  94         if (!fb->panel)
  95                 return -EINVAL;
  96
  97         return versatile_clcd_setup_dma(fb, framesize);
  98 }
  99
 100 static struct clcd_board ct_ca9x4_clcd_data = {
 101         .name           = "CT-CA9X4",
 102         .caps           = CLCD_CAP_5551 | CLCD_CAP_565,
 103         .check          = clcdfb_check,
 104         .decode         = clcdfb_decode,
 105         .enable         = ct_ca9x4_clcd_enable,
 106         .setup          = ct_ca9x4_clcd_setup,
 107         .mmap           = versatile_clcd_mmap_dma,
 108         .remove         = versatile_clcd_remove_dma,
 109 };
 110
 111 static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
 112 static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
 113 static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
 114 static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
 115
 116 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 117         &clcd_device,
 118         &dmc_device,
 119         &smc_device,
 120         &gpio_device,
 121 };
 122
 123
 124 static long ct_round(struct clk *clk, unsigned long rate)
 125 {
 126         return rate;
 127 }
 128
 129 static int ct_set(struct clk *clk, unsigned long rate)
 130 {
 131         return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
 132 }
 133
 134 static const struct clk_ops osc1_clk_ops = {
 135         .round  = ct_round,
 136         .set    = ct_set,
 137 };
 138
 139 static struct clk osc1_clk = {
 140         .ops    = &osc1_clk_ops,
 141         .rate   = 24000000,
 142 };
 143
 144 static struct clk ct_sp804_clk = {
 145         .rate   = 1000000,
 146 };
 147
 148 static struct clk_lookup lookups[] = {
 149         {       /* CLCD */
 150                 .dev_id         = "ct:clcd",
 151                 .clk            = &osc1_clk,
 152         }, {    /* SP804 timers */
 153                 .dev_id         = "sp804",
 154                 .con_id         = "ct-timer1",
 155                 .clk            = &ct_sp804_clk,
 156         },
 157 };
 158
 159 static struct resource pmu_resources[] = {
 160         [0] = {
 161                 .start  = IRQ_CT_CA9X4_PMU_CPU0,
 162                 .end    = IRQ_CT_CA9X4_PMU_CPU0,
 163                 .flags  = IORESOURCE_IRQ,
 164         },
 165         [1] = {
 166                 .start  = IRQ_CT_CA9X4_PMU_CPU1,
 167                 .end    = IRQ_CT_CA9X4_PMU_CPU1,
 168                 .flags  = IORESOURCE_IRQ,
 169         },
 170         [2] = {
 171                 .start  = IRQ_CT_CA9X4_PMU_CPU2,
 172                 .end    = IRQ_CT_CA9X4_PMU_CPU2,
 173                 .flags  = IORESOURCE_IRQ,
 174         },
 175         [3] = {
 176                 .start  = IRQ_CT_CA9X4_PMU_CPU3,
 177                 .end    = IRQ_CT_CA9X4_PMU_CPU3,
 178                 .flags  = IORESOURCE_IRQ,
 179         },
 180 };
 181
 182 static struct platform_device pmu_device = {
 183         .name           = "arm-pmu",
 184         .id             = ARM_PMU_DEVICE_CPU,
 185         .num_resources  = ARRAY_SIZE(pmu_resources),
 186         .resource       = pmu_resources,
 187 };
 188
 189 static void __init ct_ca9x4_init_early(void)
 190 {
 191         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 192 }
 193
 194 static void __init ct_ca9x4_init(void)
 195 {
 196         int i;
 197
 198 #ifdef CONFIG_CACHE_L2X0
 199         void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
 200
 201         /* set RAM latencies to 1 cycle for this core tile. */
 202         writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
 203         writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
 204
 205         l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 206 #endif
 207
 208         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
 209                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 210
 211         platform_device_register(&pmu_device);
 212 }
 213
 214 #ifdef CONFIG_SMP
 215 static void ct_ca9x4_init_cpu_map(void)
 216 {
 217         int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
 218
 219         for (i = 0; i < ncores; ++i)
 220                 set_cpu_possible(i, true);
 221 }
 222
 223 static void ct_ca9x4_smp_enable(unsigned int max_cpus)
 224 {
 225         int i;
 226         for (i = 0; i < max_cpus; i++)
 227                 set_cpu_present(i, true);
 228
 229         scu_enable(MMIO_P2V(A9_MPCORE_SCU));
 230 }
 231 #endif
 232
 233 struct ct_desc ct_ca9x4_desc __initdata = {
 234         .id             = V2M_CT_ID_CA9,
 235         .name           = "CA9x4",
 236         .map_io         = ct_ca9x4_map_io,
 237         .init_early     = ct_ca9x4_init_early,
 238         .init_irq       = ct_ca9x4_init_irq,
 239         .init_tile      = ct_ca9x4_init,
 240 #ifdef CONFIG_SMP
 241         .init_cpu_map   = ct_ca9x4_init_cpu_map,
 242         .smp_enable     = ct_ca9x4_smp_enable,
 243 #endif
 244 };