arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2012 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/amba/serial.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/gpio.h>
  25 #include <linux/clk.h>
  26 #include <linux/err.h>
  27 #include <linux/mtd/nand.h>
  28 #include <linux/mtd/fsmc.h>
  29 #include <linux/pinctrl/machine.h>
  30 #include <linux/pinctrl/consumer.h>
  31 #include <linux/pinctrl/pinconf-generic.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/platform_data/clk-u300.h>
  34 #include <linux/platform_data/pinctrl-coh901.h>
  35
  36 #include <asm/types.h>
  37 #include <asm/setup.h>
  38 #include <asm/memory.h>
  39 #include <asm/hardware/vic.h>
  40 #include <asm/mach/map.h>
  41 #include <asm/mach-types.h>
  42 #include <asm/mach/arch.h>
  43
  44 #include <mach/coh901318.h>
  45 #include <mach/hardware.h>
  46 #include <mach/syscon.h>
  47 #include <mach/irqs.h>
  48
  49 #include "timer.h"
  50 #include "spi.h"
  51 #include "i2c.h"
  52 #include "u300-gpio.h"
  53 #include "dma_channels.h"
  54
  55 /*
  56  * Static I/O mappings that are needed for booting the U300 platforms. The
  57  * only things we need are the areas where we find the timer, syscon and
  58  * intcon, since the remaining device drivers will map their own memory
  59  * physical to virtual as the need arise.
  60  */
  61 static struct map_desc u300_io_desc[] __initdata = {
  62         {
  63                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  64                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  65                 .length         = SZ_64K,
  66                 .type           = MT_DEVICE,
  67         },
  68         {
  69                 .virtual        = U300_AHB_PER_VIRT_BASE,
  70                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  71                 .length         = SZ_32K,
  72                 .type           = MT_DEVICE,
  73         },
  74         {
  75                 .virtual        = U300_FAST_PER_VIRT_BASE,
  76                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  77                 .length         = SZ_32K,
  78                 .type           = MT_DEVICE,
  79         },
  80 };
  81
  82 static void __init u300_map_io(void)
  83 {
  84         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  85 }
  86
  87 /*
  88  * Declaration of devices found on the U300 board and
  89  * their respective memory locations.
  90  */
  91
  92 static struct amba_pl011_data uart0_plat_data = {
  93 #ifdef CONFIG_COH901318
  94         .dma_filter = coh901318_filter_id,
  95         .dma_rx_param = (void *) U300_DMA_UART0_RX,
  96         .dma_tx_param = (void *) U300_DMA_UART0_TX,
  97 #endif
  98 };
  99
 100 /* Slow device at 0x3000 offset */
 101 static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
 102         { IRQ_U300_UART0 }, &uart0_plat_data);
 103
 104 /* The U335 have an additional UART1 on the APP CPU */
 105 static struct amba_pl011_data uart1_plat_data = {
 106 #ifdef CONFIG_COH901318
 107         .dma_filter = coh901318_filter_id,
 108         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 109         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 110 #endif
 111 };
 112
 113 /* Fast device at 0x7000 offset */
 114 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
 115         { IRQ_U300_UART1 }, &uart1_plat_data);
 116
 117 /* AHB device at 0x4000 offset */
 118 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
 119
 120 /* Fast device at 0x6000 offset */
 121 static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
 122         { IRQ_U300_SPI }, NULL);
 123
 124 /* Fast device at 0x1000 offset */
 125 #define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
 126
 127 static struct mmci_platform_data mmcsd_platform_data = {
 128         /*
 129          * Do not set ocr_mask or voltage translation function,
 130          * we have a regulator we can control instead.
 131          */
 132         .f_max = 24000000,
 133         .gpio_wp = -1,
 134         .gpio_cd = U300_GPIO_PIN_MMC_CD,
 135         .cd_invert = true,
 136         .capabilities = MMC_CAP_MMC_HIGHSPEED |
 137         MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 138 #ifdef CONFIG_COH901318
 139         .dma_filter = coh901318_filter_id,
 140         .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
 141         /* Don't specify a TX channel, this RX channel is bidirectional */
 142 #endif
 143 };
 144
 145 static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
 146         U300_MMCSD_IRQS, &mmcsd_platform_data);
 147
 148 /*
 149  * The order of device declaration may be important, since some devices
 150  * have dependencies on other devices being initialized first.
 151  */
 152 static struct amba_device *amba_devs[] __initdata = {
 153         &uart0_device,
 154         &uart1_device,
 155         &pl022_device,
 156         &pl172_device,
 157         &mmcsd_device,
 158 };
 159
 160 /* Here follows a list of all hw resources that the platform devices
 161  * allocate. Note, clock dependencies are not included
 162  */
 163
 164 static struct resource gpio_resources[] = {
 165         {
 166                 .start = U300_GPIO_BASE,
 167                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 168                 .flags = IORESOURCE_MEM,
 169         },
 170         {
 171                 .name  = "gpio0",
 172                 .start = IRQ_U300_GPIO_PORT0,
 173                 .end   = IRQ_U300_GPIO_PORT0,
 174                 .flags = IORESOURCE_IRQ,
 175         },
 176         {
 177                 .name  = "gpio1",
 178                 .start = IRQ_U300_GPIO_PORT1,
 179                 .end   = IRQ_U300_GPIO_PORT1,
 180                 .flags = IORESOURCE_IRQ,
 181         },
 182         {
 183                 .name  = "gpio2",
 184                 .start = IRQ_U300_GPIO_PORT2,
 185                 .end   = IRQ_U300_GPIO_PORT2,
 186                 .flags = IORESOURCE_IRQ,
 187         },
 188         {
 189                 .name  = "gpio3",
 190                 .start = IRQ_U300_GPIO_PORT3,
 191                 .end   = IRQ_U300_GPIO_PORT3,
 192                 .flags = IORESOURCE_IRQ,
 193         },
 194         {
 195                 .name  = "gpio4",
 196                 .start = IRQ_U300_GPIO_PORT4,
 197                 .end   = IRQ_U300_GPIO_PORT4,
 198                 .flags = IORESOURCE_IRQ,
 199         },
 200         {
 201                 .name  = "gpio5",
 202                 .start = IRQ_U300_GPIO_PORT5,
 203                 .end   = IRQ_U300_GPIO_PORT5,
 204                 .flags = IORESOURCE_IRQ,
 205         },
 206         {
 207                 .name  = "gpio6",
 208                 .start = IRQ_U300_GPIO_PORT6,
 209                 .end   = IRQ_U300_GPIO_PORT6,
 210                 .flags = IORESOURCE_IRQ,
 211         },
 212 };
 213
 214 static struct resource keypad_resources[] = {
 215         {
 216                 .start = U300_KEYPAD_BASE,
 217                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 218                 .flags = IORESOURCE_MEM,
 219         },
 220         {
 221                 .name  = "coh901461-press",
 222                 .start = IRQ_U300_KEYPAD_KEYBF,
 223                 .end   = IRQ_U300_KEYPAD_KEYBF,
 224                 .flags = IORESOURCE_IRQ,
 225         },
 226         {
 227                 .name  = "coh901461-release",
 228                 .start = IRQ_U300_KEYPAD_KEYBR,
 229                 .end   = IRQ_U300_KEYPAD_KEYBR,
 230                 .flags = IORESOURCE_IRQ,
 231         },
 232 };
 233
 234 static struct resource rtc_resources[] = {
 235         {
 236                 .start = U300_RTC_BASE,
 237                 .end   = U300_RTC_BASE + SZ_4K - 1,
 238                 .flags = IORESOURCE_MEM,
 239         },
 240         {
 241                 .start = IRQ_U300_RTC,
 242                 .end   = IRQ_U300_RTC,
 243                 .flags = IORESOURCE_IRQ,
 244         },
 245 };
 246
 247 /*
 248  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 249  * but these are not yet used by the driver.
 250  */
 251 static struct resource fsmc_resources[] = {
 252         {
 253                 .name  = "nand_addr",
 254                 .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
 255                 .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
 256                 .flags = IORESOURCE_MEM,
 257         },
 258         {
 259                 .name  = "nand_cmd",
 260                 .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
 261                 .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
 262                 .flags = IORESOURCE_MEM,
 263         },
 264         {
 265                 .name  = "nand_data",
 266                 .start = U300_NAND_CS0_PHYS_BASE,
 267                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 268                 .flags = IORESOURCE_MEM,
 269         },
 270         {
 271                 .name  = "fsmc_regs",
 272                 .start = U300_NAND_IF_PHYS_BASE,
 273                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 274                 .flags = IORESOURCE_MEM,
 275         },
 276 };
 277
 278 static struct resource i2c0_resources[] = {
 279         {
 280                 .start = U300_I2C0_BASE,
 281                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 282                 .flags = IORESOURCE_MEM,
 283         },
 284         {
 285                 .start = IRQ_U300_I2C0,
 286                 .end   = IRQ_U300_I2C0,
 287                 .flags = IORESOURCE_IRQ,
 288         },
 289 };
 290
 291 static struct resource i2c1_resources[] = {
 292         {
 293                 .start = U300_I2C1_BASE,
 294                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 295                 .flags = IORESOURCE_MEM,
 296         },
 297         {
 298                 .start = IRQ_U300_I2C1,
 299                 .end   = IRQ_U300_I2C1,
 300                 .flags = IORESOURCE_IRQ,
 301         },
 302
 303 };
 304
 305 static struct resource wdog_resources[] = {
 306         {
 307                 .start = U300_WDOG_BASE,
 308                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 309                 .flags = IORESOURCE_MEM,
 310         },
 311         {
 312                 .start = IRQ_U300_WDOG,
 313                 .end   = IRQ_U300_WDOG,
 314                 .flags = IORESOURCE_IRQ,
 315         }
 316 };
 317
 318 static struct resource dma_resource[] = {
 319         {
 320                 .start = U300_DMAC_BASE,
 321                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 322                 .flags =  IORESOURCE_MEM,
 323         },
 324         {
 325                 .start = IRQ_U300_DMA,
 326                 .end = IRQ_U300_DMA,
 327                 .flags =  IORESOURCE_IRQ,
 328         }
 329 };
 330
 331 /* points out all dma slave channels.
 332  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 333  * Select all channels from A to B, end of list is marked with -1,-1
 334  */
 335 static int dma_slave_channels[] = {
 336         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 337         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 338
 339 /* points out all dma memcpy channels. */
 340 static int dma_memcpy_channels[] = {
 341         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 342
 343 /** register dma for memory access
 344  *
 345  * active  1 means dma intends to access memory
 346  *         0 means dma wont access memory
 347  */
 348 static void coh901318_access_memory_state(struct device *dev, bool active)
 349 {
 350 }
 351
 352 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 353                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 354                         COH901318_CX_CFG_LCR_DISABLE | \
 355                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 356                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 357 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 358                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 359                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 360                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 361                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 362                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 363                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 364                         COH901318_CX_CTRL_TCP_DISABLE | \
 365                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 366                         COH901318_CX_CTRL_HSP_DISABLE | \
 367                         COH901318_CX_CTRL_HSS_DISABLE | \
 368                         COH901318_CX_CTRL_DDMA_LEGACY | \
 369                         COH901318_CX_CTRL_PRDD_SOURCE)
 370 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 371                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 372                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 373                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 374                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 375                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 376                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 377                         COH901318_CX_CTRL_TCP_DISABLE | \
 378                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 379                         COH901318_CX_CTRL_HSP_DISABLE | \
 380                         COH901318_CX_CTRL_HSS_DISABLE | \
 381                         COH901318_CX_CTRL_DDMA_LEGACY | \
 382                         COH901318_CX_CTRL_PRDD_SOURCE)
 383 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 384                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 385                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 386                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 387                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 388                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 389                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 390                         COH901318_CX_CTRL_TCP_DISABLE | \
 391                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 392                         COH901318_CX_CTRL_HSP_DISABLE | \
 393                         COH901318_CX_CTRL_HSS_DISABLE | \
 394                         COH901318_CX_CTRL_DDMA_LEGACY | \
 395                         COH901318_CX_CTRL_PRDD_SOURCE)
 396
 397 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 398         {
 399                 .number = U300_DMA_MSL_TX_0,
 400                 .name = "MSL TX 0",
 401                 .priority_high = 0,
 402                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 403         },
 404         {
 405                 .number = U300_DMA_MSL_TX_1,
 406                 .name = "MSL TX 1",
 407                 .priority_high = 0,
 408                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 409                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 410                                 COH901318_CX_CFG_LCR_DISABLE |
 411                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 412                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 413                 .param.ctrl_lli_chained = 0 |
 414                                 COH901318_CX_CTRL_TC_ENABLE |
 415                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 416                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 417                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 418                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 419                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 420                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 421                                 COH901318_CX_CTRL_TCP_DISABLE |
 422                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 423                                 COH901318_CX_CTRL_HSP_ENABLE |
 424                                 COH901318_CX_CTRL_HSS_DISABLE |
 425                                 COH901318_CX_CTRL_DDMA_LEGACY |
 426                                 COH901318_CX_CTRL_PRDD_SOURCE,
 427                 .param.ctrl_lli = 0 |
 428                                 COH901318_CX_CTRL_TC_ENABLE |
 429                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 430                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 431                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 432                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 433                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 434                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 435                                 COH901318_CX_CTRL_TCP_ENABLE |
 436                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 437                                 COH901318_CX_CTRL_HSP_ENABLE |
 438                                 COH901318_CX_CTRL_HSS_DISABLE |
 439                                 COH901318_CX_CTRL_DDMA_LEGACY |
 440                                 COH901318_CX_CTRL_PRDD_SOURCE,
 441                 .param.ctrl_lli_last = 0 |
 442                                 COH901318_CX_CTRL_TC_ENABLE |
 443                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 444                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 445                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 446                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 447                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 448                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 449                                 COH901318_CX_CTRL_TCP_ENABLE |
 450                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 451                                 COH901318_CX_CTRL_HSP_ENABLE |
 452                                 COH901318_CX_CTRL_HSS_DISABLE |
 453                                 COH901318_CX_CTRL_DDMA_LEGACY |
 454                                 COH901318_CX_CTRL_PRDD_SOURCE,
 455         },
 456         {
 457                 .number = U300_DMA_MSL_TX_2,
 458                 .name = "MSL TX 2",
 459                 .priority_high = 0,
 460                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 461                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 462                                 COH901318_CX_CFG_LCR_DISABLE |
 463                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 464                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 465                 .param.ctrl_lli_chained = 0 |
 466                                 COH901318_CX_CTRL_TC_ENABLE |
 467                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 468                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 469                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 470                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 471                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 472                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 473                                 COH901318_CX_CTRL_TCP_DISABLE |
 474                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 475                                 COH901318_CX_CTRL_HSP_ENABLE |
 476                                 COH901318_CX_CTRL_HSS_DISABLE |
 477                                 COH901318_CX_CTRL_DDMA_LEGACY |
 478                                 COH901318_CX_CTRL_PRDD_SOURCE,
 479                 .param.ctrl_lli = 0 |
 480                                 COH901318_CX_CTRL_TC_ENABLE |
 481                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 482                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 483                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 484                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 485                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 486                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 487                                 COH901318_CX_CTRL_TCP_ENABLE |
 488                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 489                                 COH901318_CX_CTRL_HSP_ENABLE |
 490                                 COH901318_CX_CTRL_HSS_DISABLE |
 491                                 COH901318_CX_CTRL_DDMA_LEGACY |
 492                                 COH901318_CX_CTRL_PRDD_SOURCE,
 493                 .param.ctrl_lli_last = 0 |
 494                                 COH901318_CX_CTRL_TC_ENABLE |
 495                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 496                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 497                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 498                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 499                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 500                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 501                                 COH901318_CX_CTRL_TCP_ENABLE |
 502                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 503                                 COH901318_CX_CTRL_HSP_ENABLE |
 504                                 COH901318_CX_CTRL_HSS_DISABLE |
 505                                 COH901318_CX_CTRL_DDMA_LEGACY |
 506                                 COH901318_CX_CTRL_PRDD_SOURCE,
 507                 .desc_nbr_max = 10,
 508         },
 509         {
 510                 .number = U300_DMA_MSL_TX_3,
 511                 .name = "MSL TX 3",
 512                 .priority_high = 0,
 513                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 514                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 515                                 COH901318_CX_CFG_LCR_DISABLE |
 516                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 517                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 518                 .param.ctrl_lli_chained = 0 |
 519                                 COH901318_CX_CTRL_TC_ENABLE |
 520                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 521                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 522                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 523                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 524                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 525                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 526                                 COH901318_CX_CTRL_TCP_DISABLE |
 527                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 528                                 COH901318_CX_CTRL_HSP_ENABLE |
 529                                 COH901318_CX_CTRL_HSS_DISABLE |
 530                                 COH901318_CX_CTRL_DDMA_LEGACY |
 531                                 COH901318_CX_CTRL_PRDD_SOURCE,
 532                 .param.ctrl_lli = 0 |
 533                                 COH901318_CX_CTRL_TC_ENABLE |
 534                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 535                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 536                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 537                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 538                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 539                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 540                                 COH901318_CX_CTRL_TCP_ENABLE |
 541                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 542                                 COH901318_CX_CTRL_HSP_ENABLE |
 543                                 COH901318_CX_CTRL_HSS_DISABLE |
 544                                 COH901318_CX_CTRL_DDMA_LEGACY |
 545                                 COH901318_CX_CTRL_PRDD_SOURCE,
 546                 .param.ctrl_lli_last = 0 |
 547                                 COH901318_CX_CTRL_TC_ENABLE |
 548                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 549                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 550                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 551                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 552                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 553                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 554                                 COH901318_CX_CTRL_TCP_ENABLE |
 555                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 556                                 COH901318_CX_CTRL_HSP_ENABLE |
 557                                 COH901318_CX_CTRL_HSS_DISABLE |
 558                                 COH901318_CX_CTRL_DDMA_LEGACY |
 559                                 COH901318_CX_CTRL_PRDD_SOURCE,
 560         },
 561         {
 562                 .number = U300_DMA_MSL_TX_4,
 563                 .name = "MSL TX 4",
 564                 .priority_high = 0,
 565                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 566                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 567                                 COH901318_CX_CFG_LCR_DISABLE |
 568                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 569                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 570                 .param.ctrl_lli_chained = 0 |
 571                                 COH901318_CX_CTRL_TC_ENABLE |
 572                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 573                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 574                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 575                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 576                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 577                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 578                                 COH901318_CX_CTRL_TCP_DISABLE |
 579                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 580                                 COH901318_CX_CTRL_HSP_ENABLE |
 581                                 COH901318_CX_CTRL_HSS_DISABLE |
 582                                 COH901318_CX_CTRL_DDMA_LEGACY |
 583                                 COH901318_CX_CTRL_PRDD_SOURCE,
 584                 .param.ctrl_lli = 0 |
 585                                 COH901318_CX_CTRL_TC_ENABLE |
 586                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 587                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 588                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 589                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 590                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 591                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 592                                 COH901318_CX_CTRL_TCP_ENABLE |
 593                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 594                                 COH901318_CX_CTRL_HSP_ENABLE |
 595                                 COH901318_CX_CTRL_HSS_DISABLE |
 596                                 COH901318_CX_CTRL_DDMA_LEGACY |
 597                                 COH901318_CX_CTRL_PRDD_SOURCE,
 598                 .param.ctrl_lli_last = 0 |
 599                                 COH901318_CX_CTRL_TC_ENABLE |
 600                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 601                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 602                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 603                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 604                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 605                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 606                                 COH901318_CX_CTRL_TCP_ENABLE |
 607                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 608                                 COH901318_CX_CTRL_HSP_ENABLE |
 609                                 COH901318_CX_CTRL_HSS_DISABLE |
 610                                 COH901318_CX_CTRL_DDMA_LEGACY |
 611                                 COH901318_CX_CTRL_PRDD_SOURCE,
 612         },
 613         {
 614                 .number = U300_DMA_MSL_TX_5,
 615                 .name = "MSL TX 5",
 616                 .priority_high = 0,
 617                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 618         },
 619         {
 620                 .number = U300_DMA_MSL_TX_6,
 621                 .name = "MSL TX 6",
 622                 .priority_high = 0,
 623                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 624         },
 625         {
 626                 .number = U300_DMA_MSL_RX_0,
 627                 .name = "MSL RX 0",
 628                 .priority_high = 0,
 629                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 630         },
 631         {
 632                 .number = U300_DMA_MSL_RX_1,
 633                 .name = "MSL RX 1",
 634                 .priority_high = 0,
 635                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 636                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 637                                 COH901318_CX_CFG_LCR_DISABLE |
 638                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 639                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 640                 .param.ctrl_lli_chained = 0 |
 641                                 COH901318_CX_CTRL_TC_ENABLE |
 642                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 643                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 644                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 645                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 646                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 647                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 648                                 COH901318_CX_CTRL_TCP_DISABLE |
 649                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 650                                 COH901318_CX_CTRL_HSP_ENABLE |
 651                                 COH901318_CX_CTRL_HSS_DISABLE |
 652                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 653                                 COH901318_CX_CTRL_PRDD_DEST,
 654                 .param.ctrl_lli = 0,
 655                 .param.ctrl_lli_last = 0 |
 656                                 COH901318_CX_CTRL_TC_ENABLE |
 657                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 658                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 659                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 660                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 661                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 662                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 663                                 COH901318_CX_CTRL_TCP_DISABLE |
 664                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 665                                 COH901318_CX_CTRL_HSP_ENABLE |
 666                                 COH901318_CX_CTRL_HSS_DISABLE |
 667                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 668                                 COH901318_CX_CTRL_PRDD_DEST,
 669         },
 670         {
 671                 .number = U300_DMA_MSL_RX_2,
 672                 .name = "MSL RX 2",
 673                 .priority_high = 0,
 674                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 675                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 676                                 COH901318_CX_CFG_LCR_DISABLE |
 677                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 678                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 679                 .param.ctrl_lli_chained = 0 |
 680                                 COH901318_CX_CTRL_TC_ENABLE |
 681                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 682                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 683                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 684                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 685                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 686                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 687                                 COH901318_CX_CTRL_TCP_DISABLE |
 688                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 689                                 COH901318_CX_CTRL_HSP_ENABLE |
 690                                 COH901318_CX_CTRL_HSS_DISABLE |
 691                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 692                                 COH901318_CX_CTRL_PRDD_DEST,
 693                 .param.ctrl_lli = 0 |
 694                                 COH901318_CX_CTRL_TC_ENABLE |
 695                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 696                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 697                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 698                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 699                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 700                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 701                                 COH901318_CX_CTRL_TCP_DISABLE |
 702                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 703                                 COH901318_CX_CTRL_HSP_ENABLE |
 704                                 COH901318_CX_CTRL_HSS_DISABLE |
 705                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 706                                 COH901318_CX_CTRL_PRDD_DEST,
 707                 .param.ctrl_lli_last = 0 |
 708                                 COH901318_CX_CTRL_TC_ENABLE |
 709                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 710                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 711                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 712                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 713                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 714                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 715                                 COH901318_CX_CTRL_TCP_DISABLE |
 716                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 717                                 COH901318_CX_CTRL_HSP_ENABLE |
 718                                 COH901318_CX_CTRL_HSS_DISABLE |
 719                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 720                                 COH901318_CX_CTRL_PRDD_DEST,
 721         },
 722         {
 723                 .number = U300_DMA_MSL_RX_3,
 724                 .name = "MSL RX 3",
 725                 .priority_high = 0,
 726                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 727                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 728                                 COH901318_CX_CFG_LCR_DISABLE |
 729                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 730                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 731                 .param.ctrl_lli_chained = 0 |
 732                                 COH901318_CX_CTRL_TC_ENABLE |
 733                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 734                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 735                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 736                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 737                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 738                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 739                                 COH901318_CX_CTRL_TCP_DISABLE |
 740                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 741                                 COH901318_CX_CTRL_HSP_ENABLE |
 742                                 COH901318_CX_CTRL_HSS_DISABLE |
 743                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 744                                 COH901318_CX_CTRL_PRDD_DEST,
 745                 .param.ctrl_lli = 0 |
 746                                 COH901318_CX_CTRL_TC_ENABLE |
 747                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 748                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 749                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 750                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 751                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 752                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 753                                 COH901318_CX_CTRL_TCP_DISABLE |
 754                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 755                                 COH901318_CX_CTRL_HSP_ENABLE |
 756                                 COH901318_CX_CTRL_HSS_DISABLE |
 757                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 758                                 COH901318_CX_CTRL_PRDD_DEST,
 759                 .param.ctrl_lli_last = 0 |
 760                                 COH901318_CX_CTRL_TC_ENABLE |
 761                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 762                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 763                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 764                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 765                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 766                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 767                                 COH901318_CX_CTRL_TCP_DISABLE |
 768                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 769                                 COH901318_CX_CTRL_HSP_ENABLE |
 770                                 COH901318_CX_CTRL_HSS_DISABLE |
 771                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 772                                 COH901318_CX_CTRL_PRDD_DEST,
 773         },
 774         {
 775                 .number = U300_DMA_MSL_RX_4,
 776                 .name = "MSL RX 4",
 777                 .priority_high = 0,
 778                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 779                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 780                                 COH901318_CX_CFG_LCR_DISABLE |
 781                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 782                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 783                 .param.ctrl_lli_chained = 0 |
 784                                 COH901318_CX_CTRL_TC_ENABLE |
 785                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 786                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 787                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 788                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 789                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 790                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 791                                 COH901318_CX_CTRL_TCP_DISABLE |
 792                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 793                                 COH901318_CX_CTRL_HSP_ENABLE |
 794                                 COH901318_CX_CTRL_HSS_DISABLE |
 795                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 796                                 COH901318_CX_CTRL_PRDD_DEST,
 797                 .param.ctrl_lli = 0 |
 798                                 COH901318_CX_CTRL_TC_ENABLE |
 799                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 800                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 801                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 802                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 803                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 804                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 805                                 COH901318_CX_CTRL_TCP_DISABLE |
 806                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 807                                 COH901318_CX_CTRL_HSP_ENABLE |
 808                                 COH901318_CX_CTRL_HSS_DISABLE |
 809                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 810                                 COH901318_CX_CTRL_PRDD_DEST,
 811                 .param.ctrl_lli_last = 0 |
 812                                 COH901318_CX_CTRL_TC_ENABLE |
 813                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 814                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 815                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 816                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 817                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 818                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 819                                 COH901318_CX_CTRL_TCP_DISABLE |
 820                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 821                                 COH901318_CX_CTRL_HSP_ENABLE |
 822                                 COH901318_CX_CTRL_HSS_DISABLE |
 823                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 824                                 COH901318_CX_CTRL_PRDD_DEST,
 825         },
 826         {
 827                 .number = U300_DMA_MSL_RX_5,
 828                 .name = "MSL RX 5",
 829                 .priority_high = 0,
 830                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 831                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 832                                 COH901318_CX_CFG_LCR_DISABLE |
 833                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 834                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 835                 .param.ctrl_lli_chained = 0 |
 836                                 COH901318_CX_CTRL_TC_ENABLE |
 837                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 838                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 839                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 840                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 841                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 842                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 843                                 COH901318_CX_CTRL_TCP_DISABLE |
 844                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 845                                 COH901318_CX_CTRL_HSP_ENABLE |
 846                                 COH901318_CX_CTRL_HSS_DISABLE |
 847                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 848                                 COH901318_CX_CTRL_PRDD_DEST,
 849                 .param.ctrl_lli = 0 |
 850                                 COH901318_CX_CTRL_TC_ENABLE |
 851                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 852                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 853                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 854                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 855                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 856                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 857                                 COH901318_CX_CTRL_TCP_DISABLE |
 858                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 859                                 COH901318_CX_CTRL_HSP_ENABLE |
 860                                 COH901318_CX_CTRL_HSS_DISABLE |
 861                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 862                                 COH901318_CX_CTRL_PRDD_DEST,
 863                 .param.ctrl_lli_last = 0 |
 864                                 COH901318_CX_CTRL_TC_ENABLE |
 865                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 866                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 867                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 868                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 869                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 870                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 871                                 COH901318_CX_CTRL_TCP_DISABLE |
 872                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 873                                 COH901318_CX_CTRL_HSP_ENABLE |
 874                                 COH901318_CX_CTRL_HSS_DISABLE |
 875                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 876                                 COH901318_CX_CTRL_PRDD_DEST,
 877         },
 878         {
 879                 .number = U300_DMA_MSL_RX_6,
 880                 .name = "MSL RX 6",
 881                 .priority_high = 0,
 882                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 883         },
 884         /*
 885          * Don't set up device address, burst count or size of src
 886          * or dst bus for this peripheral - handled by PrimeCell
 887          * DMA extension.
 888          */
 889         {
 890                 .number = U300_DMA_MMCSD_RX_TX,
 891                 .name = "MMCSD RX TX",
 892                 .priority_high = 0,
 893                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 894                                 COH901318_CX_CFG_LCR_DISABLE |
 895                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 896                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 897                 .param.ctrl_lli_chained = 0 |
 898                                 COH901318_CX_CTRL_TC_ENABLE |
 899                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 900                                 COH901318_CX_CTRL_TCP_ENABLE |
 901                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 902                                 COH901318_CX_CTRL_HSP_ENABLE |
 903                                 COH901318_CX_CTRL_HSS_DISABLE |
 904                                 COH901318_CX_CTRL_DDMA_LEGACY,
 905                 .param.ctrl_lli = 0 |
 906                                 COH901318_CX_CTRL_TC_ENABLE |
 907                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 908                                 COH901318_CX_CTRL_TCP_ENABLE |
 909                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 910                                 COH901318_CX_CTRL_HSP_ENABLE |
 911                                 COH901318_CX_CTRL_HSS_DISABLE |
 912                                 COH901318_CX_CTRL_DDMA_LEGACY,
 913                 .param.ctrl_lli_last = 0 |
 914                                 COH901318_CX_CTRL_TC_ENABLE |
 915                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 916                                 COH901318_CX_CTRL_TCP_DISABLE |
 917                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 918                                 COH901318_CX_CTRL_HSP_ENABLE |
 919                                 COH901318_CX_CTRL_HSS_DISABLE |
 920                                 COH901318_CX_CTRL_DDMA_LEGACY,
 921
 922         },
 923         {
 924                 .number = U300_DMA_MSPRO_TX,
 925                 .name = "MSPRO TX",
 926                 .priority_high = 0,
 927         },
 928         {
 929                 .number = U300_DMA_MSPRO_RX,
 930                 .name = "MSPRO RX",
 931                 .priority_high = 0,
 932         },
 933         /*
 934          * Don't set up device address, burst count or size of src
 935          * or dst bus for this peripheral - handled by PrimeCell
 936          * DMA extension.
 937          */
 938         {
 939                 .number = U300_DMA_UART0_TX,
 940                 .name = "UART0 TX",
 941                 .priority_high = 0,
 942                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 943                                 COH901318_CX_CFG_LCR_DISABLE |
 944                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 945                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 946                 .param.ctrl_lli_chained = 0 |
 947                                 COH901318_CX_CTRL_TC_ENABLE |
 948                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 949                                 COH901318_CX_CTRL_TCP_ENABLE |
 950                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 951                                 COH901318_CX_CTRL_HSP_ENABLE |
 952                                 COH901318_CX_CTRL_HSS_DISABLE |
 953                                 COH901318_CX_CTRL_DDMA_LEGACY,
 954                 .param.ctrl_lli = 0 |
 955                                 COH901318_CX_CTRL_TC_ENABLE |
 956                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 957                                 COH901318_CX_CTRL_TCP_ENABLE |
 958                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 959                                 COH901318_CX_CTRL_HSP_ENABLE |
 960                                 COH901318_CX_CTRL_HSS_DISABLE |
 961                                 COH901318_CX_CTRL_DDMA_LEGACY,
 962                 .param.ctrl_lli_last = 0 |
 963                                 COH901318_CX_CTRL_TC_ENABLE |
 964                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 965                                 COH901318_CX_CTRL_TCP_ENABLE |
 966                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 967                                 COH901318_CX_CTRL_HSP_ENABLE |
 968                                 COH901318_CX_CTRL_HSS_DISABLE |
 969                                 COH901318_CX_CTRL_DDMA_LEGACY,
 970         },
 971         {
 972                 .number = U300_DMA_UART0_RX,
 973                 .name = "UART0 RX",
 974                 .priority_high = 0,
 975                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 976                                 COH901318_CX_CFG_LCR_DISABLE |
 977                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 978                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 979                 .param.ctrl_lli_chained = 0 |
 980                                 COH901318_CX_CTRL_TC_ENABLE |
 981                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 982                                 COH901318_CX_CTRL_TCP_ENABLE |
 983                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 984                                 COH901318_CX_CTRL_HSP_ENABLE |
 985                                 COH901318_CX_CTRL_HSS_DISABLE |
 986                                 COH901318_CX_CTRL_DDMA_LEGACY,
 987                 .param.ctrl_lli = 0 |
 988                                 COH901318_CX_CTRL_TC_ENABLE |
 989                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 990                                 COH901318_CX_CTRL_TCP_ENABLE |
 991                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 992                                 COH901318_CX_CTRL_HSP_ENABLE |
 993                                 COH901318_CX_CTRL_HSS_DISABLE |
 994                                 COH901318_CX_CTRL_DDMA_LEGACY,
 995                 .param.ctrl_lli_last = 0 |
 996                                 COH901318_CX_CTRL_TC_ENABLE |
 997                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 998                                 COH901318_CX_CTRL_TCP_ENABLE |
 999                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1000                                 COH901318_CX_CTRL_HSP_ENABLE |
1001                                 COH901318_CX_CTRL_HSS_DISABLE |
1002                                 COH901318_CX_CTRL_DDMA_LEGACY,
1003         },
1004         {
1005                 .number = U300_DMA_APEX_TX,
1006                 .name = "APEX TX",
1007                 .priority_high = 0,
1008         },
1009         {
1010                 .number = U300_DMA_APEX_RX,
1011                 .name = "APEX RX",
1012                 .priority_high = 0,
1013         },
1014         {
1015                 .number = U300_DMA_PCM_I2S0_TX,
1016                 .name = "PCM I2S0 TX",
1017                 .priority_high = 1,
1018                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1019                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1020                                 COH901318_CX_CFG_LCR_DISABLE |
1021                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1022                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1023                 .param.ctrl_lli_chained = 0 |
1024                                 COH901318_CX_CTRL_TC_ENABLE |
1025                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1026                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1027                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1028                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1029                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1030                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1031                                 COH901318_CX_CTRL_TCP_DISABLE |
1032                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1033                                 COH901318_CX_CTRL_HSP_ENABLE |
1034                                 COH901318_CX_CTRL_HSS_DISABLE |
1035                                 COH901318_CX_CTRL_DDMA_LEGACY |
1036                                 COH901318_CX_CTRL_PRDD_SOURCE,
1037                 .param.ctrl_lli = 0 |
1038                                 COH901318_CX_CTRL_TC_ENABLE |
1039                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1040                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1041                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1042                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1043                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1044                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1045                                 COH901318_CX_CTRL_TCP_ENABLE |
1046                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1047                                 COH901318_CX_CTRL_HSP_ENABLE |
1048                                 COH901318_CX_CTRL_HSS_DISABLE |
1049                                 COH901318_CX_CTRL_DDMA_LEGACY |
1050                                 COH901318_CX_CTRL_PRDD_SOURCE,
1051                 .param.ctrl_lli_last = 0 |
1052                                 COH901318_CX_CTRL_TC_ENABLE |
1053                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1054                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1055                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1056                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1057                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1058                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1059                                 COH901318_CX_CTRL_TCP_ENABLE |
1060                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1061                                 COH901318_CX_CTRL_HSP_ENABLE |
1062                                 COH901318_CX_CTRL_HSS_DISABLE |
1063                                 COH901318_CX_CTRL_DDMA_LEGACY |
1064                                 COH901318_CX_CTRL_PRDD_SOURCE,
1065         },
1066         {
1067                 .number = U300_DMA_PCM_I2S0_RX,
1068                 .name = "PCM I2S0 RX",
1069                 .priority_high = 1,
1070                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1071                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1072                                 COH901318_CX_CFG_LCR_DISABLE |
1073                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1074                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1075                 .param.ctrl_lli_chained = 0 |
1076                                 COH901318_CX_CTRL_TC_ENABLE |
1077                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1078                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1079                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1080                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1081                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1082                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1083                                 COH901318_CX_CTRL_TCP_DISABLE |
1084                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1085                                 COH901318_CX_CTRL_HSP_ENABLE |
1086                                 COH901318_CX_CTRL_HSS_DISABLE |
1087                                 COH901318_CX_CTRL_DDMA_LEGACY |
1088                                 COH901318_CX_CTRL_PRDD_DEST,
1089                 .param.ctrl_lli = 0 |
1090                                 COH901318_CX_CTRL_TC_ENABLE |
1091                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1092                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1093                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1094                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1095                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1096                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1097                                 COH901318_CX_CTRL_TCP_ENABLE |
1098                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1099                                 COH901318_CX_CTRL_HSP_ENABLE |
1100                                 COH901318_CX_CTRL_HSS_DISABLE |
1101                                 COH901318_CX_CTRL_DDMA_LEGACY |
1102                                 COH901318_CX_CTRL_PRDD_DEST,
1103                 .param.ctrl_lli_last = 0 |
1104                                 COH901318_CX_CTRL_TC_ENABLE |
1105                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1106                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1107                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1108                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1109                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1110                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1111                                 COH901318_CX_CTRL_TCP_ENABLE |
1112                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1113                                 COH901318_CX_CTRL_HSP_ENABLE |
1114                                 COH901318_CX_CTRL_HSS_DISABLE |
1115                                 COH901318_CX_CTRL_DDMA_LEGACY |
1116                                 COH901318_CX_CTRL_PRDD_DEST,
1117         },
1118         {
1119                 .number = U300_DMA_PCM_I2S1_TX,
1120                 .name = "PCM I2S1 TX",
1121                 .priority_high = 1,
1122                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1123                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1124                                 COH901318_CX_CFG_LCR_DISABLE |
1125                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1126                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1127                 .param.ctrl_lli_chained = 0 |
1128                                 COH901318_CX_CTRL_TC_ENABLE |
1129                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1130                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1131                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1132                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1133                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1134                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1135                                 COH901318_CX_CTRL_TCP_DISABLE |
1136                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1137                                 COH901318_CX_CTRL_HSP_ENABLE |
1138                                 COH901318_CX_CTRL_HSS_DISABLE |
1139                                 COH901318_CX_CTRL_DDMA_LEGACY |
1140                                 COH901318_CX_CTRL_PRDD_SOURCE,
1141                 .param.ctrl_lli = 0 |
1142                                 COH901318_CX_CTRL_TC_ENABLE |
1143                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1144                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1145                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1146                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1147                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1148                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1149                                 COH901318_CX_CTRL_TCP_ENABLE |
1150                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1151                                 COH901318_CX_CTRL_HSP_ENABLE |
1152                                 COH901318_CX_CTRL_HSS_DISABLE |
1153                                 COH901318_CX_CTRL_DDMA_LEGACY |
1154                                 COH901318_CX_CTRL_PRDD_SOURCE,
1155                 .param.ctrl_lli_last = 0 |
1156                                 COH901318_CX_CTRL_TC_ENABLE |
1157                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1158                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1159                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1160                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1161                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1162                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1163                                 COH901318_CX_CTRL_TCP_ENABLE |
1164                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1165                                 COH901318_CX_CTRL_HSP_ENABLE |
1166                                 COH901318_CX_CTRL_HSS_DISABLE |
1167                                 COH901318_CX_CTRL_DDMA_LEGACY |
1168                                 COH901318_CX_CTRL_PRDD_SOURCE,
1169         },
1170         {
1171                 .number = U300_DMA_PCM_I2S1_RX,
1172                 .name = "PCM I2S1 RX",
1173                 .priority_high = 1,
1174                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1175                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1176                                 COH901318_CX_CFG_LCR_DISABLE |
1177                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1178                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1179                 .param.ctrl_lli_chained = 0 |
1180                                 COH901318_CX_CTRL_TC_ENABLE |
1181                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1182                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1183                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1184                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1185                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1186                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1187                                 COH901318_CX_CTRL_TCP_DISABLE |
1188                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1189                                 COH901318_CX_CTRL_HSP_ENABLE |
1190                                 COH901318_CX_CTRL_HSS_DISABLE |
1191                                 COH901318_CX_CTRL_DDMA_LEGACY |
1192                                 COH901318_CX_CTRL_PRDD_DEST,
1193                 .param.ctrl_lli = 0 |
1194                                 COH901318_CX_CTRL_TC_ENABLE |
1195                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1196                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1197                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1198                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1199                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1200                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1201                                 COH901318_CX_CTRL_TCP_ENABLE |
1202                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1203                                 COH901318_CX_CTRL_HSP_ENABLE |
1204                                 COH901318_CX_CTRL_HSS_DISABLE |
1205                                 COH901318_CX_CTRL_DDMA_LEGACY |
1206                                 COH901318_CX_CTRL_PRDD_DEST,
1207                 .param.ctrl_lli_last = 0 |
1208                                 COH901318_CX_CTRL_TC_ENABLE |
1209                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1210                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1211                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1212                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1213                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1214                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1215                                 COH901318_CX_CTRL_TCP_ENABLE |
1216                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1217                                 COH901318_CX_CTRL_HSP_ENABLE |
1218                                 COH901318_CX_CTRL_HSS_DISABLE |
1219                                 COH901318_CX_CTRL_DDMA_LEGACY |
1220                                 COH901318_CX_CTRL_PRDD_DEST,
1221         },
1222         {
1223                 .number = U300_DMA_XGAM_CDI,
1224                 .name = "XGAM CDI",
1225                 .priority_high = 0,
1226         },
1227         {
1228                 .number = U300_DMA_XGAM_PDI,
1229                 .name = "XGAM PDI",
1230                 .priority_high = 0,
1231         },
1232         /*
1233          * Don't set up device address, burst count or size of src
1234          * or dst bus for this peripheral - handled by PrimeCell
1235          * DMA extension.
1236          */
1237         {
1238                 .number = U300_DMA_SPI_TX,
1239                 .name = "SPI TX",
1240                 .priority_high = 0,
1241                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1242                                 COH901318_CX_CFG_LCR_DISABLE |
1243                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1244                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1245                 .param.ctrl_lli_chained = 0 |
1246                                 COH901318_CX_CTRL_TC_ENABLE |
1247                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1248                                 COH901318_CX_CTRL_TCP_DISABLE |
1249                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1250                                 COH901318_CX_CTRL_HSP_ENABLE |
1251                                 COH901318_CX_CTRL_HSS_DISABLE |
1252                                 COH901318_CX_CTRL_DDMA_LEGACY,
1253                 .param.ctrl_lli = 0 |
1254                                 COH901318_CX_CTRL_TC_ENABLE |
1255                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1256                                 COH901318_CX_CTRL_TCP_DISABLE |
1257                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1258                                 COH901318_CX_CTRL_HSP_ENABLE |
1259                                 COH901318_CX_CTRL_HSS_DISABLE |
1260                                 COH901318_CX_CTRL_DDMA_LEGACY,
1261                 .param.ctrl_lli_last = 0 |
1262                                 COH901318_CX_CTRL_TC_ENABLE |
1263                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1264                                 COH901318_CX_CTRL_TCP_DISABLE |
1265                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1266                                 COH901318_CX_CTRL_HSP_ENABLE |
1267                                 COH901318_CX_CTRL_HSS_DISABLE |
1268                                 COH901318_CX_CTRL_DDMA_LEGACY,
1269         },
1270         {
1271                 .number = U300_DMA_SPI_RX,
1272                 .name = "SPI RX",
1273                 .priority_high = 0,
1274                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1275                                 COH901318_CX_CFG_LCR_DISABLE |
1276                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1277                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1278                 .param.ctrl_lli_chained = 0 |
1279                                 COH901318_CX_CTRL_TC_ENABLE |
1280                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1281                                 COH901318_CX_CTRL_TCP_DISABLE |
1282                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1283                                 COH901318_CX_CTRL_HSP_ENABLE |
1284                                 COH901318_CX_CTRL_HSS_DISABLE |
1285                                 COH901318_CX_CTRL_DDMA_LEGACY,
1286                 .param.ctrl_lli = 0 |
1287                                 COH901318_CX_CTRL_TC_ENABLE |
1288                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1289                                 COH901318_CX_CTRL_TCP_DISABLE |
1290                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1291                                 COH901318_CX_CTRL_HSP_ENABLE |
1292                                 COH901318_CX_CTRL_HSS_DISABLE |
1293                                 COH901318_CX_CTRL_DDMA_LEGACY,
1294                 .param.ctrl_lli_last = 0 |
1295                                 COH901318_CX_CTRL_TC_ENABLE |
1296                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1297                                 COH901318_CX_CTRL_TCP_DISABLE |
1298                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1299                                 COH901318_CX_CTRL_HSP_ENABLE |
1300                                 COH901318_CX_CTRL_HSS_DISABLE |
1301                                 COH901318_CX_CTRL_DDMA_LEGACY,
1302
1303         },
1304         {
1305                 .number = U300_DMA_GENERAL_PURPOSE_0,
1306                 .name = "GENERAL 00",
1307                 .priority_high = 0,
1308
1309                 .param.config = flags_memcpy_config,
1310                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1311                 .param.ctrl_lli = flags_memcpy_lli,
1312                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1313         },
1314         {
1315                 .number = U300_DMA_GENERAL_PURPOSE_1,
1316                 .name = "GENERAL 01",
1317                 .priority_high = 0,
1318
1319                 .param.config = flags_memcpy_config,
1320                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1321                 .param.ctrl_lli = flags_memcpy_lli,
1322                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1323         },
1324         {
1325                 .number = U300_DMA_GENERAL_PURPOSE_2,
1326                 .name = "GENERAL 02",
1327                 .priority_high = 0,
1328
1329                 .param.config = flags_memcpy_config,
1330                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1331                 .param.ctrl_lli = flags_memcpy_lli,
1332                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1333         },
1334         {
1335                 .number = U300_DMA_GENERAL_PURPOSE_3,
1336                 .name = "GENERAL 03",
1337                 .priority_high = 0,
1338
1339                 .param.config = flags_memcpy_config,
1340                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1341                 .param.ctrl_lli = flags_memcpy_lli,
1342                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1343         },
1344         {
1345                 .number = U300_DMA_GENERAL_PURPOSE_4,
1346                 .name = "GENERAL 04",
1347                 .priority_high = 0,
1348
1349                 .param.config = flags_memcpy_config,
1350                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1351                 .param.ctrl_lli = flags_memcpy_lli,
1352                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1353         },
1354         {
1355                 .number = U300_DMA_GENERAL_PURPOSE_5,
1356                 .name = "GENERAL 05",
1357                 .priority_high = 0,
1358
1359                 .param.config = flags_memcpy_config,
1360                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1361                 .param.ctrl_lli = flags_memcpy_lli,
1362                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1363         },
1364         {
1365                 .number = U300_DMA_GENERAL_PURPOSE_6,
1366                 .name = "GENERAL 06",
1367                 .priority_high = 0,
1368
1369                 .param.config = flags_memcpy_config,
1370                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1371                 .param.ctrl_lli = flags_memcpy_lli,
1372                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1373         },
1374         {
1375                 .number = U300_DMA_GENERAL_PURPOSE_7,
1376                 .name = "GENERAL 07",
1377                 .priority_high = 0,
1378
1379                 .param.config = flags_memcpy_config,
1380                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1381                 .param.ctrl_lli = flags_memcpy_lli,
1382                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1383         },
1384         {
1385                 .number = U300_DMA_GENERAL_PURPOSE_8,
1386                 .name = "GENERAL 08",
1387                 .priority_high = 0,
1388
1389                 .param.config = flags_memcpy_config,
1390                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1391                 .param.ctrl_lli = flags_memcpy_lli,
1392                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1393         },
1394         {
1395                 .number = U300_DMA_UART1_TX,
1396                 .name = "UART1 TX",
1397                 .priority_high = 0,
1398         },
1399         {
1400                 .number = U300_DMA_UART1_RX,
1401                 .name = "UART1 RX",
1402                 .priority_high = 0,
1403         }
1404 };
1405
1406
1407 static struct coh901318_platform coh901318_platform = {
1408         .chans_slave = dma_slave_channels,
1409         .chans_memcpy = dma_memcpy_channels,
1410         .access_memory_state = coh901318_access_memory_state,
1411         .chan_conf = chan_config,
1412         .max_channels = U300_DMA_CHANNELS,
1413 };
1414
1415 static struct resource pinctrl_resources[] = {
1416         {
1417                 .start = U300_SYSCON_BASE,
1418                 .end   = U300_SYSCON_BASE + SZ_4K - 1,
1419                 .flags = IORESOURCE_MEM,
1420         },
1421 };
1422
1423 static struct platform_device wdog_device = {
1424         .name = "coh901327_wdog",
1425         .id = -1,
1426         .num_resources = ARRAY_SIZE(wdog_resources),
1427         .resource = wdog_resources,
1428 };
1429
1430 static struct platform_device i2c0_device = {
1431         .name = "stu300",
1432         .id = 0,
1433         .num_resources = ARRAY_SIZE(i2c0_resources),
1434         .resource = i2c0_resources,
1435 };
1436
1437 static struct platform_device i2c1_device = {
1438         .name = "stu300",
1439         .id = 1,
1440         .num_resources = ARRAY_SIZE(i2c1_resources),
1441         .resource = i2c1_resources,
1442 };
1443
1444 static struct platform_device pinctrl_device = {
1445         .name = "pinctrl-u300",
1446         .id = -1,
1447         .num_resources = ARRAY_SIZE(pinctrl_resources),
1448         .resource = pinctrl_resources,
1449 };
1450
1451 /*
1452  * The different variants have a few different versions of the
1453  * GPIO block, with different number of ports.
1454  */
1455 static struct u300_gpio_platform u300_gpio_plat = {
1456         .ports = 7,
1457         .gpio_base = 0,
1458 };
1459
1460 static struct platform_device gpio_device = {
1461         .name = "u300-gpio",
1462         .id = -1,
1463         .num_resources = ARRAY_SIZE(gpio_resources),
1464         .resource = gpio_resources,
1465         .dev = {
1466                 .platform_data = &u300_gpio_plat,
1467         },
1468 };
1469
1470 static struct platform_device keypad_device = {
1471         .name = "keypad",
1472         .id = -1,
1473         .num_resources = ARRAY_SIZE(keypad_resources),
1474         .resource = keypad_resources,
1475 };
1476
1477 static struct platform_device rtc_device = {
1478         .name = "rtc-coh901331",
1479         .id = -1,
1480         .num_resources = ARRAY_SIZE(rtc_resources),
1481         .resource = rtc_resources,
1482 };
1483
1484 static struct mtd_partition u300_partitions[] = {
1485         {
1486                 .name = "bootrecords",
1487                 .offset = 0,
1488                 .size = SZ_128K,
1489         },
1490         {
1491                 .name = "free",
1492                 .offset = SZ_128K,
1493                 .size = 8064 * SZ_1K,
1494         },
1495         {
1496                 .name = "platform",
1497                 .offset = 8192 * SZ_1K,
1498                 .size = 253952 * SZ_1K,
1499         },
1500 };
1501
1502 static struct fsmc_nand_platform_data nand_platform_data = {
1503         .partitions = u300_partitions,
1504         .nr_partitions = ARRAY_SIZE(u300_partitions),
1505         .options = NAND_SKIP_BBTSCAN,
1506         .width = FSMC_NAND_BW8,
1507 };
1508
1509 static struct platform_device nand_device = {
1510         .name = "fsmc-nand",
1511         .id = -1,
1512         .resource = fsmc_resources,
1513         .num_resources = ARRAY_SIZE(fsmc_resources),
1514         .dev = {
1515                 .platform_data = &nand_platform_data,
1516         },
1517 };
1518
1519 static struct platform_device dma_device = {
1520         .name           = "coh901318",
1521         .id             = -1,
1522         .resource       = dma_resource,
1523         .num_resources  = ARRAY_SIZE(dma_resource),
1524         .dev = {
1525                 .platform_data = &coh901318_platform,
1526                 .coherent_dma_mask = ~0,
1527         },
1528 };
1529
1530 static unsigned long pin_pullup_conf[] = {
1531         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
1532 };
1533
1534 static unsigned long pin_highz_conf[] = {
1535         PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
1536 };
1537
1538 /* Pin control settings */
1539 static struct pinctrl_map __initdata u300_pinmux_map[] = {
1540         /* anonymous maps for chip power and EMIFs */
1541         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
1542         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
1543         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
1544         /* per-device maps for MMC/SD, SPI and UART */
1545         PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
1546         PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
1547         PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
1548         /* This pin is used for clock return rather than GPIO */
1549         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
1550                                     pin_pullup_conf),
1551         /* This pin is used for card detect */
1552         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
1553                                     pin_highz_conf),
1554 };
1555
1556 struct u300_mux_hog {
1557         struct device *dev;
1558         struct pinctrl *p;
1559 };
1560
1561 static struct u300_mux_hog u300_mux_hogs[] = {
1562         {
1563                 .dev = &uart0_device.dev,
1564         },
1565         {
1566                 .dev = &mmcsd_device.dev,
1567         },
1568 };
1569
1570 static int __init u300_pinctrl_fetch(void)
1571 {
1572         int i;
1573
1574         for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
1575                 struct pinctrl *p;
1576
1577                 p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
1578                 if (IS_ERR(p)) {
1579                         pr_err("u300: could not get pinmux hog for dev %s\n",
1580                                dev_name(u300_mux_hogs[i].dev));
1581                         continue;
1582                 }
1583                 u300_mux_hogs[i].p = p;
1584         }
1585         return 0;
1586 }
1587 subsys_initcall(u300_pinctrl_fetch);
1588
1589 /*
1590  * Notice that AMBA devices are initialized before platform devices.
1591  *
1592  */
1593 static struct platform_device *platform_devs[] __initdata = {
1594         &dma_device,
1595         &i2c0_device,
1596         &i2c1_device,
1597         &keypad_device,
1598         &rtc_device,
1599         &pinctrl_device,
1600         &gpio_device,
1601         &nand_device,
1602         &wdog_device,
1603 };
1604
1605 /*
1606  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1607  * together so some interrupts are connected to the first one and some
1608  * to the second one.
1609  */
1610 static void __init u300_init_irq(void)
1611 {
1612         u32 mask[2] = {0, 0};
1613         struct clk *clk;
1614         int i;
1615
1616         /* initialize clocking early, we want to clock the INTCON */
1617         u300_clk_init(U300_SYSCON_VBASE);
1618
1619         /* Bootstrap EMIF and SEMI clocks */
1620         clk = clk_get_sys("pl172", NULL);
1621         BUG_ON(IS_ERR(clk));
1622         clk_prepare_enable(clk);
1623         clk = clk_get_sys("semi", NULL);
1624         BUG_ON(IS_ERR(clk));
1625         clk_prepare_enable(clk);
1626
1627         /* Clock the interrupt controller */
1628         clk = clk_get_sys("intcon", NULL);
1629         BUG_ON(IS_ERR(clk));
1630         clk_prepare_enable(clk);
1631
1632         for (i = 0; i < U300_VIC_IRQS_END; i++)
1633                 set_bit(i, (unsigned long *) &mask[0]);
1634         vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
1635                  mask[0], mask[0]);
1636         vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
1637                  mask[1], mask[1]);
1638 }
1639
1640
1641 /*
1642  * U300 platforms peripheral handling
1643  */
1644 struct db_chip {
1645         u16 chipid;
1646         const char *name;
1647 };
1648
1649 /*
1650  * This is a list of the Digital Baseband chips used in the U300 platform.
1651  */
1652 static struct db_chip db_chips[] __initdata = {
1653         {
1654                 .chipid = 0xb800,
1655                 .name = "DB3000",
1656         },
1657         {
1658                 .chipid = 0xc000,
1659                 .name = "DB3100",
1660         },
1661         {
1662                 .chipid = 0xc800,
1663                 .name = "DB3150",
1664         },
1665         {
1666                 .chipid = 0xd800,
1667                 .name = "DB3200",
1668         },
1669         {
1670                 .chipid = 0xe000,
1671                 .name = "DB3250",
1672         },
1673         {
1674                 .chipid = 0xe800,
1675                 .name = "DB3210",
1676         },
1677         {
1678                 .chipid = 0xf000,
1679                 .name = "DB3350 P1x",
1680         },
1681         {
1682                 .chipid = 0xf100,
1683                 .name = "DB3350 P2x",
1684         },
1685         {
1686                 .chipid = 0x0000, /* List terminator */
1687                 .name = NULL,
1688         }
1689 };
1690
1691 static void __init u300_init_check_chip(void)
1692 {
1693
1694         u16 val;
1695         struct db_chip *chip;
1696         const char *chipname;
1697         const char unknown[] = "UNKNOWN";
1698
1699         /* Read out and print chip ID */
1700         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1701         /* This is in funky bigendian order... */
1702         val = (val & 0xFFU) << 8 | (val >> 8);
1703         chip = db_chips;
1704         chipname = unknown;
1705
1706         for ( ; chip->chipid; chip++) {
1707                 if (chip->chipid == (val & 0xFF00U)) {
1708                         chipname = chip->name;
1709                         break;
1710                 }
1711         }
1712         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1713                "(chip ID 0x%04x)\n", chipname, val);
1714
1715         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1716                 printk(KERN_ERR "Platform configured for BS335 " \
1717                        " with DB3350 but %s detected, expect problems!",
1718                        chipname);
1719         }
1720 }
1721
1722 /*
1723  * Some devices and their resources require reserved physical memory from
1724  * the end of the available RAM. This function traverses the list of devices
1725  * and assigns actual addresses to these.
1726  */
1727 static void __init u300_assign_physmem(void)
1728 {
1729         unsigned long curr_start = __pa(high_memory);
1730         int i, j;
1731
1732         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1733                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1734                         struct resource *const res =
1735                           &platform_devs[i]->resource[j];
1736
1737                         if (IORESOURCE_MEM == res->flags &&
1738                                      0 == res->start) {
1739                                 res->start  = curr_start;
1740                                 res->end   += curr_start;
1741                                 curr_start += resource_size(res);
1742
1743                                 printk(KERN_INFO "core.c: Mapping RAM " \
1744                                        "%#x-%#x to device %s:%s\n",
1745                                         res->start, res->end,
1746                                        platform_devs[i]->name, res->name);
1747                         }
1748                 }
1749         }
1750 }
1751
1752 static void __init u300_init_machine(void)
1753 {
1754         int i;
1755         u16 val;
1756
1757         /* Check what platform we run and print some status information */
1758         u300_init_check_chip();
1759
1760         /* Initialize SPI device with some board specifics */
1761         u300_spi_init(&pl022_device);
1762
1763         /* Register the AMBA devices in the AMBA bus abstraction layer */
1764         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1765                 struct amba_device *d = amba_devs[i];
1766                 amba_device_register(d, &iomem_resource);
1767         }
1768
1769         u300_assign_physmem();
1770
1771         /* Initialize pinmuxing */
1772         pinctrl_register_mappings(u300_pinmux_map,
1773                                   ARRAY_SIZE(u300_pinmux_map));
1774
1775         /* Register subdevices on the I2C buses */
1776         u300_i2c_register_board_devices();
1777
1778         /* Register the platform devices */
1779         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1780
1781         /* Register subdevices on the SPI bus */
1782         u300_spi_register_board_devices();
1783
1784         /* Enable SEMI self refresh */
1785         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1786                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1787         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1788 }
1789
1790 /* Forward declare this function from the watchdog */
1791 void coh901327_watchdog_reset(void);
1792
1793 static void u300_restart(char mode, const char *cmd)
1794 {
1795         switch (mode) {
1796         case 's':
1797         case 'h':
1798 #ifdef CONFIG_COH901327_WATCHDOG
1799                 coh901327_watchdog_reset();
1800 #endif
1801                 break;
1802         default:
1803                 /* Do nothing */
1804                 break;
1805         }
1806         /* Wait for system do die/reset. */
1807         while (1);
1808 }
1809
1810 MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
1811         /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
1812         .atag_offset    = 0x100,
1813         .map_io         = u300_map_io,
1814         .nr_irqs        = 0,
1815         .init_irq       = u300_init_irq,
1816         .handle_irq     = vic_handle_irq,
1817         .timer          = &u300_timer,
1818         .init_machine   = u300_init_machine,
1819         .restart        = u300_restart,
1820 MACHINE_END