2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/linkage.h>
19 #include <soc/tegra/flowctrl.h>
20 #include <soc/tegra/fuse.h>
22 #include <asm/asm-offsets.h>
23 #include <asm/assembler.h>
24 #include <asm/cache.h>
30 #define EMC_ADR_CFG 0x10
31 #define EMC_TIMING_CONTROL 0x28
33 #define EMC_SELF_REF 0xe0
35 #define EMC_FBIO_CFG5 0x104
36 #define EMC_AUTO_CAL_CONFIG 0x2a4
37 #define EMC_AUTO_CAL_INTERVAL 0x2a8
38 #define EMC_AUTO_CAL_STATUS 0x2ac
39 #define EMC_REQ_CTRL 0x2b0
40 #define EMC_CFG_DIG_DLL 0x2bc
41 #define EMC_EMC_STATUS 0x2b4
42 #define EMC_ZCAL_INTERVAL 0x2e0
43 #define EMC_ZQ_CAL 0x2ec
44 #define EMC_XM2VTTGENPADCTRL 0x310
45 #define EMC_XM2VTTGENPADCTRL2 0x314
47 #define MC_EMEM_ARB_CFG 0x90
50 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_IO_DPD_REQ 0x1b8
54 #define PMC_IO_DPD_STATUS 0x1bc
56 #define CLK_RESET_CCLK_BURST 0x20
57 #define CLK_RESET_CCLK_DIVIDER 0x24
58 #define CLK_RESET_SCLK_BURST 0x28
59 #define CLK_RESET_SCLK_DIVIDER 0x2c
61 #define CLK_RESET_PLLC_BASE 0x80
62 #define CLK_RESET_PLLC_MISC 0x8c
63 #define CLK_RESET_PLLM_BASE 0x90
64 #define CLK_RESET_PLLM_MISC 0x9c
65 #define CLK_RESET_PLLP_BASE 0xa0
66 #define CLK_RESET_PLLP_MISC 0xac
67 #define CLK_RESET_PLLA_BASE 0xb0
68 #define CLK_RESET_PLLA_MISC 0xbc
69 #define CLK_RESET_PLLX_BASE 0xe0
70 #define CLK_RESET_PLLX_MISC 0xe4
71 #define CLK_RESET_PLLX_MISC3 0x518
72 #define CLK_RESET_PLLX_MISC3_IDDQ 3
73 #define CLK_RESET_PLLM_MISC_IDDQ 5
74 #define CLK_RESET_PLLC_MISC_IDDQ 26
76 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
78 #define MSELECT_CLKM (0x3 << 30)
80 #define LOCK_DELAY 50 /* safety delay after lock is detected */
82 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
84 .macro emc_device_mask, rd, base
85 ldr \rd, [\base, #EMC_ADR_CFG]
87 moveq \rd, #(0x1 << 8) @ just 1 device
88 movne \rd, #(0x3 << 8) @ 2 devices
91 .macro emc_timing_update, rd, base
93 str \rd, [\base, #EMC_TIMING_CONTROL]
95 ldr \rd, [\base, #EMC_EMC_STATUS]
96 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
100 .macro pll_enable, rd, r_car_base, pll_base, pll_misc
101 ldr \rd, [\r_car_base, #\pll_base]
103 orreq \rd, \rd, #(1 << 30)
104 streq \rd, [\r_car_base, #\pll_base]
105 /* Enable lock detector */
107 ldr \rd, [\r_car_base, #\pll_misc]
108 bic \rd, \rd, #(1 << 18)
109 str \rd, [\r_car_base, #\pll_misc]
110 ldr \rd, [\r_car_base, #\pll_misc]
111 ldr \rd, [\r_car_base, #\pll_misc]
112 orr \rd, \rd, #(1 << 18)
113 str \rd, [\r_car_base, #\pll_misc]
117 .macro pll_locked, rd, r_car_base, pll_base
119 ldr \rd, [\r_car_base, #\pll_base]
124 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
125 ldr \rd, [\car, #\iddq]
126 bic \rd, \rd, #(1<<\iddq_bit)
127 str \rd, [\car, #\iddq]
130 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
131 ldr \rd, [\car, #\iddq]
132 orr \rd, \rd, #(1<<\iddq_bit)
133 str \rd, [\car, #\iddq]
136 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
138 * tegra30_hotplug_shutdown(void)
140 * Powergates the current CPU.
141 * Should never return.
143 ENTRY(tegra30_hotplug_shutdown)
144 /* Powergate this CPU */
145 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
146 bl tegra30_cpu_shutdown
147 ret lr @ should never get here
148 ENDPROC(tegra30_hotplug_shutdown)
151 * tegra30_cpu_shutdown(unsigned long flags)
153 * Puts the current CPU in wait-for-event mode on the flow controller
154 * and powergates it -- flags (in R0) indicate the request type.
157 * corrupts r0-r4, r10-r12
159 ENTRY(tegra30_cpu_shutdown)
161 tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
163 bne _no_cpu0_chk @ It's not Tegra30
166 reteq lr @ Must never be called for CPU 0
169 ldr r12, =TEGRA_FLOW_CTRL_VIRT
170 cpu_to_csr_reg r1, r3
171 add r1, r1, r12 @ virtual CSR address for this CPU
172 cpu_to_halt_reg r2, r3
173 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
176 * Clear this CPU's "event" and "interrupt" flags and power gate
177 * it when halting but not before it is in the "WFE" state.
180 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
183 moveq r4, #(1 << 4) @ wfe bitmap
184 movne r4, #(1 << 8) @ wfi bitmap
185 ARM( orr r12, r12, r4, lsl r3 )
186 THUMB( lsl r4, r4, r3 )
187 THUMB( orr r12, r12, r4 )
193 subs r3, r3, #1 @ delay as a part of wfe war.
195 cpsid a @ disable imprecise aborts.
196 ldr r3, [r1] @ read CSR
197 str r3, [r1] @ clear CSR
199 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
200 beq flow_ctrl_setting_for_lp2
202 /* flow controller set up for hotplug */
203 mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
205 flow_ctrl_setting_for_lp2:
206 /* flow controller set up for LP2 */
208 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
209 movne r3, #FLOW_CTRL_WAITEVENT
210 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
211 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
221 wfeeq @ CPU should be power gated here
227 * 38 nop's, which fills rest of wfe cache line and
228 * 4 more cachelines with nop
233 b . @ should never get here
235 ENDPROC(tegra30_cpu_shutdown)
238 #ifdef CONFIG_PM_SLEEP
240 * tegra30_sleep_core_finish(unsigned long v2p)
242 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
243 * tegra30_tear_down_core in IRAM
245 ENTRY(tegra30_sleep_core_finish)
247 /* Flush, disable the L1 data cache and exit SMP */
248 mov r0, #TEGRA_FLUSH_CACHE_ALL
249 bl tegra_disable_clean_inv_dcache
253 * Preload all the address literals that are needed for the
254 * CPU power-gating process, to avoid loading from SDRAM which
255 * are not supported once SDRAM is put into self-refresh.
256 * LP0 / LP1 use physical address, since the MMU needs to be
257 * disabled before putting SDRAM into self-refresh to avoid
258 * memory access due to page table walks.
260 mov32 r4, TEGRA_PMC_BASE
261 mov32 r5, TEGRA_CLK_RESET_BASE
262 mov32 r6, TEGRA_FLOW_CTRL_BASE
263 mov32 r7, TEGRA_TMRUS_BASE
265 mov32 r3, tegra_shut_off_mmu
268 mov32 r0, tegra30_tear_down_core
269 mov32 r1, tegra30_iram_start
271 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
275 ENDPROC(tegra30_sleep_core_finish)
278 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
280 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
282 ENTRY(tegra30_sleep_cpu_secondary_finish)
285 /* Flush and disable the L1 data cache */
286 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
287 bl tegra_disable_clean_inv_dcache
289 /* Powergate this CPU. */
290 mov r0, #0 @ power mode flags (!hotplug)
291 bl tegra30_cpu_shutdown
292 mov r0, #1 @ never return here
294 ENDPROC(tegra30_sleep_cpu_secondary_finish)
297 * tegra30_tear_down_cpu
299 * Switches the CPU to enter sleep.
301 ENTRY(tegra30_tear_down_cpu)
302 mov32 r6, TEGRA_FLOW_CTRL_BASE
304 b tegra30_enter_sleep
305 ENDPROC(tegra30_tear_down_cpu)
307 /* START OF ROUTINES COPIED TO IRAM */
308 .align L1_CACHE_SHIFT
309 .globl tegra30_iram_start
315 * reset vector for LP1 restore; copied into IRAM during suspend.
316 * Brings the system back up to a safe staring point (SDRAM out of
317 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
318 * system clock running on the same PLL that it suspended at), and
319 * jumps to tegra_resume to restore virtual addressing.
320 * The physical address of tegra_resume expected to be stored in
323 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
325 ENTRY(tegra30_lp1_reset)
327 * The CPU and system bus are running at 32KHz and executing from
328 * IRAM when this code is executed; immediately switch to CLKM and
329 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
331 mov32 r0, TEGRA_CLK_RESET_BASE
334 str r1, [r0, #CLK_RESET_SCLK_BURST]
335 str r1, [r0, #CLK_RESET_CCLK_BURST]
337 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
338 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
340 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
342 beq _no_pll_iddq_exit
344 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
345 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
346 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
348 mov32 r7, TEGRA_TMRUS_BASE
351 wait_until r1, r7, r3
353 /* enable PLLM via PMC */
354 mov32 r2, TEGRA_PMC_BASE
355 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
356 orr r1, r1, #(1 << 12)
357 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
359 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
360 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
361 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
366 /* enable PLLM via PMC */
367 mov32 r2, TEGRA_PMC_BASE
368 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
369 orr r1, r1, #(1 << 12)
370 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
372 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
373 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
374 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
377 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
378 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
380 pll_locked r1, r0, CLK_RESET_PLLM_BASE
381 pll_locked r1, r0, CLK_RESET_PLLP_BASE
382 pll_locked r1, r0, CLK_RESET_PLLA_BASE
383 pll_locked r1, r0, CLK_RESET_PLLC_BASE
384 pll_locked r1, r0, CLK_RESET_PLLX_BASE
386 mov32 r7, TEGRA_TMRUS_BASE
388 add r1, r1, #LOCK_DELAY
389 wait_until r1, r7, r3
391 adr r5, tegra_sdram_pad_save
393 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
394 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
396 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
397 str r4, [r0, #CLK_RESET_SCLK_BURST]
400 movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
401 movteq r4, #:upper16:((1 << 28) | (0x8))
402 movwne r4, #:lower16:((1 << 28) | (0xe))
403 movtne r4, #:upper16:((1 << 28) | (0xe))
404 str r4, [r0, #CLK_RESET_CCLK_BURST]
406 /* Restore pad power state to normal */
407 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
409 bic r1, r1, #(1 << 31)
410 orr r1, r1, #(1 << 30)
411 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
414 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
415 movteq r0, #:upper16:TEGRA_EMC_BASE
417 movweq r0, #:lower16:TEGRA_EMC0_BASE
418 movteq r0, #:upper16:TEGRA_EMC0_BASE
420 movweq r0, #:lower16:TEGRA124_EMC_BASE
421 movteq r0, #:upper16:TEGRA124_EMC_BASE
425 movweq r4, #:lower16:TEGRA_MC_BASE
426 movteq r4, #:upper16:TEGRA_MC_BASE
429 movweq r4, #:lower16:TEGRA114_MC_BASE
430 movteq r4, #:upper16:TEGRA114_MC_BASE
433 movweq r4, #:lower16:TEGRA124_MC_BASE
434 movteq r4, #:upper16:TEGRA124_MC_BASE
436 ldr r1, [r5, r2] @ restore MC_EMEM_ARB_CFG
437 str r1, [r4, #MC_EMEM_ARB_CFG]
440 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
441 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
442 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
443 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
444 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
445 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
448 ldr r1, [r0, #EMC_CFG_DIG_DLL]
449 orr r1, r1, #(1 << 30) @ set DLL_RESET
450 str r1, [r0, #EMC_CFG_DIG_DLL]
452 emc_timing_update r1, r0
455 movweq r1, #:lower16:TEGRA_EMC1_BASE
456 movteq r1, #:upper16:TEGRA_EMC1_BASE
459 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
460 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
461 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
462 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
464 emc_wait_auto_cal_onetime:
465 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
466 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
467 bne emc_wait_auto_cal_onetime
469 ldr r1, [r0, #EMC_CFG]
470 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
471 str r1, [r0, #EMC_CFG]
474 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
477 streq r1, [r0, #EMC_NOP]
478 streq r1, [r0, #EMC_NOP]
480 emc_device_mask r1, r0
482 exit_selfrefresh_loop:
483 ldr r2, [r0, #EMC_EMC_STATUS]
485 bne exit_selfrefresh_loop
487 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
489 mov32 r7, TEGRA_TMRUS_BASE
490 ldr r2, [r0, #EMC_FBIO_CFG5]
492 and r2, r2, #3 @ check DRAM_TYPE
496 /* Issue a ZQ_CAL for dev0 - DDR3 */
497 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
498 str r2, [r0, #EMC_ZQ_CAL]
501 wait_until r2, r7, r3
506 /* Issue a ZQ_CAL for dev1 - DDR3 */
507 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
508 str r2, [r0, #EMC_ZQ_CAL]
511 wait_until r2, r7, r3
515 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
516 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
517 str r2, [r0, #EMC_MRW]
520 wait_until r2, r7, r3
525 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
526 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
527 str r2, [r0, #EMC_MRW]
530 wait_until r2, r7, r3
533 mov r1, #0 @ unstall all transactions
534 str r1, [r0, #EMC_REQ_CTRL]
535 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
536 str r1, [r0, #EMC_ZCAL_INTERVAL]
537 ldr r1, [r5, #0x0] @ restore EMC_CFG
538 str r1, [r0, #EMC_CFG]
540 emc_timing_update r1, r0
542 /* Tegra114 had dual EMC channel, now config the other one */
544 bne __no_dual_emc_chanl
545 mov32 r1, TEGRA_EMC1_BASE
549 bne exit_self_refresh
552 mov32 r0, TEGRA_PMC_BASE
553 ldr r0, [r0, #PMC_SCRATCH41]
554 ret r0 @ jump to tegra_resume
555 ENDPROC(tegra30_lp1_reset)
557 .align L1_CACHE_SHIFT
558 tegra30_sdram_pad_address:
559 .word TEGRA_EMC_BASE + EMC_CFG @0x0
560 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
561 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
562 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
563 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
564 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
565 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
566 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
567 .word TEGRA_MC_BASE + MC_EMEM_ARB_CFG @0x20
568 tegra30_sdram_pad_address_end:
570 tegra114_sdram_pad_address:
571 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
572 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
573 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
574 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
575 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
576 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
577 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
578 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
579 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
580 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
581 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
582 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
583 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
584 .word TEGRA114_MC_BASE + MC_EMEM_ARB_CFG @0x34
585 tegra114_sdram_pad_adress_end:
587 tegra124_sdram_pad_address:
588 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
589 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
590 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
591 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
592 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
593 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
594 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
595 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
596 .word TEGRA124_MC_BASE + MC_EMEM_ARB_CFG @0x20
597 tegra124_sdram_pad_address_end:
599 tegra30_sdram_pad_size:
600 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
602 tegra114_sdram_pad_size:
603 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
605 .type tegra_sdram_pad_save, %object
606 tegra_sdram_pad_save:
607 .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
612 * tegra30_tear_down_core
614 * copied into and executed from IRAM
615 * puts memory in self-refresh for LP0 and LP1
617 tegra30_tear_down_core:
618 bl tegra30_sdram_self_refresh
619 bl tegra30_switch_cpu_to_clk32k
620 b tegra30_enter_sleep
623 * tegra30_switch_cpu_to_clk32k
625 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
626 * to the 32KHz clock.
627 * r4 = TEGRA_PMC_BASE
628 * r5 = TEGRA_CLK_RESET_BASE
629 * r6 = TEGRA_FLOW_CTRL_BASE
630 * r7 = TEGRA_TMRUS_BASE
633 tegra30_switch_cpu_to_clk32k:
635 * start by jumping to CLKM to safely disable PLLs, then jump to
639 str r0, [r5, #CLK_RESET_SCLK_BURST]
640 /* 2uS delay delay between changing SCLK and CCLK */
643 wait_until r1, r7, r9
644 str r0, [r5, #CLK_RESET_CCLK_BURST]
646 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
647 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
649 /* switch the clock source of mselect to be CLK_M */
650 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
651 orr r0, r0, #MSELECT_CLKM
652 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
654 /* 2uS delay delay between changing SCLK and disabling PLLs */
657 wait_until r1, r7, r9
659 /* disable PLLM via PMC in LP1 */
660 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
661 bic r0, r0, #(1 << 12)
662 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
664 /* disable PLLP, PLLA, PLLC and PLLX */
665 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
666 bic r0, r0, #(1 << 30)
667 str r0, [r5, #CLK_RESET_PLLP_BASE]
668 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
669 bic r0, r0, #(1 << 30)
670 str r0, [r5, #CLK_RESET_PLLA_BASE]
671 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
672 bic r0, r0, #(1 << 30)
673 str r0, [r5, #CLK_RESET_PLLC_BASE]
674 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
675 bic r0, r0, #(1 << 30)
676 str r0, [r5, #CLK_RESET_PLLX_BASE]
680 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
684 mov r0, #0 /* brust policy = 32KHz */
685 str r0, [r5, #CLK_RESET_SCLK_BURST]
690 * tegra30_enter_sleep
692 * uses flow controller to enter sleep state
693 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
694 * executes from SDRAM with target state is LP2
695 * r6 = TEGRA_FLOW_CTRL_BASE
700 cpu_to_csr_reg r2, r1
702 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
703 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
706 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
708 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
709 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
710 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
712 cpu_to_halt_reg r2, r1
715 ldr r0, [r6, r2] /* memory barrier */
720 wfi /* CPU should be power gated here */
722 /* !!!FIXME!!! Implement halt failure handler */
726 * tegra30_sdram_self_refresh
728 * called with MMU off and caches disabled
729 * must be executed from IRAM
730 * r4 = TEGRA_PMC_BASE
731 * r5 = TEGRA_CLK_RESET_BASE
732 * r6 = TEGRA_FLOW_CTRL_BASE
733 * r7 = TEGRA_TMRUS_BASE
736 tegra30_sdram_self_refresh:
738 adr r8, tegra_sdram_pad_save
739 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
741 adreq r2, tegra30_sdram_pad_address
742 ldreq r3, tegra30_sdram_pad_size
744 adreq r2, tegra114_sdram_pad_address
745 ldreq r3, tegra114_sdram_pad_size
747 adreq r2, tegra124_sdram_pad_address
748 ldreq r3, tegra30_sdram_pad_size
753 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
756 str r1, [r8, r9] @ save the content of the addr
766 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
768 ldreq r0, =TEGRA_EMC0_BASE
770 ldreq r0, =TEGRA124_EMC_BASE
775 str r1, [r0, #EMC_ZCAL_INTERVAL]
776 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
777 ldr r1, [r0, #EMC_CFG]
778 bic r1, r1, #(1 << 28)
779 bicne r1, r1, #(1 << 29)
780 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
782 emc_timing_update r1, r0
786 wait_until r1, r7, r2
789 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
790 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
791 bne emc_wait_auto_cal
794 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
797 ldr r1, [r0, #EMC_EMC_STATUS]
802 str r1, [r0, #EMC_SELF_REF]
804 emc_device_mask r1, r0
807 ldr r2, [r0, #EMC_EMC_STATUS]
810 bne emcself @ loop until DDR in self-refresh
812 /* Put VTTGEN in the lowest power mode */
813 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
814 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
816 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
817 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
819 orreq r1, r1, #7 @ set E_NO_VTTGEN
821 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
823 emc_timing_update r1, r0
825 /* Tegra114 had dual EMC channel, now config the other one */
827 bne no_dual_emc_chanl
828 mov32 r1, TEGRA_EMC1_BASE
831 bne enter_self_refresh
834 ldr r1, [r4, #PMC_CTRL]
835 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
838 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
839 * and COMP in the lowest power mode when LP1.
842 str r1, [r4, #PMC_IO_DPD_REQ]
850 /* dummy symbol for end of IRAM */
851 .align L1_CACHE_SHIFT
852 .global tegra30_iram_end