2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/linkage.h>
19 #include <soc/tegra/flowctrl.h>
20 #include <soc/tegra/fuse.h>
22 #include <asm/asm-offsets.h>
23 #include <asm/assembler.h>
24 #include <asm/cache.h>
30 #define EMC_ADR_CFG 0x10
31 #define EMC_TIMING_CONTROL 0x28
33 #define EMC_SELF_REF 0xe0
35 #define EMC_FBIO_CFG5 0x104
36 #define EMC_AUTO_CAL_CONFIG 0x2a4
37 #define EMC_AUTO_CAL_INTERVAL 0x2a8
38 #define EMC_AUTO_CAL_STATUS 0x2ac
39 #define EMC_REQ_CTRL 0x2b0
40 #define EMC_CFG_DIG_DLL 0x2bc
41 #define EMC_EMC_STATUS 0x2b4
42 #define EMC_ZCAL_INTERVAL 0x2e0
43 #define EMC_ZQ_CAL 0x2ec
44 #define EMC_XM2VTTGENPADCTRL 0x310
45 #define EMC_XM2VTTGENPADCTRL2 0x314
48 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
50 #define PMC_PLLP_WB0_OVERRIDE 0xf8
51 #define PMC_IO_DPD_REQ 0x1b8
52 #define PMC_IO_DPD_STATUS 0x1bc
54 #define CLK_RESET_CCLK_BURST 0x20
55 #define CLK_RESET_CCLK_DIVIDER 0x24
56 #define CLK_RESET_SCLK_BURST 0x28
57 #define CLK_RESET_SCLK_DIVIDER 0x2c
59 #define CLK_RESET_PLLC_BASE 0x80
60 #define CLK_RESET_PLLC_MISC 0x8c
61 #define CLK_RESET_PLLM_BASE 0x90
62 #define CLK_RESET_PLLM_MISC 0x9c
63 #define CLK_RESET_PLLP_BASE 0xa0
64 #define CLK_RESET_PLLP_MISC 0xac
65 #define CLK_RESET_PLLA_BASE 0xb0
66 #define CLK_RESET_PLLA_MISC 0xbc
67 #define CLK_RESET_PLLX_BASE 0xe0
68 #define CLK_RESET_PLLX_MISC 0xe4
69 #define CLK_RESET_PLLX_MISC3 0x518
70 #define CLK_RESET_PLLX_MISC3_IDDQ 3
71 #define CLK_RESET_PLLM_MISC_IDDQ 5
72 #define CLK_RESET_PLLC_MISC_IDDQ 26
74 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
76 #define MSELECT_CLKM (0x3 << 30)
78 #define LOCK_DELAY 50 /* safety delay after lock is detected */
80 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
82 .macro emc_device_mask, rd, base
83 ldr \rd, [\base, #EMC_ADR_CFG]
85 moveq \rd, #(0x1 << 8) @ just 1 device
86 movne \rd, #(0x3 << 8) @ 2 devices
89 .macro emc_timing_update, rd, base
91 str \rd, [\base, #EMC_TIMING_CONTROL]
93 ldr \rd, [\base, #EMC_EMC_STATUS]
94 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
98 .macro pll_enable, rd, r_car_base, pll_base, pll_misc
99 ldr \rd, [\r_car_base, #\pll_base]
101 orreq \rd, \rd, #(1 << 30)
102 streq \rd, [\r_car_base, #\pll_base]
103 /* Enable lock detector */
105 ldr \rd, [\r_car_base, #\pll_misc]
106 bic \rd, \rd, #(1 << 18)
107 str \rd, [\r_car_base, #\pll_misc]
108 ldr \rd, [\r_car_base, #\pll_misc]
109 ldr \rd, [\r_car_base, #\pll_misc]
110 orr \rd, \rd, #(1 << 18)
111 str \rd, [\r_car_base, #\pll_misc]
115 .macro pll_locked, rd, r_car_base, pll_base
117 ldr \rd, [\r_car_base, #\pll_base]
122 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
123 ldr \rd, [\car, #\iddq]
124 bic \rd, \rd, #(1<<\iddq_bit)
125 str \rd, [\car, #\iddq]
128 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
129 ldr \rd, [\car, #\iddq]
130 orr \rd, \rd, #(1<<\iddq_bit)
131 str \rd, [\car, #\iddq]
134 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
136 * tegra30_hotplug_shutdown(void)
138 * Powergates the current CPU.
139 * Should never return.
141 ENTRY(tegra30_hotplug_shutdown)
142 /* Powergate this CPU */
143 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
144 bl tegra30_cpu_shutdown
145 ret lr @ should never get here
146 ENDPROC(tegra30_hotplug_shutdown)
149 * tegra30_cpu_shutdown(unsigned long flags)
151 * Puts the current CPU in wait-for-event mode on the flow controller
152 * and powergates it -- flags (in R0) indicate the request type.
155 * corrupts r0-r4, r10-r12
157 ENTRY(tegra30_cpu_shutdown)
159 tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
161 bne _no_cpu0_chk @ It's not Tegra30
164 reteq lr @ Must never be called for CPU 0
167 ldr r12, =TEGRA_FLOW_CTRL_VIRT
168 cpu_to_csr_reg r1, r3
169 add r1, r1, r12 @ virtual CSR address for this CPU
170 cpu_to_halt_reg r2, r3
171 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
174 * Clear this CPU's "event" and "interrupt" flags and power gate
175 * it when halting but not before it is in the "WFE" state.
178 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
181 moveq r4, #(1 << 4) @ wfe bitmap
182 movne r4, #(1 << 8) @ wfi bitmap
183 ARM( orr r12, r12, r4, lsl r3 )
184 THUMB( lsl r4, r4, r3 )
185 THUMB( orr r12, r12, r4 )
191 subs r3, r3, #1 @ delay as a part of wfe war.
193 cpsid a @ disable imprecise aborts.
194 ldr r3, [r1] @ read CSR
195 str r3, [r1] @ clear CSR
197 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
198 beq flow_ctrl_setting_for_lp2
200 /* flow controller set up for hotplug */
201 mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
203 flow_ctrl_setting_for_lp2:
204 /* flow controller set up for LP2 */
206 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
207 movne r3, #FLOW_CTRL_WAITEVENT
208 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
209 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
219 wfeeq @ CPU should be power gated here
225 * 38 nop's, which fills rest of wfe cache line and
226 * 4 more cachelines with nop
231 b . @ should never get here
233 ENDPROC(tegra30_cpu_shutdown)
236 #ifdef CONFIG_PM_SLEEP
238 * tegra30_sleep_core_finish(unsigned long v2p)
240 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
241 * tegra30_tear_down_core in IRAM
243 ENTRY(tegra30_sleep_core_finish)
245 /* Flush, disable the L1 data cache and exit SMP */
246 mov r0, #TEGRA_FLUSH_CACHE_ALL
247 bl tegra_disable_clean_inv_dcache
251 * Preload all the address literals that are needed for the
252 * CPU power-gating process, to avoid loading from SDRAM which
253 * are not supported once SDRAM is put into self-refresh.
254 * LP0 / LP1 use physical address, since the MMU needs to be
255 * disabled before putting SDRAM into self-refresh to avoid
256 * memory access due to page table walks.
258 mov32 r4, TEGRA_PMC_BASE
259 mov32 r5, TEGRA_CLK_RESET_BASE
260 mov32 r6, TEGRA_FLOW_CTRL_BASE
261 mov32 r7, TEGRA_TMRUS_BASE
263 mov32 r3, tegra_shut_off_mmu
266 mov32 r0, tegra30_tear_down_core
267 mov32 r1, tegra30_iram_start
269 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
273 ENDPROC(tegra30_sleep_core_finish)
276 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
278 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
280 ENTRY(tegra30_sleep_cpu_secondary_finish)
283 /* Flush and disable the L1 data cache */
284 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
285 bl tegra_disable_clean_inv_dcache
287 /* Powergate this CPU. */
288 mov r0, #0 @ power mode flags (!hotplug)
289 bl tegra30_cpu_shutdown
290 mov r0, #1 @ never return here
292 ENDPROC(tegra30_sleep_cpu_secondary_finish)
295 * tegra30_tear_down_cpu
297 * Switches the CPU to enter sleep.
299 ENTRY(tegra30_tear_down_cpu)
300 mov32 r6, TEGRA_FLOW_CTRL_BASE
302 b tegra30_enter_sleep
303 ENDPROC(tegra30_tear_down_cpu)
305 /* START OF ROUTINES COPIED TO IRAM */
306 .align L1_CACHE_SHIFT
307 .globl tegra30_iram_start
313 * reset vector for LP1 restore; copied into IRAM during suspend.
314 * Brings the system back up to a safe staring point (SDRAM out of
315 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
316 * system clock running on the same PLL that it suspended at), and
317 * jumps to tegra_resume to restore virtual addressing.
318 * The physical address of tegra_resume expected to be stored in
321 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
323 ENTRY(tegra30_lp1_reset)
325 * The CPU and system bus are running at 32KHz and executing from
326 * IRAM when this code is executed; immediately switch to CLKM and
327 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
329 mov32 r0, TEGRA_CLK_RESET_BASE
332 str r1, [r0, #CLK_RESET_SCLK_BURST]
333 str r1, [r0, #CLK_RESET_CCLK_BURST]
335 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
336 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
338 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
340 beq _no_pll_iddq_exit
342 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
343 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
344 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
346 mov32 r7, TEGRA_TMRUS_BASE
349 wait_until r1, r7, r3
351 /* enable PLLM via PMC */
352 mov32 r2, TEGRA_PMC_BASE
353 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
354 orr r1, r1, #(1 << 12)
355 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
357 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
358 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
359 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
364 /* enable PLLM via PMC */
365 mov32 r2, TEGRA_PMC_BASE
366 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
367 orr r1, r1, #(1 << 12)
368 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
370 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
371 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
372 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
375 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
376 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
378 pll_locked r1, r0, CLK_RESET_PLLM_BASE
379 pll_locked r1, r0, CLK_RESET_PLLP_BASE
380 pll_locked r1, r0, CLK_RESET_PLLA_BASE
381 pll_locked r1, r0, CLK_RESET_PLLC_BASE
382 pll_locked r1, r0, CLK_RESET_PLLX_BASE
384 mov32 r7, TEGRA_TMRUS_BASE
386 add r1, r1, #LOCK_DELAY
387 wait_until r1, r7, r3
389 adr r5, tegra_sdram_pad_save
391 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
392 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
394 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
395 str r4, [r0, #CLK_RESET_SCLK_BURST]
398 movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
399 movteq r4, #:upper16:((1 << 28) | (0x8))
400 movwne r4, #:lower16:((1 << 28) | (0xe))
401 movtne r4, #:upper16:((1 << 28) | (0xe))
402 str r4, [r0, #CLK_RESET_CCLK_BURST]
404 /* Restore pad power state to normal */
405 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
407 bic r1, r1, #(1 << 31)
408 orr r1, r1, #(1 << 30)
409 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
412 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
413 movteq r0, #:upper16:TEGRA_EMC_BASE
415 movweq r0, #:lower16:TEGRA_EMC0_BASE
416 movteq r0, #:upper16:TEGRA_EMC0_BASE
418 movweq r0, #:lower16:TEGRA124_EMC_BASE
419 movteq r0, #:upper16:TEGRA124_EMC_BASE
422 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
423 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
424 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
425 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
426 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
427 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
430 ldr r1, [r0, #EMC_CFG_DIG_DLL]
431 orr r1, r1, #(1 << 30) @ set DLL_RESET
432 str r1, [r0, #EMC_CFG_DIG_DLL]
434 emc_timing_update r1, r0
437 movweq r1, #:lower16:TEGRA_EMC1_BASE
438 movteq r1, #:upper16:TEGRA_EMC1_BASE
441 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
442 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
443 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
444 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
446 emc_wait_auto_cal_onetime:
447 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
448 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
449 bne emc_wait_auto_cal_onetime
451 ldr r1, [r0, #EMC_CFG]
452 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
453 str r1, [r0, #EMC_CFG]
456 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
459 streq r1, [r0, #EMC_NOP]
460 streq r1, [r0, #EMC_NOP]
462 emc_device_mask r1, r0
464 exit_selfrefresh_loop:
465 ldr r2, [r0, #EMC_EMC_STATUS]
467 bne exit_selfrefresh_loop
469 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
471 mov32 r7, TEGRA_TMRUS_BASE
472 ldr r2, [r0, #EMC_FBIO_CFG5]
474 and r2, r2, #3 @ check DRAM_TYPE
478 /* Issue a ZQ_CAL for dev0 - DDR3 */
479 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
480 str r2, [r0, #EMC_ZQ_CAL]
483 wait_until r2, r7, r3
488 /* Issue a ZQ_CAL for dev1 - DDR3 */
489 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
490 str r2, [r0, #EMC_ZQ_CAL]
493 wait_until r2, r7, r3
497 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
498 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
499 str r2, [r0, #EMC_MRW]
502 wait_until r2, r7, r3
507 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
508 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
509 str r2, [r0, #EMC_MRW]
512 wait_until r2, r7, r3
515 mov r1, #0 @ unstall all transactions
516 str r1, [r0, #EMC_REQ_CTRL]
517 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
518 str r1, [r0, #EMC_ZCAL_INTERVAL]
519 ldr r1, [r5, #0x0] @ restore EMC_CFG
520 str r1, [r0, #EMC_CFG]
522 emc_timing_update r1, r0
524 /* Tegra114 had dual EMC channel, now config the other one */
526 bne __no_dual_emc_chanl
527 mov32 r1, TEGRA_EMC1_BASE
531 bne exit_self_refresh
534 mov32 r0, TEGRA_PMC_BASE
535 ldr r0, [r0, #PMC_SCRATCH41]
536 ret r0 @ jump to tegra_resume
537 ENDPROC(tegra30_lp1_reset)
539 .align L1_CACHE_SHIFT
540 tegra30_sdram_pad_address:
541 .word TEGRA_EMC_BASE + EMC_CFG @0x0
542 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
543 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
544 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
545 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
546 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
547 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
548 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
549 tegra30_sdram_pad_address_end:
551 tegra114_sdram_pad_address:
552 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
553 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
554 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
555 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
556 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
557 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
558 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
559 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
560 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
561 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
562 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
563 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
564 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
565 tegra114_sdram_pad_adress_end:
567 tegra124_sdram_pad_address:
568 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
569 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
570 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
571 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
572 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
573 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
574 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
575 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
576 tegra124_sdram_pad_address_end:
578 tegra30_sdram_pad_size:
579 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
581 tegra114_sdram_pad_size:
582 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
584 .type tegra_sdram_pad_save, %object
585 tegra_sdram_pad_save:
586 .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
591 * tegra30_tear_down_core
593 * copied into and executed from IRAM
594 * puts memory in self-refresh for LP0 and LP1
596 tegra30_tear_down_core:
597 bl tegra30_sdram_self_refresh
598 bl tegra30_switch_cpu_to_clk32k
599 b tegra30_enter_sleep
602 * tegra30_switch_cpu_to_clk32k
604 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
605 * to the 32KHz clock.
606 * r4 = TEGRA_PMC_BASE
607 * r5 = TEGRA_CLK_RESET_BASE
608 * r6 = TEGRA_FLOW_CTRL_BASE
609 * r7 = TEGRA_TMRUS_BASE
612 tegra30_switch_cpu_to_clk32k:
614 * start by jumping to CLKM to safely disable PLLs, then jump to
618 str r0, [r5, #CLK_RESET_SCLK_BURST]
619 /* 2uS delay delay between changing SCLK and CCLK */
622 wait_until r1, r7, r9
623 str r0, [r5, #CLK_RESET_CCLK_BURST]
625 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
626 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
628 /* switch the clock source of mselect to be CLK_M */
629 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
630 orr r0, r0, #MSELECT_CLKM
631 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
633 /* 2uS delay delay between changing SCLK and disabling PLLs */
636 wait_until r1, r7, r9
638 /* disable PLLM via PMC in LP1 */
639 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
640 bic r0, r0, #(1 << 12)
641 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
643 /* disable PLLP, PLLA, PLLC and PLLX */
644 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
645 bic r0, r0, #(1 << 30)
646 str r0, [r5, #CLK_RESET_PLLP_BASE]
647 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
648 bic r0, r0, #(1 << 30)
649 str r0, [r5, #CLK_RESET_PLLA_BASE]
650 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
651 bic r0, r0, #(1 << 30)
652 str r0, [r5, #CLK_RESET_PLLC_BASE]
653 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
654 bic r0, r0, #(1 << 30)
655 str r0, [r5, #CLK_RESET_PLLX_BASE]
659 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
663 mov r0, #0 /* brust policy = 32KHz */
664 str r0, [r5, #CLK_RESET_SCLK_BURST]
669 * tegra30_enter_sleep
671 * uses flow controller to enter sleep state
672 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
673 * executes from SDRAM with target state is LP2
674 * r6 = TEGRA_FLOW_CTRL_BASE
679 cpu_to_csr_reg r2, r1
681 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
682 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
685 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
687 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
688 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
689 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
691 cpu_to_halt_reg r2, r1
694 ldr r0, [r6, r2] /* memory barrier */
699 wfi /* CPU should be power gated here */
701 /* !!!FIXME!!! Implement halt failure handler */
705 * tegra30_sdram_self_refresh
707 * called with MMU off and caches disabled
708 * must be executed from IRAM
709 * r4 = TEGRA_PMC_BASE
710 * r5 = TEGRA_CLK_RESET_BASE
711 * r6 = TEGRA_FLOW_CTRL_BASE
712 * r7 = TEGRA_TMRUS_BASE
715 tegra30_sdram_self_refresh:
717 adr r8, tegra_sdram_pad_save
718 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
720 adreq r2, tegra30_sdram_pad_address
721 ldreq r3, tegra30_sdram_pad_size
723 adreq r2, tegra114_sdram_pad_address
724 ldreq r3, tegra114_sdram_pad_size
726 adreq r2, tegra124_sdram_pad_address
727 ldreq r3, tegra30_sdram_pad_size
732 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
735 str r1, [r8, r9] @ save the content of the addr
745 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
747 ldreq r0, =TEGRA_EMC0_BASE
749 ldreq r0, =TEGRA124_EMC_BASE
754 str r1, [r0, #EMC_ZCAL_INTERVAL]
755 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
756 ldr r1, [r0, #EMC_CFG]
757 bic r1, r1, #(1 << 28)
758 bicne r1, r1, #(1 << 29)
759 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
761 emc_timing_update r1, r0
765 wait_until r1, r7, r2
768 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
769 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
770 bne emc_wait_auto_cal
773 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
776 ldr r1, [r0, #EMC_EMC_STATUS]
781 str r1, [r0, #EMC_SELF_REF]
783 emc_device_mask r1, r0
786 ldr r2, [r0, #EMC_EMC_STATUS]
789 bne emcself @ loop until DDR in self-refresh
791 /* Put VTTGEN in the lowest power mode */
792 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
793 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
795 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
796 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
798 orreq r1, r1, #7 @ set E_NO_VTTGEN
800 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
802 emc_timing_update r1, r0
804 /* Tegra114 had dual EMC channel, now config the other one */
806 bne no_dual_emc_chanl
807 mov32 r1, TEGRA_EMC1_BASE
810 bne enter_self_refresh
813 ldr r1, [r4, #PMC_CTRL]
814 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
817 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
818 * and COMP in the lowest power mode when LP1.
821 str r1, [r4, #PMC_IO_DPD_REQ]
829 /* dummy symbol for end of IRAM */
830 .align L1_CACHE_SHIFT
831 .global tegra30_iram_end