2 * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/kernel.h>
19 #include <linux/clk.h>
22 #include <linux/of_address.h>
23 #include <linux/tegra-powergate.h>
31 #define TEGRA_POWER_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
32 #define TEGRA_POWER_SYSCLK_OE (1 << 11) /* system clock enable */
33 #define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
34 #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
35 #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
38 #define PMC_CTRL_INTR_LOW (1 << 17)
39 #define PMC_PWRGATE_TOGGLE 0x30
40 #define PMC_PWRGATE_TOGGLE_START (1 << 8)
41 #define PMC_REMOVE_CLAMPING 0x34
42 #define PMC_PWRGATE_STATUS 0x38
44 #define PMC_SCRATCH0 0x50
45 #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
46 #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
47 #define PMC_SCRATCH0_MODE_RCM (1 << 1)
48 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
49 PMC_SCRATCH0_MODE_BOOTLOADER | \
50 PMC_SCRATCH0_MODE_RCM)
52 #define PMC_CPUPWRGOOD_TIMER 0xc8
53 #define PMC_CPUPWROFF_TIMER 0xcc
55 static u8 tegra_cpu_domains[] = {
56 0xFF, /* not available for CPU0 */
61 static DEFINE_SPINLOCK(tegra_powergate_lock);
63 static void __iomem *tegra_pmc_base;
64 static bool tegra_pmc_invert_interrupt;
65 static struct clk *tegra_pclk;
68 u32 cpu_good_time; /* CPU power good time in uS */
69 u32 cpu_off_time; /* CPU power off time in uS */
70 u32 core_osc_time; /* Core power good osc time in uS */
71 u32 core_pmu_time; /* Core power good pmu time in uS */
72 u32 core_off_time; /* Core power off time in uS */
73 bool corereq_high; /* Core power request active-high */
74 bool sysclkreq_high; /* System clock request active-high */
75 bool combined_req; /* Combined pwr req for CPU & Core */
76 bool cpu_pwr_good_en; /* CPU power good signal is enabled */
77 u32 lp0_vec_phy_addr; /* The phy addr of LP0 warm boot code */
78 u32 lp0_vec_size; /* The size of LP0 warm boot code */
79 enum tegra_suspend_mode suspend_mode;
81 static struct pmc_pm_data pmc_pm_data;
83 static inline u32 tegra_pmc_readl(u32 reg)
85 return readl(tegra_pmc_base + reg);
88 static inline void tegra_pmc_writel(u32 val, u32 reg)
90 writel(val, tegra_pmc_base + reg);
93 static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
95 if (cpuid <= 0 || cpuid >= num_possible_cpus())
97 return tegra_cpu_domains[cpuid];
100 static bool tegra_pmc_powergate_is_powered(int id)
102 return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
105 static int tegra_pmc_powergate_set(int id, bool new_state)
110 spin_lock_irqsave(&tegra_powergate_lock, flags);
112 old_state = tegra_pmc_powergate_is_powered(id);
113 WARN_ON(old_state == new_state);
115 tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
117 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
122 static int tegra_pmc_powergate_remove_clamping(int id)
127 * Tegra has a bug where PCIE and VDE clamping masks are
128 * swapped relatively to the partition ids.
130 if (id == TEGRA_POWERGATE_VDEC)
131 mask = (1 << TEGRA_POWERGATE_PCIE);
132 else if (id == TEGRA_POWERGATE_PCIE)
133 mask = (1 << TEGRA_POWERGATE_VDEC);
137 tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
142 bool tegra_pmc_cpu_is_powered(int cpuid)
146 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
149 return tegra_pmc_powergate_is_powered(id);
152 int tegra_pmc_cpu_power_on(int cpuid)
156 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
159 return tegra_pmc_powergate_set(id, true);
162 int tegra_pmc_cpu_remove_clamping(int cpuid)
166 id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
169 return tegra_pmc_powergate_remove_clamping(id);
172 void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
176 val = tegra_pmc_readl(PMC_SCRATCH0);
177 val &= ~PMC_SCRATCH0_MODE_MASK;
180 if (strcmp(cmd, "recovery") == 0)
181 val |= PMC_SCRATCH0_MODE_RECOVERY;
183 if (strcmp(cmd, "bootloader") == 0)
184 val |= PMC_SCRATCH0_MODE_BOOTLOADER;
186 if (strcmp(cmd, "forced-recovery") == 0)
187 val |= PMC_SCRATCH0_MODE_RCM;
190 tegra_pmc_writel(val, PMC_SCRATCH0);
192 val = tegra_pmc_readl(0);
194 tegra_pmc_writel(val, 0);
197 #ifdef CONFIG_PM_SLEEP
198 static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
200 unsigned long long ticks;
201 unsigned long long pclk;
202 static unsigned long tegra_last_pclk;
204 if (WARN_ON_ONCE(rate <= 0))
209 if ((rate != tegra_last_pclk)) {
210 ticks = (us_on * pclk) + 999999ull;
211 do_div(ticks, 1000000);
212 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
214 ticks = (us_off * pclk) + 999999ull;
215 do_div(ticks, 1000000);
216 tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
219 tegra_last_pclk = pclk;
222 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
224 return pmc_pm_data.suspend_mode;
227 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
229 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
232 pmc_pm_data.suspend_mode = mode;
235 void tegra_pmc_suspend(void)
237 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
240 void tegra_pmc_resume(void)
242 tegra_pmc_writel(0x0, PMC_SCRATCH41);
245 void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
248 unsigned long rate = 0;
250 reg = tegra_pmc_readl(PMC_CTRL);
251 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
252 reg &= ~TEGRA_POWER_EFFECT_LP0;
254 switch (tegra_chip_id) {
260 csr_reg = flowctrl_read_cpu_csr(0);
261 csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
262 csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
263 flowctrl_write_cpu_csr(0, csr_reg);
268 case TEGRA_SUSPEND_LP1:
271 case TEGRA_SUSPEND_LP2:
272 rate = clk_get_rate(tegra_pclk);
278 set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
281 tegra_pmc_writel(reg, PMC_CTRL);
284 void tegra_pmc_suspend_init(void)
288 /* Always enable CPU power request */
289 reg = tegra_pmc_readl(PMC_CTRL);
290 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
291 tegra_pmc_writel(reg, PMC_CTRL);
293 reg = tegra_pmc_readl(PMC_CTRL);
295 if (!pmc_pm_data.sysclkreq_high)
296 reg |= TEGRA_POWER_SYSCLK_POLARITY;
298 reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
300 /* configure the output polarity while the request is tristated */
301 tegra_pmc_writel(reg, PMC_CTRL);
303 /* now enable the request */
304 reg |= TEGRA_POWER_SYSCLK_OE;
305 tegra_pmc_writel(reg, PMC_CTRL);
309 static const struct of_device_id matches[] __initconst = {
310 { .compatible = "nvidia,tegra124-pmc" },
311 { .compatible = "nvidia,tegra114-pmc" },
312 { .compatible = "nvidia,tegra30-pmc" },
313 { .compatible = "nvidia,tegra20-pmc" },
317 void __init tegra_pmc_init_irq(void)
319 struct device_node *np;
322 np = of_find_matching_node(NULL, matches);
325 tegra_pmc_base = of_iomap(np, 0);
327 tegra_pmc_invert_interrupt = of_property_read_bool(np,
328 "nvidia,invert-interrupt");
330 val = tegra_pmc_readl(PMC_CTRL);
331 if (tegra_pmc_invert_interrupt)
332 val |= PMC_CTRL_INTR_LOW;
334 val &= ~PMC_CTRL_INTR_LOW;
335 tegra_pmc_writel(val, PMC_CTRL);
338 void __init tegra_pmc_init(void)
340 struct device_node *np;
342 enum tegra_suspend_mode suspend_mode;
343 u32 core_good_time[2] = {0, 0};
344 u32 lp0_vec[2] = {0, 0};
346 np = of_find_matching_node(NULL, matches);
349 tegra_pclk = of_clk_get_by_name(np, "pclk");
350 WARN_ON(IS_ERR(tegra_pclk));
352 /* Grabbing the power management configurations */
353 if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
354 suspend_mode = TEGRA_SUSPEND_NONE;
358 suspend_mode = TEGRA_SUSPEND_LP0;
361 suspend_mode = TEGRA_SUSPEND_LP1;
364 suspend_mode = TEGRA_SUSPEND_LP2;
367 suspend_mode = TEGRA_SUSPEND_NONE;
371 suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
373 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
374 suspend_mode = TEGRA_SUSPEND_NONE;
375 pmc_pm_data.cpu_good_time = prop;
377 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
378 suspend_mode = TEGRA_SUSPEND_NONE;
379 pmc_pm_data.cpu_off_time = prop;
381 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
382 core_good_time, ARRAY_SIZE(core_good_time)))
383 suspend_mode = TEGRA_SUSPEND_NONE;
384 pmc_pm_data.core_osc_time = core_good_time[0];
385 pmc_pm_data.core_pmu_time = core_good_time[1];
387 if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
389 suspend_mode = TEGRA_SUSPEND_NONE;
390 pmc_pm_data.core_off_time = prop;
392 pmc_pm_data.corereq_high = of_property_read_bool(np,
393 "nvidia,core-power-req-active-high");
395 pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
396 "nvidia,sys-clock-req-active-high");
398 pmc_pm_data.combined_req = of_property_read_bool(np,
399 "nvidia,combined-power-req");
401 pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
402 "nvidia,cpu-pwr-good-en");
404 if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
405 ARRAY_SIZE(lp0_vec)))
406 if (suspend_mode == TEGRA_SUSPEND_LP0)
407 suspend_mode = TEGRA_SUSPEND_LP1;
409 pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
410 pmc_pm_data.lp0_vec_size = lp0_vec[1];
412 pmc_pm_data.suspend_mode = suspend_mode;