2 * arch/arm/mach-tegra/include/mach/uncompress.h
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 Google, Inc.
6 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
9 * Colin Cross <ccross@google.com>
10 * Erik Gilling <konkers@google.com>
11 * Doug Anderson <dianders@chromium.org>
12 * Stephen Warren <swarren@nvidia.com>
14 * This software is licensed under the terms of the GNU General Public
15 * License version 2, as published by the Free Software Foundation, and
16 * may be copied, distributed, and modified under those terms.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 #ifndef __MACH_TEGRA_UNCOMPRESS_H
26 #define __MACH_TEGRA_UNCOMPRESS_H
28 #include <linux/types.h>
29 #include <linux/serial_reg.h>
31 #include <mach/iomap.h>
32 #include <mach/irammap.h>
34 #define BIT(x) (1 << (x))
35 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
37 #define DEBUG_UART_SHIFT 2
41 static void putc(int c)
46 while (!(uart[UART_LSR << DEBUG_UART_SHIFT] & UART_LSR_THRE))
48 uart[UART_TX << DEBUG_UART_SHIFT] = c;
51 static inline void flush(void)
55 static inline void save_uart_address(void)
57 u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET);
60 buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE;
74 TEGRA_CLK_RESET_BASE + 0x04,
75 TEGRA_CLK_RESET_BASE + 0x10,
80 TEGRA_CLK_RESET_BASE + 0x04,
81 TEGRA_CLK_RESET_BASE + 0x10,
86 TEGRA_CLK_RESET_BASE + 0x08,
87 TEGRA_CLK_RESET_BASE + 0x14,
92 TEGRA_CLK_RESET_BASE + 0x0c,
93 TEGRA_CLK_RESET_BASE + 0x18,
98 TEGRA_CLK_RESET_BASE + 0x0c,
99 TEGRA_CLK_RESET_BASE + 0x18,
104 static inline bool uart_clocked(int i)
106 if (*(u8 *)uarts[i].reset_reg & BIT(uarts[i].bit))
109 if (!(*(u8 *)uarts[i].clock_reg & BIT(uarts[i].bit)))
115 #ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
116 int auto_odmdata(void)
118 volatile u32 *pmc = (volatile u32 *)TEGRA_PMC_BASE;
119 u32 odmdata = pmc[0xa0 / 4];
122 * Bits 19:18 are the console type: 0=default, 1=none, 2==DCC, 3==UART
123 * Some boards apparently swap the last two values, but we don't have
124 * any way of catering for that here, so we just accept either. If this
125 * doesn't make sense for your board, just don't enable this feature.
127 * Bits 17:15 indicate the UART to use, 0/1/2/3/4 are UART A/B/C/D/E.
130 switch ((odmdata >> 18) & 3) {
138 return (odmdata >> 15) & 7;
142 #ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH
143 int auto_scratch(void)
148 * Look for the first UART that:
149 * a) Is not in reset.
151 * c) Has a 'D' in the scratchpad register.
153 * Note that on Tegra30, the first two conditions are required, since
154 * if not true, accesses to the UART scratch register will hang.
155 * Tegra20 doesn't have this issue.
157 * The intent is that the bootloader will tell the kernel which UART
158 * to use by setting up those conditions. If nothing found, we'll fall
159 * back to what's specified in TEGRA_DEBUG_UART_BASE.
161 for (i = 0; i < ARRAY_SIZE(uarts); i++) {
162 if (!uart_clocked(i))
165 uart = (volatile u8 *)uarts[i].base;
166 if (uart[UART_SCR << DEBUG_UART_SHIFT] != 'D')
177 * Setup before decompression. This is where we do UART selection for
178 * earlyprintk and init the uart_base register.
180 static inline void arch_decomp_setup(void)
182 int uart_id, auto_uart_id;
183 volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
186 #if defined(CONFIG_TEGRA_DEBUG_UARTA)
188 #elif defined(CONFIG_TEGRA_DEBUG_UARTB)
190 #elif defined(CONFIG_TEGRA_DEBUG_UARTC)
192 #elif defined(CONFIG_TEGRA_DEBUG_UARTD)
194 #elif defined(CONFIG_TEGRA_DEBUG_UARTE)
200 #if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
201 auto_uart_id = auto_odmdata();
202 #elif defined(CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH)
203 auto_uart_id = auto_scratch();
207 if (auto_uart_id != -1)
208 uart_id = auto_uart_id;
210 if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
211 !uart_clocked(uart_id))
214 uart = (volatile u8 *)uarts[uart_id].base;
220 chip = (apb_misc[0x804 / 4] >> 8) & 0xff;
226 uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB;
227 uart[UART_DLL << DEBUG_UART_SHIFT] = div & 0xff;
228 uart[UART_DLM << DEBUG_UART_SHIFT] = div >> 8;
229 uart[UART_LCR << DEBUG_UART_SHIFT] = 3;
232 static inline void arch_decomp_wdog(void)