2 * arch/arm/mach-tegra/fuse.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@android.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
22 #include <linux/export.h>
23 #include <linux/tegra-soc.h>
29 #define FUSE_UID_LOW 0x108
30 #define FUSE_UID_HIGH 0x10c
31 #define FUSE_SKU_INFO 0x110
33 #define TEGRA20_FUSE_SPARE_BIT 0x200
34 #define TEGRA30_FUSE_SPARE_BIT 0x244
37 int tegra_cpu_process_id;
38 int tegra_core_process_id;
40 int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
41 int tegra_soc_speedo_id;
42 enum tegra_revision tegra_revision;
44 static int tegra_fuse_spare_bit;
45 static void (*tegra_init_speedo_data)(void);
47 /* The BCT to use at boot is specified by board straps that can be read
48 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
50 int tegra_bct_strapping;
52 #define STRAP_OPT 0x008
53 #define GMI_AD0 (1 << 4)
54 #define GMI_AD1 (1 << 5)
55 #define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
56 #define RAM_CODE_SHIFT 4
58 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
59 [TEGRA_REVISION_UNKNOWN] = "unknown",
60 [TEGRA_REVISION_A01] = "A01",
61 [TEGRA_REVISION_A02] = "A02",
62 [TEGRA_REVISION_A03] = "A03",
63 [TEGRA_REVISION_A03p] = "A03 prime",
64 [TEGRA_REVISION_A04] = "A04",
67 u32 tegra_fuse_readl(unsigned long offset)
69 return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
72 bool tegra_spare_fuse(int bit)
74 return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
77 static enum tegra_revision tegra_get_revision(u32 id)
79 u32 minor_rev = (id >> 16) & 0xf;
83 return TEGRA_REVISION_A01;
85 return TEGRA_REVISION_A02;
87 if (tegra_chip_id == TEGRA20 &&
88 (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
89 return TEGRA_REVISION_A03p;
91 return TEGRA_REVISION_A03;
93 return TEGRA_REVISION_A04;
95 return TEGRA_REVISION_UNKNOWN;
99 static void tegra_get_process_id(void)
103 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
104 tegra_cpu_process_id = (reg >> 6) & 3;
105 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
106 tegra_core_process_id = (reg >> 12) & 3;
109 u32 tegra_read_chipid(void)
111 return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
114 void tegra_init_fuse(void)
118 u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
120 writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
122 reg = tegra_fuse_readl(FUSE_SKU_INFO);
123 tegra_sku_id = reg & 0xFF;
125 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
126 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
128 id = tegra_read_chipid();
129 tegra_chip_id = (id >> 8) & 0xff;
131 switch (tegra_chip_id) {
133 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
134 tegra_init_speedo_data = &tegra20_init_speedo_data;
137 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
138 tegra_init_speedo_data = &tegra30_init_speedo_data;
141 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
142 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
143 tegra_init_speedo_data = &tegra_get_process_id;
146 tegra_revision = tegra_get_revision(id);
147 tegra_init_speedo_data();
149 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
150 tegra_revision_name[tegra_revision],
151 tegra_sku_id, tegra_cpu_process_id,
152 tegra_core_process_id);
155 unsigned long long tegra_chip_uid(void)
157 unsigned long long lo, hi;
159 lo = tegra_fuse_readl(FUSE_UID_LOW);
160 hi = tegra_fuse_readl(FUSE_UID_HIGH);
161 return (hi << 32ull) | lo;
163 EXPORT_SYMBOL(tegra_chip_uid);