arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/sh_intc.h>
  32 #include <linux/sh_timer.h>
  33 #include <mach/hardware.h>
  34 #include <mach/irqs.h>
  35 #include <mach/sh73a0.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/mach/arch.h>
  38
  39 static struct plat_sci_port scif0_platform_data = {
  40         .mapbase        = 0xe6c40000,
  41         .flags          = UPF_BOOT_AUTOCONF,
  42         .scscr          = SCSCR_RE | SCSCR_TE,
  43         .scbrr_algo_id  = SCBRR_ALGO_4,
  44         .type           = PORT_SCIFA,
  45         .irqs           = { gic_spi(72), gic_spi(72),
  46                             gic_spi(72), gic_spi(72) },
  47 };
  48
  49 static struct platform_device scif0_device = {
  50         .name           = "sh-sci",
  51         .id             = 0,
  52         .dev            = {
  53                 .platform_data  = &scif0_platform_data,
  54         },
  55 };
  56
  57 static struct plat_sci_port scif1_platform_data = {
  58         .mapbase        = 0xe6c50000,
  59         .flags          = UPF_BOOT_AUTOCONF,
  60         .scscr          = SCSCR_RE | SCSCR_TE,
  61         .scbrr_algo_id  = SCBRR_ALGO_4,
  62         .type           = PORT_SCIFA,
  63         .irqs           = { gic_spi(73), gic_spi(73),
  64                             gic_spi(73), gic_spi(73) },
  65 };
  66
  67 static struct platform_device scif1_device = {
  68         .name           = "sh-sci",
  69         .id             = 1,
  70         .dev            = {
  71                 .platform_data  = &scif1_platform_data,
  72         },
  73 };
  74
  75 static struct plat_sci_port scif2_platform_data = {
  76         .mapbase        = 0xe6c60000,
  77         .flags          = UPF_BOOT_AUTOCONF,
  78         .scscr          = SCSCR_RE | SCSCR_TE,
  79         .scbrr_algo_id  = SCBRR_ALGO_4,
  80         .type           = PORT_SCIFA,
  81         .irqs           = { gic_spi(74), gic_spi(74),
  82                             gic_spi(74), gic_spi(74) },
  83 };
  84
  85 static struct platform_device scif2_device = {
  86         .name           = "sh-sci",
  87         .id             = 2,
  88         .dev            = {
  89                 .platform_data  = &scif2_platform_data,
  90         },
  91 };
  92
  93 static struct plat_sci_port scif3_platform_data = {
  94         .mapbase        = 0xe6c70000,
  95         .flags          = UPF_BOOT_AUTOCONF,
  96         .scscr          = SCSCR_RE | SCSCR_TE,
  97         .scbrr_algo_id  = SCBRR_ALGO_4,
  98         .type           = PORT_SCIFA,
  99         .irqs           = { gic_spi(75), gic_spi(75),
 100                             gic_spi(75), gic_spi(75) },
 101 };
 102
 103 static struct platform_device scif3_device = {
 104         .name           = "sh-sci",
 105         .id             = 3,
 106         .dev            = {
 107                 .platform_data  = &scif3_platform_data,
 108         },
 109 };
 110
 111 static struct plat_sci_port scif4_platform_data = {
 112         .mapbase        = 0xe6c80000,
 113         .flags          = UPF_BOOT_AUTOCONF,
 114         .scscr          = SCSCR_RE | SCSCR_TE,
 115         .scbrr_algo_id  = SCBRR_ALGO_4,
 116         .type           = PORT_SCIFA,
 117         .irqs           = { gic_spi(78), gic_spi(78),
 118                             gic_spi(78), gic_spi(78) },
 119 };
 120
 121 static struct platform_device scif4_device = {
 122         .name           = "sh-sci",
 123         .id             = 4,
 124         .dev            = {
 125                 .platform_data  = &scif4_platform_data,
 126         },
 127 };
 128
 129 static struct plat_sci_port scif5_platform_data = {
 130         .mapbase        = 0xe6cb0000,
 131         .flags          = UPF_BOOT_AUTOCONF,
 132         .scscr          = SCSCR_RE | SCSCR_TE,
 133         .scbrr_algo_id  = SCBRR_ALGO_4,
 134         .type           = PORT_SCIFA,
 135         .irqs           = { gic_spi(79), gic_spi(79),
 136                             gic_spi(79), gic_spi(79) },
 137 };
 138
 139 static struct platform_device scif5_device = {
 140         .name           = "sh-sci",
 141         .id             = 5,
 142         .dev            = {
 143                 .platform_data  = &scif5_platform_data,
 144         },
 145 };
 146
 147 static struct plat_sci_port scif6_platform_data = {
 148         .mapbase        = 0xe6cc0000,
 149         .flags          = UPF_BOOT_AUTOCONF,
 150         .scscr          = SCSCR_RE | SCSCR_TE,
 151         .scbrr_algo_id  = SCBRR_ALGO_4,
 152         .type           = PORT_SCIFA,
 153         .irqs           = { gic_spi(156), gic_spi(156),
 154                             gic_spi(156), gic_spi(156) },
 155 };
 156
 157 static struct platform_device scif6_device = {
 158         .name           = "sh-sci",
 159         .id             = 6,
 160         .dev            = {
 161                 .platform_data  = &scif6_platform_data,
 162         },
 163 };
 164
 165 static struct plat_sci_port scif7_platform_data = {
 166         .mapbase        = 0xe6cd0000,
 167         .flags          = UPF_BOOT_AUTOCONF,
 168         .scscr          = SCSCR_RE | SCSCR_TE,
 169         .scbrr_algo_id  = SCBRR_ALGO_4,
 170         .type           = PORT_SCIFA,
 171         .irqs           = { gic_spi(143), gic_spi(143),
 172                             gic_spi(143), gic_spi(143) },
 173 };
 174
 175 static struct platform_device scif7_device = {
 176         .name           = "sh-sci",
 177         .id             = 7,
 178         .dev            = {
 179                 .platform_data  = &scif7_platform_data,
 180         },
 181 };
 182
 183 static struct plat_sci_port scif8_platform_data = {
 184         .mapbase        = 0xe6c30000,
 185         .flags          = UPF_BOOT_AUTOCONF,
 186         .scscr          = SCSCR_RE | SCSCR_TE,
 187         .scbrr_algo_id  = SCBRR_ALGO_4,
 188         .type           = PORT_SCIFB,
 189         .irqs           = { gic_spi(80), gic_spi(80),
 190                             gic_spi(80), gic_spi(80) },
 191 };
 192
 193 static struct platform_device scif8_device = {
 194         .name           = "sh-sci",
 195         .id             = 8,
 196         .dev            = {
 197                 .platform_data  = &scif8_platform_data,
 198         },
 199 };
 200
 201 static struct sh_timer_config cmt10_platform_data = {
 202         .name = "CMT10",
 203         .channel_offset = 0x10,
 204         .timer_bit = 0,
 205         .clockevent_rating = 125,
 206         .clocksource_rating = 125,
 207 };
 208
 209 static struct resource cmt10_resources[] = {
 210         [0] = {
 211                 .name   = "CMT10",
 212                 .start  = 0xe6138010,
 213                 .end    = 0xe613801b,
 214                 .flags  = IORESOURCE_MEM,
 215         },
 216         [1] = {
 217                 .start  = gic_spi(65),
 218                 .flags  = IORESOURCE_IRQ,
 219         },
 220 };
 221
 222 static struct platform_device cmt10_device = {
 223         .name           = "sh_cmt",
 224         .id             = 10,
 225         .dev = {
 226                 .platform_data  = &cmt10_platform_data,
 227         },
 228         .resource       = cmt10_resources,
 229         .num_resources  = ARRAY_SIZE(cmt10_resources),
 230 };
 231
 232 /* TMU */
 233 static struct sh_timer_config tmu00_platform_data = {
 234         .name = "TMU00",
 235         .channel_offset = 0x4,
 236         .timer_bit = 0,
 237         .clockevent_rating = 200,
 238 };
 239
 240 static struct resource tmu00_resources[] = {
 241         [0] = {
 242                 .name   = "TMU00",
 243                 .start  = 0xfff60008,
 244                 .end    = 0xfff60013,
 245                 .flags  = IORESOURCE_MEM,
 246         },
 247         [1] = {
 248                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
 249                 .flags  = IORESOURCE_IRQ,
 250         },
 251 };
 252
 253 static struct platform_device tmu00_device = {
 254         .name           = "sh_tmu",
 255         .id             = 0,
 256         .dev = {
 257                 .platform_data  = &tmu00_platform_data,
 258         },
 259         .resource       = tmu00_resources,
 260         .num_resources  = ARRAY_SIZE(tmu00_resources),
 261 };
 262
 263 static struct sh_timer_config tmu01_platform_data = {
 264         .name = "TMU01",
 265         .channel_offset = 0x10,
 266         .timer_bit = 1,
 267         .clocksource_rating = 200,
 268 };
 269
 270 static struct resource tmu01_resources[] = {
 271         [0] = {
 272                 .name   = "TMU01",
 273                 .start  = 0xfff60014,
 274                 .end    = 0xfff6001f,
 275                 .flags  = IORESOURCE_MEM,
 276         },
 277         [1] = {
 278                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
 279                 .flags  = IORESOURCE_IRQ,
 280         },
 281 };
 282
 283 static struct platform_device tmu01_device = {
 284         .name           = "sh_tmu",
 285         .id             = 1,
 286         .dev = {
 287                 .platform_data  = &tmu01_platform_data,
 288         },
 289         .resource       = tmu01_resources,
 290         .num_resources  = ARRAY_SIZE(tmu01_resources),
 291 };
 292
 293 static struct resource i2c0_resources[] = {
 294         [0] = {
 295                 .name   = "IIC0",
 296                 .start  = 0xe6820000,
 297                 .end    = 0xe6820425 - 1,
 298                 .flags  = IORESOURCE_MEM,
 299         },
 300         [1] = {
 301                 .start  = gic_spi(167),
 302                 .end    = gic_spi(170),
 303                 .flags  = IORESOURCE_IRQ,
 304         },
 305 };
 306
 307 static struct resource i2c1_resources[] = {
 308         [0] = {
 309                 .name   = "IIC1",
 310                 .start  = 0xe6822000,
 311                 .end    = 0xe6822425 - 1,
 312                 .flags  = IORESOURCE_MEM,
 313         },
 314         [1] = {
 315                 .start  = gic_spi(51),
 316                 .end    = gic_spi(54),
 317                 .flags  = IORESOURCE_IRQ,
 318         },
 319 };
 320
 321 static struct resource i2c2_resources[] = {
 322         [0] = {
 323                 .name   = "IIC2",
 324                 .start  = 0xe6824000,
 325                 .end    = 0xe6824425 - 1,
 326                 .flags  = IORESOURCE_MEM,
 327         },
 328         [1] = {
 329                 .start  = gic_spi(171),
 330                 .end    = gic_spi(174),
 331                 .flags  = IORESOURCE_IRQ,
 332         },
 333 };
 334
 335 static struct resource i2c3_resources[] = {
 336         [0] = {
 337                 .name   = "IIC3",
 338                 .start  = 0xe6826000,
 339                 .end    = 0xe6826425 - 1,
 340                 .flags  = IORESOURCE_MEM,
 341         },
 342         [1] = {
 343                 .start  = gic_spi(183),
 344                 .end    = gic_spi(186),
 345                 .flags  = IORESOURCE_IRQ,
 346         },
 347 };
 348
 349 static struct resource i2c4_resources[] = {
 350         [0] = {
 351                 .name   = "IIC4",
 352                 .start  = 0xe6828000,
 353                 .end    = 0xe6828425 - 1,
 354                 .flags  = IORESOURCE_MEM,
 355         },
 356         [1] = {
 357                 .start  = gic_spi(187),
 358                 .end    = gic_spi(190),
 359                 .flags  = IORESOURCE_IRQ,
 360         },
 361 };
 362
 363 static struct platform_device i2c0_device = {
 364         .name           = "i2c-sh_mobile",
 365         .id             = 0,
 366         .resource       = i2c0_resources,
 367         .num_resources  = ARRAY_SIZE(i2c0_resources),
 368 };
 369
 370 static struct platform_device i2c1_device = {
 371         .name           = "i2c-sh_mobile",
 372         .id             = 1,
 373         .resource       = i2c1_resources,
 374         .num_resources  = ARRAY_SIZE(i2c1_resources),
 375 };
 376
 377 static struct platform_device i2c2_device = {
 378         .name           = "i2c-sh_mobile",
 379         .id             = 2,
 380         .resource       = i2c2_resources,
 381         .num_resources  = ARRAY_SIZE(i2c2_resources),
 382 };
 383
 384 static struct platform_device i2c3_device = {
 385         .name           = "i2c-sh_mobile",
 386         .id             = 3,
 387         .resource       = i2c3_resources,
 388         .num_resources  = ARRAY_SIZE(i2c3_resources),
 389 };
 390
 391 static struct platform_device i2c4_device = {
 392         .name           = "i2c-sh_mobile",
 393         .id             = 4,
 394         .resource       = i2c4_resources,
 395         .num_resources  = ARRAY_SIZE(i2c4_resources),
 396 };
 397
 398 /* Transmit sizes and respective CHCR register values */
 399 enum {
 400         XMIT_SZ_8BIT            = 0,
 401         XMIT_SZ_16BIT           = 1,
 402         XMIT_SZ_32BIT           = 2,
 403         XMIT_SZ_64BIT           = 7,
 404         XMIT_SZ_128BIT          = 3,
 405         XMIT_SZ_256BIT          = 4,
 406         XMIT_SZ_512BIT          = 5,
 407 };
 408
 409 /* log2(size / 8) - used to calculate number of transfers */
 410 #define TS_SHIFT {                      \
 411         [XMIT_SZ_8BIT]          = 0,    \
 412         [XMIT_SZ_16BIT]         = 1,    \
 413         [XMIT_SZ_32BIT]         = 2,    \
 414         [XMIT_SZ_64BIT]         = 3,    \
 415         [XMIT_SZ_128BIT]        = 4,    \
 416         [XMIT_SZ_256BIT]        = 5,    \
 417         [XMIT_SZ_512BIT]        = 6,    \
 418 }
 419
 420 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
 421 #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
 422 #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
 423
 424 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 425         {
 426                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 427                 .addr           = 0xe6c40020,
 428                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 429                 .mid_rid        = 0x21,
 430         }, {
 431                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 432                 .addr           = 0xe6c40024,
 433                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 434                 .mid_rid        = 0x22,
 435         }, {
 436                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 437                 .addr           = 0xe6c50020,
 438                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 439                 .mid_rid        = 0x25,
 440         }, {
 441                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 442                 .addr           = 0xe6c50024,
 443                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 444                 .mid_rid        = 0x26,
 445         }, {
 446                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 447                 .addr           = 0xe6c60020,
 448                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 449                 .mid_rid        = 0x29,
 450         }, {
 451                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 452                 .addr           = 0xe6c60024,
 453                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 454                 .mid_rid        = 0x2a,
 455         }, {
 456                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 457                 .addr           = 0xe6c70020,
 458                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 459                 .mid_rid        = 0x2d,
 460         }, {
 461                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 462                 .addr           = 0xe6c70024,
 463                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 464                 .mid_rid        = 0x2e,
 465         }, {
 466                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 467                 .addr           = 0xe6c80020,
 468                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 469                 .mid_rid        = 0x39,
 470         }, {
 471                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 472                 .addr           = 0xe6c80024,
 473                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 474                 .mid_rid        = 0x3a,
 475         }, {
 476                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 477                 .addr           = 0xe6cb0020,
 478                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 479                 .mid_rid        = 0x35,
 480         }, {
 481                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 482                 .addr           = 0xe6cb0024,
 483                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 484                 .mid_rid        = 0x36,
 485         }, {
 486                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 487                 .addr           = 0xe6cc0020,
 488                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 489                 .mid_rid        = 0x1d,
 490         }, {
 491                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 492                 .addr           = 0xe6cc0024,
 493                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 494                 .mid_rid        = 0x1e,
 495         }, {
 496                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 497                 .addr           = 0xe6cd0020,
 498                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 499                 .mid_rid        = 0x19,
 500         }, {
 501                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 502                 .addr           = 0xe6cd0024,
 503                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 504                 .mid_rid        = 0x1a,
 505         }, {
 506                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 507                 .addr           = 0xe6c30040,
 508                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 509                 .mid_rid        = 0x3d,
 510         }, {
 511                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 512                 .addr           = 0xe6c30060,
 513                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 514                 .mid_rid        = 0x3e,
 515         }, {
 516                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 517                 .addr           = 0xee100030,
 518                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 519                 .mid_rid        = 0xc1,
 520         }, {
 521                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 522                 .addr           = 0xee100030,
 523                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 524                 .mid_rid        = 0xc2,
 525         }, {
 526                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 527                 .addr           = 0xee120030,
 528                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 529                 .mid_rid        = 0xc9,
 530         }, {
 531                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 532                 .addr           = 0xee120030,
 533                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 534                 .mid_rid        = 0xca,
 535         }, {
 536                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 537                 .addr           = 0xee140030,
 538                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 539                 .mid_rid        = 0xcd,
 540         }, {
 541                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 542                 .addr           = 0xee140030,
 543                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 544                 .mid_rid        = 0xce,
 545         }, {
 546                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 547                 .addr           = 0xe6bd0034,
 548                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 549                 .mid_rid        = 0xd1,
 550         }, {
 551                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 552                 .addr           = 0xe6bd0034,
 553                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 554                 .mid_rid        = 0xd2,
 555         },
 556 };
 557
 558 #define DMAE_CHANNEL(_offset)                                   \
 559         {                                                       \
 560                 .offset         = _offset - 0x20,               \
 561                 .dmars          = _offset - 0x20 + 0x40,        \
 562         }
 563
 564 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 565         DMAE_CHANNEL(0x8000),
 566         DMAE_CHANNEL(0x8080),
 567         DMAE_CHANNEL(0x8100),
 568         DMAE_CHANNEL(0x8180),
 569         DMAE_CHANNEL(0x8200),
 570         DMAE_CHANNEL(0x8280),
 571         DMAE_CHANNEL(0x8300),
 572         DMAE_CHANNEL(0x8380),
 573         DMAE_CHANNEL(0x8400),
 574         DMAE_CHANNEL(0x8480),
 575         DMAE_CHANNEL(0x8500),
 576         DMAE_CHANNEL(0x8580),
 577         DMAE_CHANNEL(0x8600),
 578         DMAE_CHANNEL(0x8680),
 579         DMAE_CHANNEL(0x8700),
 580         DMAE_CHANNEL(0x8780),
 581         DMAE_CHANNEL(0x8800),
 582         DMAE_CHANNEL(0x8880),
 583         DMAE_CHANNEL(0x8900),
 584         DMAE_CHANNEL(0x8980),
 585 };
 586
 587 static const unsigned int ts_shift[] = TS_SHIFT;
 588
 589 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 590         .slave          = sh73a0_dmae_slaves,
 591         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 592         .channel        = sh73a0_dmae_channels,
 593         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 594         .ts_low_shift   = 3,
 595         .ts_low_mask    = 0x18,
 596         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
 597         .ts_high_mask   = 0x00300000,
 598         .ts_shift       = ts_shift,
 599         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 600         .dmaor_init     = DMAOR_DME,
 601 };
 602
 603 static struct resource sh73a0_dmae_resources[] = {
 604         {
 605                 /* Registers including DMAOR and channels including DMARSx */
 606                 .start  = 0xfe000020,
 607                 .end    = 0xfe008a00 - 1,
 608                 .flags  = IORESOURCE_MEM,
 609         },
 610         {
 611                 .name   = "error_irq",
 612                 .start  = gic_spi(129),
 613                 .end    = gic_spi(129),
 614                 .flags  = IORESOURCE_IRQ,
 615         },
 616         {
 617                 /* IRQ for channels 0-19 */
 618                 .start  = gic_spi(109),
 619                 .end    = gic_spi(128),
 620                 .flags  = IORESOURCE_IRQ,
 621         },
 622 };
 623
 624 static struct platform_device dma0_device = {
 625         .name           = "sh-dma-engine",
 626         .id             = 0,
 627         .resource       = sh73a0_dmae_resources,
 628         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 629         .dev            = {
 630                 .platform_data  = &sh73a0_dmae_platform_data,
 631         },
 632 };
 633
 634 static struct platform_device *sh73a0_early_devices[] __initdata = {
 635         &scif0_device,
 636         &scif1_device,
 637         &scif2_device,
 638         &scif3_device,
 639         &scif4_device,
 640         &scif5_device,
 641         &scif6_device,
 642         &scif7_device,
 643         &scif8_device,
 644         &cmt10_device,
 645         &tmu00_device,
 646         &tmu01_device,
 647 };
 648
 649 static struct platform_device *sh73a0_late_devices[] __initdata = {
 650         &i2c0_device,
 651         &i2c1_device,
 652         &i2c2_device,
 653         &i2c3_device,
 654         &i2c4_device,
 655         &dma0_device,
 656 };
 657
 658 #define SRCR2          0xe61580b0
 659
 660 void __init sh73a0_add_standard_devices(void)
 661 {
 662         /* Clear software reset bit on SY-DMAC module */
 663         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 664
 665         platform_add_devices(sh73a0_early_devices,
 666                             ARRAY_SIZE(sh73a0_early_devices));
 667         platform_add_devices(sh73a0_late_devices,
 668                             ARRAY_SIZE(sh73a0_late_devices));
 669 }
 670
 671 void __init sh73a0_add_early_devices(void)
 672 {
 673         early_platform_add_devices(sh73a0_early_devices,
 674                                    ARRAY_SIZE(sh73a0_early_devices));
 675 }