2 * r8a7779 processor support
4 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 * Copyright (C) 2013 Cogent Embedded, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqchip.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_data/dma-rcar-hpbdma.h>
29 #include <linux/platform_data/gpio-rcar.h>
30 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
31 #include <linux/platform_device.h>
32 #include <linux/delay.h>
33 #include <linux/input.h>
35 #include <linux/serial_sci.h>
36 #include <linux/sh_timer.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/usb/otg.h>
39 #include <linux/usb/hcd.h>
40 #include <linux/usb/ehci_pdriver.h>
41 #include <linux/usb/ohci_pdriver.h>
42 #include <linux/pm_runtime.h>
44 #include <asm/mach-types.h>
45 #include <asm/mach/arch.h>
46 #include <asm/mach/time.h>
47 #include <asm/mach/map.h>
48 #include <asm/hardware/cache-l2x0.h>
54 static struct map_desc r8a7779_io_desc[] __initdata = {
55 /* 2M entity map for 0xf0000000 (MPCORE) */
57 .virtual = 0xf0000000,
58 .pfn = __phys_to_pfn(0xf0000000),
60 .type = MT_DEVICE_NONSHARED
62 /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
64 .virtual = 0xfe000000,
65 .pfn = __phys_to_pfn(0xfe000000),
67 .type = MT_DEVICE_NONSHARED
71 void __init r8a7779_map_io(void)
74 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
78 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
79 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
80 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
81 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
82 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
84 #define INT2NTSR0 IOMEM(0xfe700060)
85 #define INT2NTSR1 IOMEM(0xfe700064)
87 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
88 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
89 .sense_bitfield_width = 2,
92 static struct resource irqpin0_resources[] __initdata = {
93 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
94 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
95 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
96 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
97 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
98 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
99 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
100 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
101 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
104 void __init r8a7779_init_irq_extpin_dt(int irlm)
106 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
110 pr_warn("r8a7779: unable to setup external irq pin mode\n");
114 tmp = ioread32(icr0);
116 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
118 tmp &= ~(1 << 23); /* IRL mode - not supported */
119 tmp |= (1 << 21); /* LVLMODE = 1 */
120 iowrite32(tmp, icr0);
124 void __init r8a7779_init_irq_extpin(int irlm)
126 r8a7779_init_irq_extpin_dt(irlm);
128 platform_device_register_resndata(
129 NULL, "renesas_intc_irqpin", -1,
130 irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
131 &irqpin0_platform_data, sizeof(irqpin0_platform_data));
135 static struct resource r8a7779_pfc_resources[] = {
136 DEFINE_RES_MEM(0xfffc0000, 0x023c),
139 static struct platform_device r8a7779_pfc_device = {
140 .name = "pfc-r8a7779",
142 .resource = r8a7779_pfc_resources,
143 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
146 #define R8A7779_GPIO(idx, npins) \
147 static struct resource r8a7779_gpio##idx##_resources[] = { \
148 DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \
149 DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \
152 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
153 .gpio_base = 32 * (idx), \
155 .number_of_pins = npins, \
156 .pctl_name = "pfc-r8a7779", \
159 static struct platform_device r8a7779_gpio##idx##_device = { \
160 .name = "gpio_rcar", \
162 .resource = r8a7779_gpio##idx##_resources, \
163 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
165 .platform_data = &r8a7779_gpio##idx##_platform_data, \
177 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
179 &r8a7779_gpio0_device,
180 &r8a7779_gpio1_device,
181 &r8a7779_gpio2_device,
182 &r8a7779_gpio3_device,
183 &r8a7779_gpio4_device,
184 &r8a7779_gpio5_device,
185 &r8a7779_gpio6_device,
188 void __init r8a7779_pinmux_init(void)
190 platform_add_devices(r8a7779_pinctrl_devices,
191 ARRAY_SIZE(r8a7779_pinctrl_devices));
195 #define R8A7779_SCIF(index, baseaddr, irq) \
196 static struct plat_sci_port scif##index##_platform_data = { \
198 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
199 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
202 static struct resource scif##index##_resources[] = { \
203 DEFINE_RES_MEM(baseaddr, 0x100), \
204 DEFINE_RES_IRQ(irq), \
207 static struct platform_device scif##index##_device = { \
210 .resource = scif##index##_resources, \
211 .num_resources = ARRAY_SIZE(scif##index##_resources), \
213 .platform_data = &scif##index##_platform_data, \
217 R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
218 R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
219 R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
220 R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
221 R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
222 R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
225 static struct sh_timer_config tmu0_platform_data = {
229 static struct resource tmu0_resources[] = {
230 DEFINE_RES_MEM(0xffd80000, 0x30),
231 DEFINE_RES_IRQ(gic_iid(0x40)),
232 DEFINE_RES_IRQ(gic_iid(0x41)),
233 DEFINE_RES_IRQ(gic_iid(0x42)),
236 static struct platform_device tmu0_device = {
240 .platform_data = &tmu0_platform_data,
242 .resource = tmu0_resources,
243 .num_resources = ARRAY_SIZE(tmu0_resources),
247 static struct resource rcar_i2c0_res[] = {
251 .flags = IORESOURCE_MEM,
253 .start = gic_iid(0x6f),
254 .flags = IORESOURCE_IRQ,
258 static struct platform_device i2c0_device = {
261 .resource = rcar_i2c0_res,
262 .num_resources = ARRAY_SIZE(rcar_i2c0_res),
265 static struct resource rcar_i2c1_res[] = {
269 .flags = IORESOURCE_MEM,
271 .start = gic_iid(0x72),
272 .flags = IORESOURCE_IRQ,
276 static struct platform_device i2c1_device = {
279 .resource = rcar_i2c1_res,
280 .num_resources = ARRAY_SIZE(rcar_i2c1_res),
283 static struct resource rcar_i2c2_res[] = {
287 .flags = IORESOURCE_MEM,
289 .start = gic_iid(0x70),
290 .flags = IORESOURCE_IRQ,
294 static struct platform_device i2c2_device = {
297 .resource = rcar_i2c2_res,
298 .num_resources = ARRAY_SIZE(rcar_i2c2_res),
301 static struct resource rcar_i2c3_res[] = {
305 .flags = IORESOURCE_MEM,
307 .start = gic_iid(0x71),
308 .flags = IORESOURCE_IRQ,
312 static struct platform_device i2c3_device = {
315 .resource = rcar_i2c3_res,
316 .num_resources = ARRAY_SIZE(rcar_i2c3_res),
319 static struct resource sata_resources[] = {
324 .flags = IORESOURCE_MEM,
327 .start = gic_iid(0x84),
328 .flags = IORESOURCE_IRQ,
332 static struct platform_device sata_device = {
335 .resource = sata_resources,
336 .num_resources = ARRAY_SIZE(sata_resources),
338 .dma_mask = &sata_device.dev.coherent_dma_mask,
339 .coherent_dma_mask = DMA_BIT_MASK(32),
344 static struct usb_phy *phy;
346 static int usb_power_on(struct platform_device *pdev)
351 pm_runtime_enable(&pdev->dev);
352 pm_runtime_get_sync(&pdev->dev);
359 static void usb_power_off(struct platform_device *pdev)
364 usb_phy_shutdown(phy);
366 pm_runtime_put_sync(&pdev->dev);
367 pm_runtime_disable(&pdev->dev);
370 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
373 * Below are recommended values from the datasheet;
374 * see [USB :: Setting of EHCI Internal Buffer].
376 /* EHCI IP internal buffer setting */
377 iowrite32(0x00ff0040, hcd->regs + 0x0094);
378 /* EHCI IP internal buffer enable */
379 iowrite32(0x00000001, hcd->regs + 0x009C);
384 static struct usb_ehci_pdata ehcix_pdata = {
385 .power_on = usb_power_on,
386 .power_off = usb_power_off,
387 .power_suspend = usb_power_off,
388 .pre_setup = ehci_init_internal_buffer,
391 static struct resource ehci0_resources[] = {
394 .end = 0xffe70400 - 1,
395 .flags = IORESOURCE_MEM,
398 .start = gic_iid(0x4c),
399 .flags = IORESOURCE_IRQ,
403 static struct platform_device ehci0_device = {
404 .name = "ehci-platform",
407 .dma_mask = &ehci0_device.dev.coherent_dma_mask,
408 .coherent_dma_mask = 0xffffffff,
409 .platform_data = &ehcix_pdata,
411 .num_resources = ARRAY_SIZE(ehci0_resources),
412 .resource = ehci0_resources,
415 static struct resource ehci1_resources[] = {
418 .end = 0xfff70400 - 1,
419 .flags = IORESOURCE_MEM,
422 .start = gic_iid(0x4d),
423 .flags = IORESOURCE_IRQ,
427 static struct platform_device ehci1_device = {
428 .name = "ehci-platform",
431 .dma_mask = &ehci1_device.dev.coherent_dma_mask,
432 .coherent_dma_mask = 0xffffffff,
433 .platform_data = &ehcix_pdata,
435 .num_resources = ARRAY_SIZE(ehci1_resources),
436 .resource = ehci1_resources,
439 static struct usb_ohci_pdata ohcix_pdata = {
440 .power_on = usb_power_on,
441 .power_off = usb_power_off,
442 .power_suspend = usb_power_off,
445 static struct resource ohci0_resources[] = {
448 .end = 0xffe70800 - 1,
449 .flags = IORESOURCE_MEM,
452 .start = gic_iid(0x4c),
453 .flags = IORESOURCE_IRQ,
457 static struct platform_device ohci0_device = {
458 .name = "ohci-platform",
461 .dma_mask = &ohci0_device.dev.coherent_dma_mask,
462 .coherent_dma_mask = 0xffffffff,
463 .platform_data = &ohcix_pdata,
465 .num_resources = ARRAY_SIZE(ohci0_resources),
466 .resource = ohci0_resources,
469 static struct resource ohci1_resources[] = {
472 .end = 0xfff70800 - 1,
473 .flags = IORESOURCE_MEM,
476 .start = gic_iid(0x4d),
477 .flags = IORESOURCE_IRQ,
481 static struct platform_device ohci1_device = {
482 .name = "ohci-platform",
485 .dma_mask = &ohci1_device.dev.coherent_dma_mask,
486 .coherent_dma_mask = 0xffffffff,
487 .platform_data = &ohcix_pdata,
489 .num_resources = ARRAY_SIZE(ohci1_resources),
490 .resource = ohci1_resources,
495 /* Asynchronous mode register bits */
496 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */
497 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */
498 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */
499 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */
500 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */
501 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */
502 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */
503 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */
504 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */
505 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */
506 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */
507 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */
508 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */
509 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */
510 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */
511 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */
512 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */
513 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */
514 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */
515 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */
516 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */
517 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */
518 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */
519 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */
520 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */
521 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */
522 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */
523 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */
524 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */
525 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */
526 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */
527 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */
528 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */
529 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */
530 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */
531 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */
532 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */
533 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */
534 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */
535 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */
536 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */
537 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */
538 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */
539 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */
540 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */
541 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */
542 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */
543 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */
544 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */
545 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */
546 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */
547 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */
548 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */
549 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */
550 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */
551 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */
552 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
553 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */
554 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */
555 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */
556 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */
557 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */
558 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
559 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */
560 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */
561 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */
562 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */
563 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */
564 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */
565 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */
566 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */
567 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */
569 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
571 .id = HPBDMA_SLAVE_SDHI0_TX,
572 .addr = 0xffe4c000 + 0x30,
573 .dcr = HPB_DMAE_DCR_SPDS_16BIT |
575 HPB_DMAE_DCR_DPDS_16BIT,
576 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
577 HPB_DMAE_ASYNCRSTR_ASRST22 |
578 HPB_DMAE_ASYNCRSTR_ASRST23,
579 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
580 HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
581 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
582 HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
584 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
587 .id = HPBDMA_SLAVE_SDHI0_RX,
588 .addr = 0xffe4c000 + 0x30,
589 .dcr = HPB_DMAE_DCR_SMDL |
590 HPB_DMAE_DCR_SPDS_16BIT |
591 HPB_DMAE_DCR_DPDS_16BIT,
592 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
593 HPB_DMAE_ASYNCRSTR_ASRST22 |
594 HPB_DMAE_ASYNCRSTR_ASRST23,
595 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
596 HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
597 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
598 HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
600 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
605 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
606 HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
607 HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
610 static struct hpb_dmae_pdata dma_platform_data __initdata = {
611 .slaves = hpb_dmae_slaves,
612 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
613 .channels = hpb_dmae_channels,
614 .num_channels = ARRAY_SIZE(hpb_dmae_channels),
620 .num_hw_channels = 44,
623 static struct resource hpb_dmae_resources[] __initdata = {
624 /* Channel registers */
625 DEFINE_RES_MEM(0xffc08000, 0x1000),
626 /* Common registers */
627 DEFINE_RES_MEM(0xffc09000, 0x170),
628 /* Asynchronous reset registers */
629 DEFINE_RES_MEM(0xffc00300, 4),
630 /* Asynchronous mode registers */
631 DEFINE_RES_MEM(0xffc00400, 4),
632 /* IRQ for DMA channels */
633 DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
636 static void __init r8a7779_register_hpb_dmae(void)
638 platform_device_register_resndata(NULL, "hpb-dma-engine",
639 -1, hpb_dmae_resources,
640 ARRAY_SIZE(hpb_dmae_resources),
642 sizeof(dma_platform_data));
645 static struct platform_device *r8a7779_early_devices[] __initdata = {
649 static struct platform_device *r8a7779_standard_devices[] __initdata = {
663 void __init r8a7779_add_standard_devices(void)
665 #ifdef CONFIG_CACHE_L2X0
666 /* Shared attribute override enable, 64K*16way */
667 l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
671 r8a7779_init_pm_domains();
673 platform_add_devices(r8a7779_early_devices,
674 ARRAY_SIZE(r8a7779_early_devices));
675 platform_add_devices(r8a7779_standard_devices,
676 ARRAY_SIZE(r8a7779_standard_devices));
677 r8a7779_register_hpb_dmae();
680 void __init r8a7779_add_early_devices(void)
682 early_platform_add_devices(r8a7779_early_devices,
683 ARRAY_SIZE(r8a7779_early_devices));
685 /* Early serial console setup is not included here due to
686 * memory map collisions. The SCIF serial ports in r8a7779
687 * are difficult to entity map 1:1 due to collision with the
688 * virtual memory range used by the coherent DMA code on ARM.
690 * Anyone wanting to debug early can remove UPF_IOREMAP from
691 * the sh-sci serial console platform data, adjust mapbase
692 * to a static M:N virt:phys mapping that needs to be added to
693 * the mappings passed with iotable_init() above.
695 * Then add a call to shmobile_setup_console() from this function.
697 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
698 * command line in case of the marzen board.
702 static struct platform_device *r8a7779_late_devices[] __initdata = {
709 void __init r8a7779_init_late(void)
712 phy = usb_get_phy(USB_PHY_TYPE_USB2);
714 shmobile_init_late();
715 platform_add_devices(r8a7779_late_devices,
716 ARRAY_SIZE(r8a7779_late_devices));
720 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
722 return 0; /* always allow wakeup */
725 void __init r8a7779_init_irq_dt(void)
727 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
731 /* route all interrupts to ARM */
732 __raw_writel(0xffffffff, INT2NTSR0);
733 __raw_writel(0x3fffffff, INT2NTSR1);
735 /* unmask all known interrupts in INTCS2 */
736 __raw_writel(0xfffffff0, INT2SMSKCR0);
737 __raw_writel(0xfff7ffff, INT2SMSKCR1);
738 __raw_writel(0xfffbffdf, INT2SMSKCR2);
739 __raw_writel(0xbffffffc, INT2SMSKCR3);
740 __raw_writel(0x003fee3f, INT2SMSKCR4);
743 #define MODEMR 0xffcc0020
745 u32 __init r8a7779_read_mode_pins(void)
748 static bool mode_valid;
751 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
753 mode = ioread32(modemr);
761 static const char *r8a7779_compat_dt[] __initdata = {
766 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
767 .map_io = r8a7779_map_io,
768 .init_early = shmobile_init_delay,
769 .init_irq = r8a7779_init_irq_dt,
770 .init_late = shmobile_init_late,
771 .dt_compat = r8a7779_compat_dt,
773 #endif /* CONFIG_USE_OF */