2 * R8A7740 processor support
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
21 #include <linux/irqchip.h>
22 #include <linux/irqchip/arm-gic.h>
23 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/serial_sci.h>
27 #include <linux/sh_dma.h>
28 #include <linux/sh_timer.h>
29 #include <linux/platform_data/sh_ipmmu.h>
31 #include <asm/mach-types.h>
32 #include <asm/mach/map.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/time.h>
35 #include <asm/hardware/cache-l2x0.h>
38 #include "dma-register.h"
40 #include "pm-rmobile.h"
43 static struct map_desc r8a7740_io_desc[] __initdata = {
46 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
49 .virtual = 0xe6000000,
50 .pfn = __phys_to_pfn(0xe6000000),
52 .type = MT_DEVICE_NONSHARED
54 #ifdef CONFIG_CACHE_L2X0
57 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
60 .virtual = 0xf0002000,
61 .pfn = __phys_to_pfn(0xf0100000),
63 .type = MT_DEVICE_NONSHARED
68 void __init r8a7740_map_io(void)
71 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
75 static const struct resource pfc_resources[] = {
76 DEFINE_RES_MEM(0xe6050000, 0x8000),
77 DEFINE_RES_MEM(0xe605800c, 0x0020),
80 void __init r8a7740_pinmux_init(void)
82 platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
83 ARRAY_SIZE(pfc_resources));
86 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
87 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
90 static struct resource irqpin0_resources[] = {
91 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
92 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
93 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
94 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
95 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
96 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
97 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
98 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
99 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
100 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
101 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
102 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
103 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
106 static struct platform_device irqpin0_device = {
107 .name = "renesas_intc_irqpin",
109 .resource = irqpin0_resources,
110 .num_resources = ARRAY_SIZE(irqpin0_resources),
112 .platform_data = &irqpin0_platform_data,
116 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
117 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
120 static struct resource irqpin1_resources[] = {
121 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
122 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
123 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
124 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
125 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
126 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
127 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
128 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
129 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
130 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
131 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
132 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
133 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
136 static struct platform_device irqpin1_device = {
137 .name = "renesas_intc_irqpin",
139 .resource = irqpin1_resources,
140 .num_resources = ARRAY_SIZE(irqpin1_resources),
142 .platform_data = &irqpin1_platform_data,
146 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
147 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
150 static struct resource irqpin2_resources[] = {
151 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
152 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
153 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
154 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
155 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
156 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
157 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
158 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
159 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
160 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
161 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
162 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
163 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
166 static struct platform_device irqpin2_device = {
167 .name = "renesas_intc_irqpin",
169 .resource = irqpin2_resources,
170 .num_resources = ARRAY_SIZE(irqpin2_resources),
172 .platform_data = &irqpin2_platform_data,
176 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
177 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
180 static struct resource irqpin3_resources[] = {
181 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
182 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
183 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
184 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
185 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
186 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
187 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
188 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
189 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
190 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
191 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
192 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
193 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
196 static struct platform_device irqpin3_device = {
197 .name = "renesas_intc_irqpin",
199 .resource = irqpin3_resources,
200 .num_resources = ARRAY_SIZE(irqpin3_resources),
202 .platform_data = &irqpin3_platform_data,
207 #define R8A7740_SCIF(scif_type, index, baseaddr, irq) \
208 static struct plat_sci_port scif##index##_platform_data = { \
210 .flags = UPF_BOOT_AUTOCONF, \
211 .scscr = SCSCR_RE | SCSCR_TE, \
214 static struct resource scif##index##_resources[] = { \
215 DEFINE_RES_MEM(baseaddr, 0x100), \
216 DEFINE_RES_IRQ(irq), \
219 static struct platform_device scif##index##_device = { \
222 .resource = scif##index##_resources, \
223 .num_resources = ARRAY_SIZE(scif##index##_resources), \
225 .platform_data = &scif##index##_platform_data, \
229 R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
230 R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
231 R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
232 R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
233 R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
234 R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
235 R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
236 R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
237 R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
240 static struct sh_timer_config cmt1_platform_data = {
241 .channels_mask = 0x3f,
244 static struct resource cmt1_resources[] = {
245 DEFINE_RES_MEM(0xe6138000, 0x170),
246 DEFINE_RES_IRQ(gic_spi(58)),
249 static struct platform_device cmt1_device = {
253 .platform_data = &cmt1_platform_data,
255 .resource = cmt1_resources,
256 .num_resources = ARRAY_SIZE(cmt1_resources),
260 static struct sh_timer_config tmu0_platform_data = {
264 static struct resource tmu0_resources[] = {
265 DEFINE_RES_MEM(0xfff80000, 0x2c),
266 DEFINE_RES_IRQ(gic_spi(198)),
267 DEFINE_RES_IRQ(gic_spi(199)),
268 DEFINE_RES_IRQ(gic_spi(200)),
271 static struct platform_device tmu0_device = {
275 .platform_data = &tmu0_platform_data,
277 .resource = tmu0_resources,
278 .num_resources = ARRAY_SIZE(tmu0_resources),
281 /* IPMMUI (an IPMMU module for ICB/LMB) */
282 static struct resource ipmmu_resources[] = {
287 .flags = IORESOURCE_MEM,
291 static const char * const ipmmu_dev_names[] = {
292 "sh_mobile_lcdc_fb.0",
293 "sh_mobile_lcdc_fb.1",
297 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
298 .dev_names = ipmmu_dev_names,
299 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
302 static struct platform_device ipmmu_device = {
306 .platform_data = &ipmmu_platform_data,
308 .resource = ipmmu_resources,
309 .num_resources = ARRAY_SIZE(ipmmu_resources),
312 static struct platform_device *r8a7740_early_devices[] __initdata = {
332 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
334 .slave_id = SHDMA_SLAVE_SDHI0_TX,
336 .chcr = CHCR_TX(XMIT_SZ_16BIT),
339 .slave_id = SHDMA_SLAVE_SDHI0_RX,
341 .chcr = CHCR_RX(XMIT_SZ_16BIT),
344 .slave_id = SHDMA_SLAVE_SDHI1_TX,
346 .chcr = CHCR_TX(XMIT_SZ_16BIT),
349 .slave_id = SHDMA_SLAVE_SDHI1_RX,
351 .chcr = CHCR_RX(XMIT_SZ_16BIT),
354 .slave_id = SHDMA_SLAVE_SDHI2_TX,
356 .chcr = CHCR_TX(XMIT_SZ_16BIT),
359 .slave_id = SHDMA_SLAVE_SDHI2_RX,
361 .chcr = CHCR_RX(XMIT_SZ_16BIT),
364 .slave_id = SHDMA_SLAVE_FSIA_TX,
366 .chcr = CHCR_TX(XMIT_SZ_32BIT),
369 .slave_id = SHDMA_SLAVE_FSIA_RX,
371 .chcr = CHCR_RX(XMIT_SZ_32BIT),
374 .slave_id = SHDMA_SLAVE_FSIB_TX,
376 .chcr = CHCR_TX(XMIT_SZ_32BIT),
379 .slave_id = SHDMA_SLAVE_MMCIF_TX,
381 .chcr = CHCR_TX(XMIT_SZ_32BIT),
384 .slave_id = SHDMA_SLAVE_MMCIF_RX,
386 .chcr = CHCR_RX(XMIT_SZ_32BIT),
391 #define DMA_CHANNEL(a, b, c) \
396 .chclr_offset = (0x220 - 0x20) + a \
399 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
400 DMA_CHANNEL(0x00, 0, 0),
401 DMA_CHANNEL(0x10, 0, 8),
402 DMA_CHANNEL(0x20, 4, 0),
403 DMA_CHANNEL(0x30, 4, 8),
404 DMA_CHANNEL(0x50, 8, 0),
405 DMA_CHANNEL(0x60, 8, 8),
408 static struct sh_dmae_pdata dma_platform_data = {
409 .slave = r8a7740_dmae_slaves,
410 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
411 .channel = r8a7740_dmae_channels,
412 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
413 .ts_low_shift = TS_LOW_SHIFT,
414 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
415 .ts_high_shift = TS_HI_SHIFT,
416 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
417 .ts_shift = dma_ts_shift,
418 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
419 .dmaor_init = DMAOR_DME,
423 /* Resource order important! */
424 static struct resource r8a7740_dmae0_resources[] = {
426 /* Channel registers and DMAOR */
429 .flags = IORESOURCE_MEM,
435 .flags = IORESOURCE_MEM,
439 .start = gic_spi(34),
441 .flags = IORESOURCE_IRQ,
444 /* IRQ for channels 0-5 */
445 .start = gic_spi(28),
447 .flags = IORESOURCE_IRQ,
451 /* Resource order important! */
452 static struct resource r8a7740_dmae1_resources[] = {
454 /* Channel registers and DMAOR */
457 .flags = IORESOURCE_MEM,
463 .flags = IORESOURCE_MEM,
467 .start = gic_spi(41),
469 .flags = IORESOURCE_IRQ,
472 /* IRQ for channels 0-5 */
473 .start = gic_spi(35),
475 .flags = IORESOURCE_IRQ,
479 /* Resource order important! */
480 static struct resource r8a7740_dmae2_resources[] = {
482 /* Channel registers and DMAOR */
485 .flags = IORESOURCE_MEM,
491 .flags = IORESOURCE_MEM,
495 .start = gic_spi(48),
497 .flags = IORESOURCE_IRQ,
500 /* IRQ for channels 0-5 */
501 .start = gic_spi(42),
503 .flags = IORESOURCE_IRQ,
507 static struct platform_device dma0_device = {
508 .name = "sh-dma-engine",
510 .resource = r8a7740_dmae0_resources,
511 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
513 .platform_data = &dma_platform_data,
517 static struct platform_device dma1_device = {
518 .name = "sh-dma-engine",
520 .resource = r8a7740_dmae1_resources,
521 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
523 .platform_data = &dma_platform_data,
527 static struct platform_device dma2_device = {
528 .name = "sh-dma-engine",
530 .resource = r8a7740_dmae2_resources,
531 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
533 .platform_data = &dma_platform_data,
538 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
546 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
548 .slave_id = SHDMA_SLAVE_USBHS_TX,
549 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
551 .slave_id = SHDMA_SLAVE_USBHS_RX,
552 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
556 static struct sh_dmae_pdata usb_dma_platform_data = {
557 .slave = r8a7740_usb_dma_slaves,
558 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
559 .channel = r8a7740_usb_dma_channels,
560 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
561 .ts_low_shift = USBTS_LOW_SHIFT,
562 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
563 .ts_high_shift = USBTS_HI_SHIFT,
564 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
565 .ts_shift = dma_usbts_shift,
566 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
567 .dmaor_init = DMAOR_DME,
569 .chcr_ie_bit = 1 << 5,
576 static struct resource r8a7740_usb_dma_resources[] = {
578 /* Channel registers and DMAOR */
580 .end = 0xe68a0064 - 1,
581 .flags = IORESOURCE_MEM,
586 .end = 0xe68a0014 - 1,
587 .flags = IORESOURCE_MEM,
590 /* IRQ for channels */
591 .start = gic_spi(49),
593 .flags = IORESOURCE_IRQ,
597 static struct platform_device usb_dma_device = {
598 .name = "sh-dma-engine",
600 .resource = r8a7740_usb_dma_resources,
601 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
603 .platform_data = &usb_dma_platform_data,
608 static struct resource i2c0_resources[] = {
612 .end = 0xfff20425 - 1,
613 .flags = IORESOURCE_MEM,
616 .start = gic_spi(201),
618 .flags = IORESOURCE_IRQ,
622 static struct resource i2c1_resources[] = {
626 .end = 0xe6c20425 - 1,
627 .flags = IORESOURCE_MEM,
630 .start = gic_spi(70), /* IIC1_ALI1 */
631 .end = gic_spi(73), /* IIC1_DTEI1 */
632 .flags = IORESOURCE_IRQ,
636 static struct platform_device i2c0_device = {
637 .name = "i2c-sh_mobile",
639 .resource = i2c0_resources,
640 .num_resources = ARRAY_SIZE(i2c0_resources),
643 static struct platform_device i2c1_device = {
644 .name = "i2c-sh_mobile",
646 .resource = i2c1_resources,
647 .num_resources = ARRAY_SIZE(i2c1_resources),
650 static struct resource pmu_resources[] = {
652 .start = gic_spi(83),
654 .flags = IORESOURCE_IRQ,
658 static struct platform_device pmu_device = {
661 .num_resources = ARRAY_SIZE(pmu_resources),
662 .resource = pmu_resources,
665 static struct platform_device *r8a7740_late_devices[] __initdata = {
676 * r8a7740 chip has lasting errata on MERAM buffer.
677 * this is work-around for it.
679 * "Media RAM (MERAM)" on r8a7740 documentation
681 #define MEBUFCNTR 0xFE950098
682 void __init r8a7740_meram_workaround(void)
686 reg = ioremap_nocache(MEBUFCNTR, 4);
688 iowrite32(0x01600164, reg);
694 #define ICSTART 0x0070
696 #define i2c_read(reg, offset) ioread8(reg + offset)
697 #define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
700 * r8a7740 chip has lasting errata on I2C I/O pad reset.
701 * this is work-around for it.
703 static void r8a7740_i2c_workaround(struct platform_device *pdev)
705 struct resource *res;
708 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
709 if (unlikely(!res)) {
710 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
714 reg = ioremap(res->start, resource_size(res));
715 if (unlikely(!reg)) {
716 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
720 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
721 i2c_read(reg, ICCR); /* dummy read */
723 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
724 i2c_read(reg, ICSTART); /* dummy read */
728 i2c_write(reg, ICCR, 0x01);
729 i2c_write(reg, ICSTART, 0x00);
733 i2c_write(reg, ICCR, 0x10);
735 i2c_write(reg, ICCR, 0x00);
737 i2c_write(reg, ICCR, 0x10);
743 void __init r8a7740_add_standard_devices(void)
745 static struct pm_domain_device domain_devices[] __initdata = {
746 { "A4R", &tmu0_device },
747 { "A4R", &i2c0_device },
748 { "A4S", &irqpin0_device },
749 { "A4S", &irqpin1_device },
750 { "A4S", &irqpin2_device },
751 { "A4S", &irqpin3_device },
752 { "A3SP", &scif0_device },
753 { "A3SP", &scif1_device },
754 { "A3SP", &scif2_device },
755 { "A3SP", &scif3_device },
756 { "A3SP", &scif4_device },
757 { "A3SP", &scif5_device },
758 { "A3SP", &scif6_device },
759 { "A3SP", &scif7_device },
760 { "A3SP", &scif8_device },
761 { "A3SP", &i2c1_device },
762 { "A3SP", &ipmmu_device },
763 { "A3SP", &dma0_device },
764 { "A3SP", &dma1_device },
765 { "A3SP", &dma2_device },
766 { "A3SP", &usb_dma_device },
769 /* I2C work-around */
770 r8a7740_i2c_workaround(&i2c0_device);
771 r8a7740_i2c_workaround(&i2c1_device);
773 r8a7740_init_pm_domains();
776 platform_add_devices(r8a7740_early_devices,
777 ARRAY_SIZE(r8a7740_early_devices));
778 platform_add_devices(r8a7740_late_devices,
779 ARRAY_SIZE(r8a7740_late_devices));
781 /* add devices to PM domain */
782 rmobile_add_devices_to_domains(domain_devices,
783 ARRAY_SIZE(domain_devices));
786 void __init r8a7740_add_early_devices(void)
788 early_platform_add_devices(r8a7740_early_devices,
789 ARRAY_SIZE(r8a7740_early_devices));
791 /* setup early console here as well */
792 shmobile_setup_console();
797 void __init r8a7740_init_irq_of(void)
799 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
800 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
801 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
803 #ifdef CONFIG_ARCH_SHMOBILE_LEGACY
804 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
805 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
807 gic_init(0, 29, gic_dist_base, gic_cpu_base);
812 /* route signals to GIC */
813 iowrite32(0x0, pfc_inta_ctrl);
816 * To mask the shared interrupt to SPI 149 we must ensure to set
817 * PRIO *and* MASK. Else we run into IRQ floods when registering
818 * the intc_irqpin devices
820 iowrite32(0x0, intc_prio_base + 0x0);
821 iowrite32(0x0, intc_prio_base + 0x4);
822 iowrite32(0x0, intc_prio_base + 0x8);
823 iowrite32(0x0, intc_prio_base + 0xc);
824 iowrite8(0xff, intc_msk_base + 0x0);
825 iowrite8(0xff, intc_msk_base + 0x4);
826 iowrite8(0xff, intc_msk_base + 0x8);
827 iowrite8(0xff, intc_msk_base + 0xc);
829 iounmap(intc_prio_base);
830 iounmap(intc_msk_base);
831 iounmap(pfc_inta_ctrl);
834 static void __init r8a7740_generic_init(void)
836 r8a7740_meram_workaround();
838 #ifdef CONFIG_CACHE_L2X0
839 /* Shared attribute override enable, 32K*8way */
840 l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
842 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
845 #define RESCNT2 IOMEM(0xe6188020)
846 static void r8a7740_restart(enum reboot_mode mode, const char *cmd)
848 /* Do soft power on reset */
849 writel(1 << 31, RESCNT2);
852 static const char *r8a7740_boards_compat_dt[] __initdata = {
857 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
858 .map_io = r8a7740_map_io,
859 .init_early = shmobile_init_delay,
860 .init_irq = r8a7740_init_irq_of,
861 .init_machine = r8a7740_generic_init,
862 .init_late = shmobile_init_late,
863 .dt_compat = r8a7740_boards_compat_dt,
864 .restart = r8a7740_restart,
867 #endif /* CONFIG_USE_OF */