2 * sh73a0 clock framework support
4 * Copyright (C) 2010 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/init.h>
20 #include <linux/kernel.h>
22 #include <linux/sh_clk.h>
23 #include <mach/common.h>
24 #include <asm/clkdev.h>
26 #define SMSTPCR0 0xe6150130
27 #define SMSTPCR1 0xe6150134
28 #define SMSTPCR2 0xe6150138
29 #define SMSTPCR3 0xe615013c
30 #define SMSTPCR4 0xe6150140
31 #define SMSTPCR5 0xe6150144
33 /* Fixed 32 KHz root clock from EXTALR pin */
34 static struct clk r_clk = {
38 /* Temporarily fixed 48 MHz SUB clock */
39 static struct clk sub_clk = {
43 /* Temporarily fixed 104 MHz HP clock */
44 static struct clk hp_clk = {
48 static struct clk *main_clks[] = {
56 MSTP219, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
57 MSTP331, MSTP329, MSTP323,
58 MSTP411, MSTP410, MSTP403,
61 #define MSTP(_parent, _reg, _bit, _flags) \
62 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
64 static struct clk mstp_clks[MSTP_NR] = {
65 [MSTP001] = MSTP(&hp_clk, SMSTPCR0, 1, 0), /* I2C2 */
66 [MSTP116] = MSTP(&hp_clk, SMSTPCR1, 16, 0), /* I2C0 */
67 [MSTP219] = MSTP(&sub_clk, SMSTPCR2, 19, 0), /* SCIFA7 */
68 [MSTP207] = MSTP(&sub_clk, SMSTPCR2, 7, 0), /* SCIFA5 */
69 [MSTP206] = MSTP(&sub_clk, SMSTPCR2, 6, 0), /* SCIFB */
70 [MSTP204] = MSTP(&sub_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
71 [MSTP203] = MSTP(&sub_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
72 [MSTP202] = MSTP(&sub_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
73 [MSTP201] = MSTP(&sub_clk, SMSTPCR2, 1, 0), /* SCIFA3 */
74 [MSTP200] = MSTP(&sub_clk, SMSTPCR2, 0, 0), /* SCIFA4 */
75 [MSTP331] = MSTP(&sub_clk, SMSTPCR3, 31, 0), /* SCIFA6 */
76 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
77 [MSTP323] = MSTP(&hp_clk, SMSTPCR3, 23, 0), /* I2C1 */
78 [MSTP411] = MSTP(&hp_clk, SMSTPCR4, 11, 0), /* I2C3 */
79 [MSTP410] = MSTP(&hp_clk, SMSTPCR4, 10, 0), /* I2C4 */
80 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* KEYSC0 */
83 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
85 static struct clk_lookup lookups[] = {
87 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
88 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
89 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
90 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
91 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
92 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
93 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
94 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
95 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
96 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
97 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
98 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
99 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
100 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
101 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
102 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC0 */
105 void __init sh73a0_clock_init(void)
109 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
110 ret = clk_register(main_clks[k]);
113 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
115 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
120 panic("failed to setup sh73a0 clocks\n");