1 // SPDX-License-Identifier: GPL-2.0
3 * linux/arch/arm/mach-sa1100/neponset.c
6 #include <linux/gpio/driver.h>
7 #include <linux/gpio/gpio-reg.h>
8 #include <linux/gpio/machine.h>
9 #include <linux/init.h>
10 #include <linux/ioport.h>
11 #include <linux/irq.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/sa11x0-serial.h>
15 #include <linux/platform_device.h>
17 #include <linux/serial_core.h>
18 #include <linux/slab.h>
19 #include <linux/smc91x.h>
21 #include <asm/mach-types.h>
22 #include <asm/mach/map.h>
23 #include <asm/hardware/sa1111.h>
24 #include <asm/sizes.h>
26 #include <mach/hardware.h>
27 #include <mach/assabet.h>
28 #include <mach/neponset.h>
29 #include <mach/irqs.h>
31 #define NEP_IRQ_SMC91X 0
32 #define NEP_IRQ_USAR 1
33 #define NEP_IRQ_SA1111 2
43 #define MDM_CTL_0 0xb0
44 #define MDM_CTL_1 0xb4
47 #define IRR_ETHERNET (1 << 0)
48 #define IRR_USAR (1 << 1)
49 #define IRR_SA1111 (1 << 2)
53 #define MDM_CTL0_RTS1 (1 << 0)
54 #define MDM_CTL0_DTR1 (1 << 1)
55 #define MDM_CTL0_RTS2 (1 << 2)
56 #define MDM_CTL0_DTR2 (1 << 3)
57 #define MDM_CTL0_NGPIO 4
59 #define MDM_CTL1_CTS1 (1 << 0)
60 #define MDM_CTL1_DSR1 (1 << 1)
61 #define MDM_CTL1_DCD1 (1 << 2)
62 #define MDM_CTL1_CTS2 (1 << 3)
63 #define MDM_CTL1_DSR2 (1 << 4)
64 #define MDM_CTL1_DCD2 (1 << 5)
65 #define MDM_CTL1_NGPIO 6
67 #define AUD_SEL_1341 (1 << 0)
68 #define AUD_MUTE_1341 (1 << 1)
71 extern void sa1110_mb_disable(void);
73 #define to_neponset_gpio_chip(x) container_of(x, struct neponset_gpio_chip, gc)
75 static const char *neponset_ncr_names[] = {
76 "gp01_off", "tp_power", "ms_power", "enet_osc",
77 "spi_kb_wk_up", "a0vpp", "a1vpp"
80 static const char *neponset_mdmctl0_names[] = {
81 "rts3", "dtr3", "rts1", "dtr1",
84 static const char *neponset_mdmctl1_names[] = {
85 "cts3", "dsr3", "dcd3", "cts1", "dsr1", "dcd1"
88 static const char *neponset_aud_names[] = {
89 "sel_1341", "mute_1341",
92 struct neponset_drvdata {
94 struct platform_device *sa1111;
95 struct platform_device *smc91x;
97 struct gpio_chip *gpio[4];
100 static struct gpiod_lookup_table neponset_pcmcia_table = {
103 GPIO_LOOKUP("sa1111", 1, "a0vcc", GPIO_ACTIVE_HIGH),
104 GPIO_LOOKUP("sa1111", 0, "a1vcc", GPIO_ACTIVE_HIGH),
105 GPIO_LOOKUP("neponset-ncr", 5, "a0vpp", GPIO_ACTIVE_HIGH),
106 GPIO_LOOKUP("neponset-ncr", 6, "a1vpp", GPIO_ACTIVE_HIGH),
107 GPIO_LOOKUP("sa1111", 2, "b0vcc", GPIO_ACTIVE_HIGH),
108 GPIO_LOOKUP("sa1111", 3, "b1vcc", GPIO_ACTIVE_HIGH),
113 static struct neponset_drvdata *nep;
115 void neponset_ncr_frob(unsigned int mask, unsigned int val)
117 struct neponset_drvdata *n = nep;
118 unsigned long m = mask, v = val;
121 n->gpio[0]->set_multiple(n->gpio[0], &m, &v);
123 WARN(1, "nep unset\n");
125 EXPORT_SYMBOL(neponset_ncr_frob);
127 static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
129 struct neponset_drvdata *n = nep;
130 unsigned long mask, val = 0;
135 if (port->mapbase == _Ser1UTCR0) {
136 mask = MDM_CTL0_RTS2 | MDM_CTL0_DTR2;
138 if (!(mctrl & TIOCM_RTS))
139 val |= MDM_CTL0_RTS2;
141 if (!(mctrl & TIOCM_DTR))
142 val |= MDM_CTL0_DTR2;
143 } else if (port->mapbase == _Ser3UTCR0) {
144 mask = MDM_CTL0_RTS1 | MDM_CTL0_DTR1;
146 if (!(mctrl & TIOCM_RTS))
147 val |= MDM_CTL0_RTS1;
149 if (!(mctrl & TIOCM_DTR))
150 val |= MDM_CTL0_DTR1;
153 n->gpio[1]->set_multiple(n->gpio[1], &mask, &val);
156 static u_int neponset_get_mctrl(struct uart_port *port)
158 void __iomem *base = nep->base;
159 u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
165 mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
166 if (port->mapbase == _Ser1UTCR0) {
167 if (mdm_ctl1 & MDM_CTL1_DCD2)
169 if (mdm_ctl1 & MDM_CTL1_CTS2)
171 if (mdm_ctl1 & MDM_CTL1_DSR2)
173 } else if (port->mapbase == _Ser3UTCR0) {
174 if (mdm_ctl1 & MDM_CTL1_DCD1)
176 if (mdm_ctl1 & MDM_CTL1_CTS1)
178 if (mdm_ctl1 & MDM_CTL1_DSR1)
185 static struct sa1100_port_fns neponset_port_fns = {
186 .set_mctrl = neponset_set_mctrl,
187 .get_mctrl = neponset_get_mctrl,
191 * Install handler for Neponset IRQ. Note that we have to loop here
192 * since the ETHERNET and USAR IRQs are level based, and we need to
193 * ensure that the IRQ signal is deasserted before returning. This
194 * is rather unfortunate.
196 static void neponset_irq_handler(struct irq_desc *desc)
198 struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
203 * Acknowledge the parent IRQ.
205 desc->irq_data.chip->irq_ack(&desc->irq_data);
208 * Read the interrupt reason register. Let's have all
209 * active IRQ bits high. Note: there is a typo in the
210 * Neponset user's guide for the SA1111 IRR level.
212 irr = readb_relaxed(d->base + IRR);
213 irr ^= IRR_ETHERNET | IRR_USAR;
215 if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
219 * Since there is no individual mask, we have to
220 * mask the parent IRQ. This is safe, since we'll
221 * recheck the register for any pending IRQs.
223 if (irr & (IRR_ETHERNET | IRR_USAR)) {
224 desc->irq_data.chip->irq_mask(&desc->irq_data);
227 * Ack the interrupt now to prevent re-entering
228 * this neponset handler. Again, this is safe
229 * since we'll check the IRR register prior to
232 desc->irq_data.chip->irq_ack(&desc->irq_data);
234 if (irr & IRR_ETHERNET)
235 generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
238 generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
240 desc->irq_data.chip->irq_unmask(&desc->irq_data);
243 if (irr & IRR_SA1111)
244 generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
248 /* Yes, we really do not have any kind of masking or unmasking */
249 static void nochip_noop(struct irq_data *irq)
253 static struct irq_chip nochip = {
255 .irq_ack = nochip_noop,
256 .irq_mask = nochip_noop,
257 .irq_unmask = nochip_noop,
260 static int neponset_init_gpio(struct gpio_chip **gcp,
261 struct device *dev, const char *label, void __iomem *reg,
262 unsigned num, bool in, const char *const * names)
264 struct gpio_chip *gc;
266 gc = gpio_reg_init(dev, reg, -1, num, label, in ? 0xffffffff : 0,
267 readl_relaxed(reg), names, NULL, NULL);
276 static struct sa1111_platform_data sa1111_info = {
277 .disable_devs = SA1111_DEVID_PS2_MSE,
280 static int neponset_probe(struct platform_device *dev)
282 struct neponset_drvdata *d;
283 struct resource *nep_res, *sa1111_res, *smc91x_res;
284 struct resource sa1111_resources[] = {
285 DEFINE_RES_MEM(0x40000000, SZ_8K),
286 { .flags = IORESOURCE_IRQ },
288 struct platform_device_info sa1111_devinfo = {
292 .res = sa1111_resources,
293 .num_res = ARRAY_SIZE(sa1111_resources),
294 .data = &sa1111_info,
295 .size_data = sizeof(sa1111_info),
296 .dma_mask = 0xffffffffUL,
298 struct resource smc91x_resources[] = {
299 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
300 0x02000000, "smc91x-regs"),
301 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
302 0x02000000, "smc91x-attrib"),
303 { .flags = IORESOURCE_IRQ },
305 struct smc91x_platdata smc91x_platdata = {
306 .flags = SMC91X_USE_8BIT | SMC91X_IO_SHIFT_2 | SMC91X_NOWAIT,
308 struct platform_device_info smc91x_devinfo = {
312 .res = smc91x_resources,
313 .num_res = ARRAY_SIZE(smc91x_resources),
314 .data = &smc91x_platdata,
315 .size_data = sizeof(smc91x_platdata),
322 irq = ret = platform_get_irq(dev, 0);
326 nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
327 smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
328 sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
329 if (!nep_res || !smc91x_res || !sa1111_res) {
334 d = kzalloc(sizeof(*d), GFP_KERNEL);
340 d->base = ioremap(nep_res->start, SZ_4K);
346 if (readb_relaxed(d->base + WHOAMI) != 0x11) {
347 dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
348 readb_relaxed(d->base + WHOAMI));
353 ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
355 dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
364 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
366 irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST | IRQ_NOPROBE);
367 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
369 irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST | IRQ_NOPROBE);
370 irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
372 irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
373 irq_set_chained_handler_and_data(irq, neponset_irq_handler, d);
375 /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
376 writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
378 neponset_init_gpio(&d->gpio[0], &dev->dev, "neponset-ncr",
379 d->base + NCR_0, NCR_NGPIO, false,
381 neponset_init_gpio(&d->gpio[1], &dev->dev, "neponset-mdm-ctl0",
382 d->base + MDM_CTL_0, MDM_CTL0_NGPIO, false,
383 neponset_mdmctl0_names);
384 neponset_init_gpio(&d->gpio[2], &dev->dev, "neponset-mdm-ctl1",
385 d->base + MDM_CTL_1, MDM_CTL1_NGPIO, true,
386 neponset_mdmctl1_names);
387 neponset_init_gpio(&d->gpio[3], &dev->dev, "neponset-aud-ctl",
388 d->base + AUD_CTL, AUD_NGPIO, false,
391 gpiod_add_lookup_table(&neponset_pcmcia_table);
394 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
395 * something on the Neponset activates this IRQ on sleep (eth?)
398 enable_irq_wake(irq);
401 dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
402 d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
405 sa1100_register_uart_fns(&neponset_port_fns);
407 /* Ensure that the memory bus request/grant signals are setup */
410 sa1111_resources[0].parent = sa1111_res;
411 sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
412 sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
413 d->sa1111 = platform_device_register_full(&sa1111_devinfo);
415 smc91x_resources[0].parent = smc91x_res;
416 smc91x_resources[1].parent = smc91x_res;
417 smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
418 smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
419 d->smc91x = platform_device_register_full(&smc91x_devinfo);
421 platform_set_drvdata(dev, d);
434 static int neponset_remove(struct platform_device *dev)
436 struct neponset_drvdata *d = platform_get_drvdata(dev);
437 int irq = platform_get_irq(dev, 0);
439 if (!IS_ERR(d->sa1111))
440 platform_device_unregister(d->sa1111);
441 if (!IS_ERR(d->smc91x))
442 platform_device_unregister(d->smc91x);
444 gpiod_remove_lookup_table(&neponset_pcmcia_table);
446 irq_set_chained_handler(irq, NULL);
447 irq_free_descs(d->irq_base, NEP_IRQ_NR);
455 #ifdef CONFIG_PM_SLEEP
456 static int neponset_resume(struct device *dev)
458 struct neponset_drvdata *d = dev_get_drvdata(dev);
461 for (i = 0; i < ARRAY_SIZE(d->gpio); i++) {
462 ret = gpio_reg_resume(d->gpio[i]);
470 static const struct dev_pm_ops neponset_pm_ops = {
471 .resume_noirq = neponset_resume,
472 .restore_noirq = neponset_resume,
474 #define PM_OPS &neponset_pm_ops
479 static struct platform_driver neponset_device_driver = {
480 .probe = neponset_probe,
481 .remove = neponset_remove,
488 static int __init neponset_init(void)
490 return platform_driver_register(&neponset_device_driver);
493 subsys_initcall(neponset_init);