2 * Support for the Arcom ZEUS.
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
6 * Loosely based on Arcom's 2.6.16.28.
7 * Maintained by Marc Zyngier <maz@misterjones.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/cpufreq.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
18 #include <linux/gpio.h>
19 #include <linux/serial_8250.h>
20 #include <linux/dm9000.h>
21 #include <linux/mmc/host.h>
22 #include <linux/spi/spi.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/mtd/physmap.h>
26 #include <linux/i2c.h>
27 #include <linux/i2c/pca953x.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
35 #include <mach/pxa2xx-regs.h>
36 #include <mach/regs-uart.h>
37 #include <mach/ohci.h>
39 #include <mach/pxa27x-udc.h>
41 #include <mach/pxafb.h>
42 #include <mach/pxa2xx_spi.h>
43 #include <mach/mfp-pxa27x.h>
45 #include <mach/audio.h>
46 #include <mach/arcom-pcmcia.h>
47 #include <mach/zeus.h>
55 static unsigned long zeus_irq_enabled_mask;
56 static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
57 static const int zeus_isa_irq_map[] = {
58 0, /* ISA irq #0, invalid */
59 0, /* ISA irq #1, invalid */
60 0, /* ISA irq #2, invalid */
61 1 << 0, /* ISA irq #3 */
62 1 << 1, /* ISA irq #4 */
63 1 << 2, /* ISA irq #5 */
64 1 << 3, /* ISA irq #6 */
65 1 << 4, /* ISA irq #7 */
66 0, /* ISA irq #8, invalid */
67 0, /* ISA irq #9, invalid */
68 1 << 5, /* ISA irq #10 */
69 1 << 6, /* ISA irq #11 */
70 1 << 7, /* ISA irq #12 */
73 static inline int zeus_irq_to_bitmask(unsigned int irq)
75 return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
78 static inline int zeus_bit_to_irq(int bit)
80 return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
83 static void zeus_ack_irq(unsigned int irq)
85 __raw_writew(zeus_irq_to_bitmask(irq), ZEUS_CPLD_ISA_IRQ);
88 static void zeus_mask_irq(unsigned int irq)
90 zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(irq));
93 static void zeus_unmask_irq(unsigned int irq)
95 zeus_irq_enabled_mask |= zeus_irq_to_bitmask(irq);
98 static inline unsigned long zeus_irq_pending(void)
100 return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
103 static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
105 unsigned long pending;
107 pending = zeus_irq_pending();
109 /* we're in a chained irq handler,
110 * so ack the interrupt by hand */
111 desc->chip->ack(gpio_to_irq(ZEUS_ISA_GPIO));
113 if (likely(pending)) {
114 irq = zeus_bit_to_irq(__ffs(pending));
115 generic_handle_irq(irq);
117 pending = zeus_irq_pending();
121 static struct irq_chip zeus_irq_chip = {
124 .mask = zeus_mask_irq,
125 .unmask = zeus_unmask_irq,
128 static void __init zeus_init_irq(void)
135 /* Peripheral IRQs. It would be nice to move those inside driver
136 configuration, but it is not supported at the moment. */
137 set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
138 set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
139 set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
140 set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING);
141 set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
144 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
145 isa_irq = zeus_bit_to_irq(level);
146 set_irq_chip(isa_irq, &zeus_irq_chip);
147 set_irq_handler(isa_irq, handle_edge_irq);
148 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
151 set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
152 set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
161 static struct resource zeus_mtd_resources[] = {
162 [0] = { /* NOR Flash (up to 64MB) */
163 .start = ZEUS_FLASH_PHYS,
164 .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
165 .flags = IORESOURCE_MEM,
168 .start = ZEUS_SRAM_PHYS,
169 .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
170 .flags = IORESOURCE_MEM,
174 static struct physmap_flash_data zeus_flash_data[] = {
182 static struct platform_device zeus_mtd_devices[] = {
184 .name = "physmap-flash",
187 .platform_data = &zeus_flash_data[0],
189 .resource = &zeus_mtd_resources[0],
195 static struct resource zeus_serial_resources[] = {
199 .flags = IORESOURCE_MEM,
204 .flags = IORESOURCE_MEM,
209 .flags = IORESOURCE_MEM,
214 .flags = IORESOURCE_MEM,
219 .flags = IORESOURCE_MEM,
224 .flags = IORESOURCE_MEM,
228 static struct plat_serial8250_port serial_platform_data[] = {
230 /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
232 .mapbase = 0x10000000,
233 .irq = gpio_to_irq(ZEUS_UARTA_GPIO),
234 .irqflags = IRQF_TRIGGER_RISING,
237 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
241 .mapbase = 0x10800000,
242 .irq = gpio_to_irq(ZEUS_UARTB_GPIO),
243 .irqflags = IRQF_TRIGGER_RISING,
246 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
250 .mapbase = 0x11000000,
251 .irq = gpio_to_irq(ZEUS_UARTC_GPIO),
252 .irqflags = IRQF_TRIGGER_RISING,
255 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
259 .mapbase = 0x11800000,
260 .irq = gpio_to_irq(ZEUS_UARTD_GPIO),
261 .irqflags = IRQF_TRIGGER_RISING,
264 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
269 .membase = (void *)&FFUART,
270 .mapbase = __PREG(FFUART),
272 .uartclk = 921600 * 16,
274 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
278 .membase = (void *)&BTUART,
279 .mapbase = __PREG(BTUART),
281 .uartclk = 921600 * 16,
283 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
287 .membase = (void *)&STUART,
288 .mapbase = __PREG(STUART),
290 .uartclk = 921600 * 16,
292 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
298 static struct platform_device zeus_serial_device = {
299 .name = "serial8250",
300 .id = PLAT8250_DEV_PLATFORM,
302 .platform_data = serial_platform_data,
304 .num_resources = ARRAY_SIZE(zeus_serial_resources),
305 .resource = zeus_serial_resources,
309 static struct resource zeus_dm9k0_resource[] = {
311 .start = ZEUS_ETH0_PHYS,
312 .end = ZEUS_ETH0_PHYS + 1,
313 .flags = IORESOURCE_MEM
316 .start = ZEUS_ETH0_PHYS + 2,
317 .end = ZEUS_ETH0_PHYS + 3,
318 .flags = IORESOURCE_MEM
321 .start = gpio_to_irq(ZEUS_ETH0_GPIO),
322 .end = gpio_to_irq(ZEUS_ETH0_GPIO),
323 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
327 static struct resource zeus_dm9k1_resource[] = {
329 .start = ZEUS_ETH1_PHYS,
330 .end = ZEUS_ETH1_PHYS + 1,
331 .flags = IORESOURCE_MEM
334 .start = ZEUS_ETH1_PHYS + 2,
335 .end = ZEUS_ETH1_PHYS + 3,
336 .flags = IORESOURCE_MEM,
339 .start = gpio_to_irq(ZEUS_ETH1_GPIO),
340 .end = gpio_to_irq(ZEUS_ETH1_GPIO),
341 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
345 static struct dm9000_plat_data zeus_dm9k_platdata = {
346 .flags = DM9000_PLATF_16BITONLY,
349 static struct platform_device zeus_dm9k0_device = {
352 .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
353 .resource = zeus_dm9k0_resource,
355 .platform_data = &zeus_dm9k_platdata,
359 static struct platform_device zeus_dm9k1_device = {
362 .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
363 .resource = zeus_dm9k1_resource,
365 .platform_data = &zeus_dm9k_platdata,
370 static struct resource zeus_sram_resource = {
371 .start = ZEUS_SRAM_PHYS,
372 .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
373 .flags = IORESOURCE_MEM,
376 static struct platform_device zeus_sram_device = {
377 .name = "pxa2xx-8bit-sram",
380 .resource = &zeus_sram_resource,
383 /* SPI interface on SSP3 */
384 static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
389 static struct platform_device pxa2xx_spi_ssp3_device = {
390 .name = "pxa2xx-spi",
393 .platform_data = &pxa2xx_spi_ssp3_master_info,
398 static struct gpio_led zeus_leds[] = {
400 .name = "zeus:yellow:1",
401 .default_trigger = "heartbeat",
402 .gpio = ZEUS_EXT0_GPIO(3),
406 .name = "zeus:yellow:2",
407 .default_trigger = "default-on",
408 .gpio = ZEUS_EXT0_GPIO(4),
412 .name = "zeus:yellow:3",
413 .default_trigger = "default-on",
414 .gpio = ZEUS_EXT0_GPIO(5),
419 static struct gpio_led_platform_data zeus_leds_info = {
421 .num_leds = ARRAY_SIZE(zeus_leds),
424 static struct platform_device zeus_leds_device = {
428 .platform_data = &zeus_leds_info,
432 static void zeus_cf_reset(int state)
434 u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
437 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
439 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
441 __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
444 static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
445 .cd_gpio = ZEUS_CF_CD_GPIO,
446 .rdy_gpio = ZEUS_CF_RDY_GPIO,
447 .pwr_gpio = ZEUS_CF_PWEN_GPIO,
448 .reset = zeus_cf_reset,
451 static struct platform_device zeus_pcmcia_device = {
452 .name = "zeus-pcmcia",
455 .platform_data = &zeus_pcmcia_info,
459 static struct platform_device *zeus_devices[] __initdata = {
461 &zeus_mtd_devices[0],
465 &pxa2xx_spi_ssp3_device,
471 static pxa2xx_audio_ops_t zeus_ac97_info = {
480 static int zeus_ohci_init(struct device *dev)
484 /* Switch on port 2. */
485 if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) {
486 dev_err(dev, "Can't request USB2_PWREN\n");
490 if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) {
491 gpio_free(ZEUS_USB2_PWREN_GPIO);
492 dev_err(dev, "Can't enable USB2_PWREN\n");
496 /* Port 2 is shared between host and client interface. */
497 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
502 static void zeus_ohci_exit(struct device *dev)
504 /* Power-off port 2 */
505 gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0);
506 gpio_free(ZEUS_USB2_PWREN_GPIO);
509 static struct pxaohci_platform_data zeus_ohci_platform_data = {
510 .port_mode = PMM_NPS_MODE,
511 .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
512 .init = zeus_ohci_init,
513 .exit = zeus_ohci_exit,
520 static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
522 gpio_set_value(ZEUS_LCD_EN_GPIO, on);
525 static void zeus_backlight_power(int on)
527 gpio_set_value(ZEUS_BKLEN_GPIO, on);
530 static int zeus_setup_fb_gpios(void)
534 if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
537 if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
540 if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
543 if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
549 gpio_free(ZEUS_BKLEN_GPIO);
551 gpio_free(ZEUS_LCD_EN_GPIO);
556 static struct pxafb_mode_info zeus_fb_mode_info[] = {
577 static struct pxafb_mach_info zeus_fb_info = {
578 .modes = zeus_fb_mode_info,
580 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
581 .pxafb_lcd_power = zeus_lcd_power,
582 .pxafb_backlight_power = zeus_backlight_power,
588 * The card detect interrupt isn't debounced so we delay it by 250ms
589 * to give the card a chance to fully insert/eject.
592 static struct pxamci_platform_data zeus_mci_platform_data = {
593 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
594 .detect_delay = HZ/4,
595 .gpio_card_detect = ZEUS_MMC_CD_GPIO,
596 .gpio_card_ro = ZEUS_MMC_WP_GPIO,
597 .gpio_card_ro_invert = 1,
602 * USB Device Controller
604 static void zeus_udc_command(int cmd)
607 case PXA2XX_UDC_CMD_DISCONNECT:
608 pr_info("zeus: disconnecting USB client\n");
609 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
612 case PXA2XX_UDC_CMD_CONNECT:
613 pr_info("zeus: connecting USB client\n");
614 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
619 static struct pxa2xx_udc_mach_info zeus_udc_info = {
620 .udc_command = zeus_udc_command,
623 static void zeus_power_off(void)
626 pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP);
629 int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
630 unsigned ngpio, void *context)
635 for (i = 0; i < 8; i++) {
636 int pcb_bit = gpio + i + 8;
638 if (gpio_request(pcb_bit, "pcb info")) {
639 dev_err(&client->dev, "Can't request pcb info %d\n", i);
643 if (gpio_direction_input(pcb_bit)) {
644 dev_err(&client->dev, "Can't read pcb info %d\n", i);
649 pcb_info |= !!gpio_get_value(pcb_bit) << i;
654 dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
655 pcb_info >> 4, pcb_info & 0xf);
660 static struct pca953x_platform_data zeus_pca953x_pdata[] = {
661 [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, },
663 .gpio_base = ZEUS_EXT1_GPIO_BASE,
664 .setup = zeus_get_pcb_info,
666 [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
669 static struct i2c_board_info __initdata zeus_i2c_devices[] = {
671 I2C_BOARD_INFO("pca9535", 0x21),
672 .platform_data = &zeus_pca953x_pdata[0],
675 I2C_BOARD_INFO("pca9535", 0x22),
676 .platform_data = &zeus_pca953x_pdata[1],
679 I2C_BOARD_INFO("pca9535", 0x20),
680 .platform_data = &zeus_pca953x_pdata[2],
681 .irq = gpio_to_irq(ZEUS_EXTGPIO_GPIO),
683 { I2C_BOARD_INFO("lm75a", 0x48) },
684 { I2C_BOARD_INFO("24c01", 0x50) },
685 { I2C_BOARD_INFO("isl1208", 0x6f) },
688 static mfp_cfg_t zeus_pin_config[] __initdata = {
724 GPIO36_GPIO, /* CF CD */
725 GPIO97_GPIO, /* CF PWREN */
726 GPIO99_GPIO, /* CF RDY */
729 static void __init zeus_init(void)
731 u16 dm9000_msc = 0xe279;
733 system_rev = __raw_readw(ZEUS_CPLD_VERSION);
734 pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
736 /* Fix timings for dm9000s (CS1/CS2)*/
737 MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16);
738 MSC1 = (MSC1 & 0xffff0000) | dm9000_msc;
740 pm_power_off = zeus_power_off;
742 pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
744 platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
746 pxa_set_ohci_info(&zeus_ohci_platform_data);
748 if (zeus_setup_fb_gpios())
749 pr_err("Failed to setup fb gpios\n");
751 set_pxa_fb_info(&zeus_fb_info);
753 pxa_set_mci_info(&zeus_mci_platform_data);
754 pxa_set_udc_info(&zeus_udc_info);
755 pxa_set_ac97_info(&zeus_ac97_info);
756 pxa_set_i2c_info(NULL);
757 i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
760 static struct map_desc zeus_io_desc[] __initdata = {
762 .virtual = ZEUS_CPLD_VERSION,
763 .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
768 .virtual = ZEUS_CPLD_ISA_IRQ,
769 .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
774 .virtual = ZEUS_CPLD_CONTROL,
775 .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
780 .virtual = ZEUS_CPLD_EXTWDOG,
781 .pfn = __phys_to_pfn(ZEUS_CPLD_EXTWDOG_PHYS),
786 .virtual = ZEUS_PC104IO,
787 .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
788 .length = 0x00800000,
793 static void __init zeus_map_io(void)
797 iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
799 /* Clear PSPR to ensure a full restart on wake-up. */
802 /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
805 /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
806 * float chip selects and PCMCIA */
807 PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
810 MACHINE_START(ARCOM_ZEUS, "Arcom ZEUS")
811 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
812 .phys_io = 0x40000000,
813 .io_pg_offst = ((io_p2v(0x40000000) >> 18) & 0xfffc),
814 .boot_params = 0xa0000100,
815 .map_io = zeus_map_io,
816 .init_irq = zeus_init_irq,
818 .init_machine = zeus_init,