2 * Support for the Arcom ZEUS.
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
6 * Loosely based on Arcom's 2.6.16.28.
7 * Maintained by Marc Zyngier <maz@misterjones.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/cpufreq.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
18 #include <linux/gpio.h>
19 #include <linux/serial_8250.h>
20 #include <linux/dm9000.h>
21 #include <linux/mmc/host.h>
22 #include <linux/spi/spi.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/mtd/physmap.h>
26 #include <linux/i2c.h>
27 #include <linux/i2c/pca953x.h>
28 #include <linux/apm-emulation.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/map.h>
36 #include <mach/pxa2xx-regs.h>
37 #include <mach/regs-uart.h>
38 #include <mach/ohci.h>
40 #include <mach/pxa27x-udc.h>
42 #include <mach/pxafb.h>
43 #include <mach/pxa2xx_spi.h>
44 #include <mach/mfp-pxa27x.h>
46 #include <mach/audio.h>
47 #include <mach/arcom-pcmcia.h>
48 #include <mach/zeus.h>
56 static unsigned long zeus_irq_enabled_mask;
57 static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
58 static const int zeus_isa_irq_map[] = {
59 0, /* ISA irq #0, invalid */
60 0, /* ISA irq #1, invalid */
61 0, /* ISA irq #2, invalid */
62 1 << 0, /* ISA irq #3 */
63 1 << 1, /* ISA irq #4 */
64 1 << 2, /* ISA irq #5 */
65 1 << 3, /* ISA irq #6 */
66 1 << 4, /* ISA irq #7 */
67 0, /* ISA irq #8, invalid */
68 0, /* ISA irq #9, invalid */
69 1 << 5, /* ISA irq #10 */
70 1 << 6, /* ISA irq #11 */
71 1 << 7, /* ISA irq #12 */
74 static inline int zeus_irq_to_bitmask(unsigned int irq)
76 return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
79 static inline int zeus_bit_to_irq(int bit)
81 return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
84 static void zeus_ack_irq(unsigned int irq)
86 __raw_writew(zeus_irq_to_bitmask(irq), ZEUS_CPLD_ISA_IRQ);
89 static void zeus_mask_irq(unsigned int irq)
91 zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(irq));
94 static void zeus_unmask_irq(unsigned int irq)
96 zeus_irq_enabled_mask |= zeus_irq_to_bitmask(irq);
99 static inline unsigned long zeus_irq_pending(void)
101 return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
104 static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
106 unsigned long pending;
108 pending = zeus_irq_pending();
110 /* we're in a chained irq handler,
111 * so ack the interrupt by hand */
112 desc->chip->ack(gpio_to_irq(ZEUS_ISA_GPIO));
114 if (likely(pending)) {
115 irq = zeus_bit_to_irq(__ffs(pending));
116 generic_handle_irq(irq);
118 pending = zeus_irq_pending();
122 static struct irq_chip zeus_irq_chip = {
125 .mask = zeus_mask_irq,
126 .unmask = zeus_unmask_irq,
129 static void __init zeus_init_irq(void)
136 /* Peripheral IRQs. It would be nice to move those inside driver
137 configuration, but it is not supported at the moment. */
138 set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
139 set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
140 set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
141 set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING);
142 set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
145 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
146 isa_irq = zeus_bit_to_irq(level);
147 set_irq_chip(isa_irq, &zeus_irq_chip);
148 set_irq_handler(isa_irq, handle_edge_irq);
149 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
152 set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
153 set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
162 static struct resource zeus_mtd_resources[] = {
163 [0] = { /* NOR Flash (up to 64MB) */
164 .start = ZEUS_FLASH_PHYS,
165 .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
166 .flags = IORESOURCE_MEM,
169 .start = ZEUS_SRAM_PHYS,
170 .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
171 .flags = IORESOURCE_MEM,
175 static struct physmap_flash_data zeus_flash_data[] = {
183 static struct platform_device zeus_mtd_devices[] = {
185 .name = "physmap-flash",
188 .platform_data = &zeus_flash_data[0],
190 .resource = &zeus_mtd_resources[0],
196 static struct resource zeus_serial_resources[] = {
200 .flags = IORESOURCE_MEM,
205 .flags = IORESOURCE_MEM,
210 .flags = IORESOURCE_MEM,
215 .flags = IORESOURCE_MEM,
220 .flags = IORESOURCE_MEM,
225 .flags = IORESOURCE_MEM,
229 static struct plat_serial8250_port serial_platform_data[] = {
231 /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
233 .mapbase = 0x10000000,
234 .irq = gpio_to_irq(ZEUS_UARTA_GPIO),
235 .irqflags = IRQF_TRIGGER_RISING,
238 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
242 .mapbase = 0x10800000,
243 .irq = gpio_to_irq(ZEUS_UARTB_GPIO),
244 .irqflags = IRQF_TRIGGER_RISING,
247 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
251 .mapbase = 0x11000000,
252 .irq = gpio_to_irq(ZEUS_UARTC_GPIO),
253 .irqflags = IRQF_TRIGGER_RISING,
256 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
260 .mapbase = 0x11800000,
261 .irq = gpio_to_irq(ZEUS_UARTD_GPIO),
262 .irqflags = IRQF_TRIGGER_RISING,
265 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
270 .membase = (void *)&FFUART,
271 .mapbase = __PREG(FFUART),
273 .uartclk = 921600 * 16,
275 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
279 .membase = (void *)&BTUART,
280 .mapbase = __PREG(BTUART),
282 .uartclk = 921600 * 16,
284 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
288 .membase = (void *)&STUART,
289 .mapbase = __PREG(STUART),
291 .uartclk = 921600 * 16,
293 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
299 static struct platform_device zeus_serial_device = {
300 .name = "serial8250",
301 .id = PLAT8250_DEV_PLATFORM,
303 .platform_data = serial_platform_data,
305 .num_resources = ARRAY_SIZE(zeus_serial_resources),
306 .resource = zeus_serial_resources,
310 static struct resource zeus_dm9k0_resource[] = {
312 .start = ZEUS_ETH0_PHYS,
313 .end = ZEUS_ETH0_PHYS + 1,
314 .flags = IORESOURCE_MEM
317 .start = ZEUS_ETH0_PHYS + 2,
318 .end = ZEUS_ETH0_PHYS + 3,
319 .flags = IORESOURCE_MEM
322 .start = gpio_to_irq(ZEUS_ETH0_GPIO),
323 .end = gpio_to_irq(ZEUS_ETH0_GPIO),
324 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
328 static struct resource zeus_dm9k1_resource[] = {
330 .start = ZEUS_ETH1_PHYS,
331 .end = ZEUS_ETH1_PHYS + 1,
332 .flags = IORESOURCE_MEM
335 .start = ZEUS_ETH1_PHYS + 2,
336 .end = ZEUS_ETH1_PHYS + 3,
337 .flags = IORESOURCE_MEM,
340 .start = gpio_to_irq(ZEUS_ETH1_GPIO),
341 .end = gpio_to_irq(ZEUS_ETH1_GPIO),
342 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
346 static struct dm9000_plat_data zeus_dm9k_platdata = {
347 .flags = DM9000_PLATF_16BITONLY,
350 static struct platform_device zeus_dm9k0_device = {
353 .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
354 .resource = zeus_dm9k0_resource,
356 .platform_data = &zeus_dm9k_platdata,
360 static struct platform_device zeus_dm9k1_device = {
363 .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
364 .resource = zeus_dm9k1_resource,
366 .platform_data = &zeus_dm9k_platdata,
371 static struct resource zeus_sram_resource = {
372 .start = ZEUS_SRAM_PHYS,
373 .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
374 .flags = IORESOURCE_MEM,
377 static struct platform_device zeus_sram_device = {
378 .name = "pxa2xx-8bit-sram",
381 .resource = &zeus_sram_resource,
384 /* SPI interface on SSP3 */
385 static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
390 static struct platform_device pxa2xx_spi_ssp3_device = {
391 .name = "pxa2xx-spi",
394 .platform_data = &pxa2xx_spi_ssp3_master_info,
399 static struct gpio_led zeus_leds[] = {
401 .name = "zeus:yellow:1",
402 .default_trigger = "heartbeat",
403 .gpio = ZEUS_EXT0_GPIO(3),
407 .name = "zeus:yellow:2",
408 .default_trigger = "default-on",
409 .gpio = ZEUS_EXT0_GPIO(4),
413 .name = "zeus:yellow:3",
414 .default_trigger = "default-on",
415 .gpio = ZEUS_EXT0_GPIO(5),
420 static struct gpio_led_platform_data zeus_leds_info = {
422 .num_leds = ARRAY_SIZE(zeus_leds),
425 static struct platform_device zeus_leds_device = {
429 .platform_data = &zeus_leds_info,
433 static void zeus_cf_reset(int state)
435 u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
438 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
440 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
442 __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
445 static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
446 .cd_gpio = ZEUS_CF_CD_GPIO,
447 .rdy_gpio = ZEUS_CF_RDY_GPIO,
448 .pwr_gpio = ZEUS_CF_PWEN_GPIO,
449 .reset = zeus_cf_reset,
452 static struct platform_device zeus_pcmcia_device = {
453 .name = "zeus-pcmcia",
456 .platform_data = &zeus_pcmcia_info,
460 static struct platform_device *zeus_devices[] __initdata = {
462 &zeus_mtd_devices[0],
466 &pxa2xx_spi_ssp3_device,
472 static pxa2xx_audio_ops_t zeus_ac97_info = {
481 static int zeus_ohci_init(struct device *dev)
485 /* Switch on port 2. */
486 if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) {
487 dev_err(dev, "Can't request USB2_PWREN\n");
491 if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) {
492 gpio_free(ZEUS_USB2_PWREN_GPIO);
493 dev_err(dev, "Can't enable USB2_PWREN\n");
497 /* Port 2 is shared between host and client interface. */
498 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
503 static void zeus_ohci_exit(struct device *dev)
505 /* Power-off port 2 */
506 gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0);
507 gpio_free(ZEUS_USB2_PWREN_GPIO);
510 static struct pxaohci_platform_data zeus_ohci_platform_data = {
511 .port_mode = PMM_NPS_MODE,
512 .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
513 .init = zeus_ohci_init,
514 .exit = zeus_ohci_exit,
521 static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
523 gpio_set_value(ZEUS_LCD_EN_GPIO, on);
526 static void zeus_backlight_power(int on)
528 gpio_set_value(ZEUS_BKLEN_GPIO, on);
531 static int zeus_setup_fb_gpios(void)
535 if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
538 if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
541 if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
544 if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
550 gpio_free(ZEUS_BKLEN_GPIO);
552 gpio_free(ZEUS_LCD_EN_GPIO);
557 static struct pxafb_mode_info zeus_fb_mode_info[] = {
578 static struct pxafb_mach_info zeus_fb_info = {
579 .modes = zeus_fb_mode_info,
581 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
582 .pxafb_lcd_power = zeus_lcd_power,
583 .pxafb_backlight_power = zeus_backlight_power,
589 * The card detect interrupt isn't debounced so we delay it by 250ms
590 * to give the card a chance to fully insert/eject.
593 static struct pxamci_platform_data zeus_mci_platform_data = {
594 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
595 .detect_delay = HZ/4,
596 .gpio_card_detect = ZEUS_MMC_CD_GPIO,
597 .gpio_card_ro = ZEUS_MMC_WP_GPIO,
598 .gpio_card_ro_invert = 1,
603 * USB Device Controller
605 static void zeus_udc_command(int cmd)
608 case PXA2XX_UDC_CMD_DISCONNECT:
609 pr_info("zeus: disconnecting USB client\n");
610 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
613 case PXA2XX_UDC_CMD_CONNECT:
614 pr_info("zeus: connecting USB client\n");
615 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
620 static struct pxa2xx_udc_mach_info zeus_udc_info = {
621 .udc_command = zeus_udc_command,
624 static void zeus_power_off(void)
627 pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP);
630 #ifdef CONFIG_APM_EMULATION
631 static void zeus_get_power_status(struct apm_power_info *info)
633 /* Power supply is always present */
634 info->ac_line_status = APM_AC_ONLINE;
635 info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
636 info->battery_flag = APM_BATTERY_FLAG_NOT_PRESENT;
639 static inline void zeus_setup_apm(void)
641 apm_get_power_status = zeus_get_power_status;
644 static inline void zeus_setup_apm(void)
649 static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
650 unsigned ngpio, void *context)
655 for (i = 0; i < 8; i++) {
656 int pcb_bit = gpio + i + 8;
658 if (gpio_request(pcb_bit, "pcb info")) {
659 dev_err(&client->dev, "Can't request pcb info %d\n", i);
663 if (gpio_direction_input(pcb_bit)) {
664 dev_err(&client->dev, "Can't read pcb info %d\n", i);
669 pcb_info |= !!gpio_get_value(pcb_bit) << i;
674 dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
675 pcb_info >> 4, pcb_info & 0xf);
680 static struct pca953x_platform_data zeus_pca953x_pdata[] = {
681 [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, },
683 .gpio_base = ZEUS_EXT1_GPIO_BASE,
684 .setup = zeus_get_pcb_info,
686 [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
689 static struct i2c_board_info __initdata zeus_i2c_devices[] = {
691 I2C_BOARD_INFO("pca9535", 0x21),
692 .platform_data = &zeus_pca953x_pdata[0],
695 I2C_BOARD_INFO("pca9535", 0x22),
696 .platform_data = &zeus_pca953x_pdata[1],
699 I2C_BOARD_INFO("pca9535", 0x20),
700 .platform_data = &zeus_pca953x_pdata[2],
701 .irq = gpio_to_irq(ZEUS_EXTGPIO_GPIO),
703 { I2C_BOARD_INFO("lm75a", 0x48) },
704 { I2C_BOARD_INFO("24c01", 0x50) },
705 { I2C_BOARD_INFO("isl1208", 0x6f) },
708 static mfp_cfg_t zeus_pin_config[] __initdata = {
744 GPIO36_GPIO, /* CF CD */
745 GPIO97_GPIO, /* CF PWREN */
746 GPIO99_GPIO, /* CF RDY */
750 * DM9k MSCx settings: SRAM, 16 bits
751 * 17 cycles delay first access
752 * 5 cycles delay next access
753 * 13 cycles recovery time
756 #define DM9K_MSC_VALUE 0xe4c9
758 static void __init zeus_init(void)
760 u16 dm9000_msc = DM9K_MSC_VALUE;
762 system_rev = __raw_readw(ZEUS_CPLD_VERSION);
763 pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
765 /* Fix timings for dm9000s (CS1/CS2)*/
766 MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16);
767 MSC1 = (MSC1 & 0xffff0000) | dm9000_msc;
769 pm_power_off = zeus_power_off;
772 pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
774 platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
776 pxa_set_ohci_info(&zeus_ohci_platform_data);
778 if (zeus_setup_fb_gpios())
779 pr_err("Failed to setup fb gpios\n");
781 set_pxa_fb_info(&zeus_fb_info);
783 pxa_set_mci_info(&zeus_mci_platform_data);
784 pxa_set_udc_info(&zeus_udc_info);
785 pxa_set_ac97_info(&zeus_ac97_info);
786 pxa_set_i2c_info(NULL);
787 i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
790 static struct map_desc zeus_io_desc[] __initdata = {
792 .virtual = ZEUS_CPLD_VERSION,
793 .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
798 .virtual = ZEUS_CPLD_ISA_IRQ,
799 .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
804 .virtual = ZEUS_CPLD_CONTROL,
805 .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
810 .virtual = ZEUS_CPLD_EXTWDOG,
811 .pfn = __phys_to_pfn(ZEUS_CPLD_EXTWDOG_PHYS),
816 .virtual = ZEUS_PC104IO,
817 .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
818 .length = 0x00800000,
823 static void __init zeus_map_io(void)
827 iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
829 /* Clear PSPR to ensure a full restart on wake-up. */
832 /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
835 /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
836 * float chip selects and PCMCIA */
837 PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
840 MACHINE_START(ARCOM_ZEUS, "Arcom ZEUS")
841 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
842 .phys_io = 0x40000000,
843 .io_pg_offst = ((io_p2v(0x40000000) >> 18) & 0xfffc),
844 .boot_params = 0xa0000100,
845 .map_io = zeus_map_io,
846 .init_irq = zeus_init_irq,
848 .init_machine = zeus_init,