2 * arch/arm/mach-pxa/include/mach/pxa-regs.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 #include <mach/hardware.h>
22 #define PXA_CS0_PHYS 0x00000000
23 #define PXA_CS1_PHYS 0x04000000
24 #define PXA_CS2_PHYS 0x08000000
25 #define PXA_CS3_PHYS 0x0C000000
26 #define PXA_CS4_PHYS 0x10000000
27 #define PXA_CS5_PHYS 0x14000000
31 * Personal Computer Memory Card International Association (PCMCIA) sockets
34 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
35 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
36 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
37 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
38 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
40 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
41 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
42 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
43 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
45 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
46 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
47 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
48 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
50 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
51 (0x20000000 + (Nb)*PCMCIASp)
52 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
53 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
54 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
55 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
56 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
58 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
59 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
60 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
61 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
63 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
64 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
65 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
66 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
72 #define RCNR __REG(0x40900000) /* RTC Count Register */
73 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
74 #define RTSR __REG(0x40900008) /* RTC Status Register */
75 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
76 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
78 #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
79 #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
80 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
81 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
82 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
83 #define RTSR_AL (1 << 0) /* RTC alarm detected */
87 * OS Timer & Match Registers
90 #define OSMR0 __REG(0x40A00000) /* */
91 #define OSMR1 __REG(0x40A00004) /* */
92 #define OSMR2 __REG(0x40A00008) /* */
93 #define OSMR3 __REG(0x40A0000C) /* */
94 #define OSMR4 __REG(0x40A00080) /* */
95 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
96 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
97 #define OMCR4 __REG(0x40A000C0) /* */
98 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
99 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
100 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
102 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
103 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
104 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
105 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
107 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
109 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
110 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
111 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
112 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
116 * Interrupt Controller
119 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
120 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
121 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
122 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
123 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
124 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
126 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
127 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
128 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
129 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
130 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
133 * General Purpose I/O
136 #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
137 #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
138 #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
140 #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
141 #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
142 #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
144 #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
145 #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
146 #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
148 #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
149 #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
150 #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
152 #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
153 #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
154 #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
156 #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
157 #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
158 #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
160 #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
161 #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
162 #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
164 #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
165 #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
166 #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
167 #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
168 #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
169 #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
170 #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
171 #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
173 #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
174 #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
175 #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
176 #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
177 #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
178 #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
179 #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
181 /* More handy macros. The argument is a literal GPIO number. */
183 #define GPIO_bit(x) (1 << ((x) & 0x1f))
185 #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
186 #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
187 #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
188 #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
189 #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
190 #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
191 #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
192 #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
194 #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
195 #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
196 #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
197 #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
198 #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
199 #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
200 #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
201 #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
202 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))