2 * arch/arm/mach-orion5x/include/mach/orion5x.h
4 * Generic definitions of Orion SoC flavors:
5 * Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90.
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #ifndef __ASM_ARCH_ORION5X_H
15 #define __ASM_ARCH_ORION5X_H
17 /*****************************************************************************
21 * e0000000 PCIe MEM space
22 * e8000000 PCI MEM space
23 * f0000000 PCIe WA space (Orion-1/Orion-NAS only)
24 * f1000000 on-chip peripheral registers
25 * f2000000 PCIe I/O space
26 * f2100000 PCI I/O space
27 * f4000000 device bus mappings (boot)
28 * fa000000 device bus mappings (cs0)
29 * fa800000 device bus mappings (cs2)
30 * fc000000 device bus mappings (cs0/cs1)
33 * fdd00000 f1000000 1M on-chip peripheral registers
34 * fde00000 f2000000 1M PCIe I/O space
35 * fdf00000 f2100000 1M PCI I/O space
36 * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
37 ****************************************************************************/
38 #define ORION5X_REGS_PHYS_BASE 0xf1000000
39 #define ORION5X_REGS_VIRT_BASE 0xfdd00000
40 #define ORION5X_REGS_SIZE SZ_1M
42 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
43 #define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000
44 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000
45 #define ORION5X_PCIE_IO_SIZE SZ_1M
47 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
48 #define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000
49 #define ORION5X_PCI_IO_BUS_BASE 0x00100000
50 #define ORION5X_PCI_IO_SIZE SZ_1M
52 /* Relevant only for Orion-1/Orion-NAS */
53 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
54 #define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000
55 #define ORION5X_PCIE_WA_SIZE SZ_16M
57 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
58 #define ORION5X_PCIE_MEM_SIZE SZ_128M
60 #define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000
61 #define ORION5X_PCI_MEM_SIZE SZ_128M
63 /*******************************************************************************
65 ******************************************************************************/
67 #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
69 #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
70 #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
71 #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
72 #define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
73 #define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
74 #define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
75 #define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
76 #define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
77 #define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
79 #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
81 #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
83 #define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
85 #define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
86 #define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
88 #define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900)
89 #define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900)
91 #define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
92 #define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
94 #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
95 #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
97 #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
98 #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
100 /*******************************************************************************
101 * Device Bus Registers
102 ******************************************************************************/
103 #define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
104 #define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
105 #define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
106 #define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
107 #define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
108 #define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
109 #define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
110 #define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
111 #define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
112 #define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
113 #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
114 #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
116 /*******************************************************************************
117 * Supported Devices & Revisions
118 ******************************************************************************/
119 /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
120 #define MV88F5181_DEV_ID 0x5181
121 #define MV88F5181_REV_B1 3
122 #define MV88F5181L_REV_A0 8
123 #define MV88F5181L_REV_A1 9
124 /* Orion-NAS (88F5182) */
125 #define MV88F5182_DEV_ID 0x5182
126 #define MV88F5182_REV_A2 2
127 /* Orion-2 (88F5281) */
128 #define MV88F5281_DEV_ID 0x5281
129 #define MV88F5281_REV_D0 4
130 #define MV88F5281_REV_D1 5
131 #define MV88F5281_REV_D2 6
132 /* Orion-1-90 (88F6183) */
133 #define MV88F6183_DEV_ID 0x6183
134 #define MV88F6183_REV_B0 3