regulator: tps62360: Fix up a pointer-integer size mismatch warning
[linux-2.6-block.git] / arch / arm / mach-omap2 / pm24xx.c
1 /*
2  * OMAP2 Power Management Routines
3  *
4  * Copyright (C) 2005 Texas Instruments, Inc.
5  * Copyright (C) 2006-2008 Nokia Corporation
6  *
7  * Written by:
8  * Richard Woodruff <r-woodruff2@ti.com>
9  * Tony Lindgren
10  * Juha Yrjola
11  * Amit Kucheria <amit.kucheria@nokia.com>
12  * Igor Stoppa <igor.stoppa@nokia.com>
13  *
14  * Based on pm.c for omap1
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk-provider.h>
29 #include <linux/irq.h>
30 #include <linux/time.h>
31 #include <linux/gpio.h>
32 #include <linux/platform_data/gpio-omap.h>
33
34 #include <asm/fncpy.h>
35
36 #include <asm/mach/time.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach-types.h>
39 #include <asm/system_misc.h>
40
41 #include <linux/omap-dma.h>
42
43 #include "soc.h"
44 #include "common.h"
45 #include "clock.h"
46 #include "prm2xxx.h"
47 #include "prm-regbits-24xx.h"
48 #include "cm2xxx.h"
49 #include "cm-regbits-24xx.h"
50 #include "sdrc.h"
51 #include "sram.h"
52 #include "pm.h"
53 #include "control.h"
54 #include "powerdomain.h"
55 #include "clockdomain.h"
56
57 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
58                                   void __iomem *sdrc_power);
59
60 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
61 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
62
63 static struct clk *osc_ck, *emul_ck;
64
65 static int omap2_enter_full_retention(void)
66 {
67         u32 l;
68
69         /* There is 1 reference hold for all children of the oscillator
70          * clock, the following will remove it. If no one else uses the
71          * oscillator itself it will be disabled if/when we enter retention
72          * mode.
73          */
74         clk_disable(osc_ck);
75
76         /* Clear old wake-up events */
77         /* REVISIT: These write to reserved bits? */
78         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
79         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
80         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
81
82         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
83         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
84
85         /* Workaround to kill USB */
86         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
87         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
88
89         omap2_gpio_prepare_for_idle(0);
90
91         /* One last check for pending IRQs to avoid extra latency due
92          * to sleeping unnecessarily. */
93         if (omap_irq_pending())
94                 goto no_sleep;
95
96         /* Jump to SRAM suspend code */
97         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
98                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
99                            OMAP_SDRC_REGADDR(SDRC_POWER));
100
101 no_sleep:
102         omap2_gpio_resume_after_idle();
103
104         clk_enable(osc_ck);
105
106         /* clear CORE wake-up events */
107         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
108         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
109
110         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
111         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
112
113         /* MPU domain wake events */
114         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
115         if (l & 0x01)
116                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
117                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
118         if (l & 0x20)
119                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
120                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
121
122         /* Mask future PRCM-to-MPU interrupts */
123         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
124
125         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
126         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
127
128         return 0;
129 }
130
131 static int sti_console_enabled;
132
133 static int omap2_allow_mpu_retention(void)
134 {
135         if (!omap2xxx_cm_mpu_retention_allowed())
136                 return 0;
137         if (sti_console_enabled)
138                 return 0;
139
140         return 1;
141 }
142
143 static void omap2_enter_mpu_retention(void)
144 {
145         const int zero = 0;
146
147         /* The peripherals seem not to be able to wake up the MPU when
148          * it is in retention mode. */
149         if (omap2_allow_mpu_retention()) {
150                 /* REVISIT: These write to reserved bits? */
151                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
152                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
153                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
154
155                 /* Try to enter MPU retention */
156                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
157
158         } else {
159                 /* Block MPU retention */
160                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
161         }
162
163         /* WFI */
164         asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
165
166         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
167 }
168
169 static int omap2_can_sleep(void)
170 {
171         if (omap2xxx_cm_fclks_active())
172                 return 0;
173         if (__clk_is_enabled(osc_ck))
174                 return 0;
175         if (omap_dma_running())
176                 return 0;
177
178         return 1;
179 }
180
181 static void omap2_pm_idle(void)
182 {
183         if (!omap2_can_sleep()) {
184                 if (omap_irq_pending())
185                         return;
186                 omap2_enter_mpu_retention();
187                 return;
188         }
189
190         if (omap_irq_pending())
191                 return;
192
193         omap2_enter_full_retention();
194 }
195
196 static void __init prcm_setup_regs(void)
197 {
198         int i, num_mem_banks;
199         struct powerdomain *pwrdm;
200
201         /*
202          * Enable autoidle
203          * XXX This should be handled by hwmod code or PRCM init code
204          */
205         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
206                           OMAP2_PRCM_SYSCONFIG_OFFSET);
207
208         /*
209          * Set CORE powerdomain memory banks to retain their contents
210          * during RETENTION
211          */
212         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
213         for (i = 0; i < num_mem_banks; i++)
214                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
215
216         pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
217
218         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
219
220         /* Force-power down DSP, GFX powerdomains */
221
222         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
223         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
224
225         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
226         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
227
228         /* Enable hardware-supervised idle for all clkdms */
229         clkdm_for_each(omap_pm_clkdms_setup, NULL);
230         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
231
232 #ifdef CONFIG_SUSPEND
233         omap_pm_suspend = omap2_enter_full_retention;
234 #endif
235
236         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
237          * stabilisation */
238         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
239                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
240
241         /* Configure automatic voltage transition */
242         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
243                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
244         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
245                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
246                                 OMAP24XX_MEMRETCTRL_MASK |
247                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
248                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
249                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
250
251         /* Enable wake-up events */
252         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
253                                 WKUP_MOD, PM_WKEN);
254 }
255
256 int __init omap2_pm_init(void)
257 {
258         u32 l;
259
260         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
261         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
262         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
263
264         /* Look up important powerdomains */
265
266         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
267         if (!mpu_pwrdm)
268                 pr_err("PM: mpu_pwrdm not found\n");
269
270         core_pwrdm = pwrdm_lookup("core_pwrdm");
271         if (!core_pwrdm)
272                 pr_err("PM: core_pwrdm not found\n");
273
274         /* Look up important clockdomains */
275
276         mpu_clkdm = clkdm_lookup("mpu_clkdm");
277         if (!mpu_clkdm)
278                 pr_err("PM: mpu_clkdm not found\n");
279
280         wkup_clkdm = clkdm_lookup("wkup_clkdm");
281         if (!wkup_clkdm)
282                 pr_err("PM: wkup_clkdm not found\n");
283
284         dsp_clkdm = clkdm_lookup("dsp_clkdm");
285         if (!dsp_clkdm)
286                 pr_err("PM: dsp_clkdm not found\n");
287
288         gfx_clkdm = clkdm_lookup("gfx_clkdm");
289         if (!gfx_clkdm)
290                 pr_err("PM: gfx_clkdm not found\n");
291
292
293         osc_ck = clk_get(NULL, "osc_ck");
294         if (IS_ERR(osc_ck)) {
295                 printk(KERN_ERR "could not get osc_ck\n");
296                 return -ENODEV;
297         }
298
299         if (cpu_is_omap242x()) {
300                 emul_ck = clk_get(NULL, "emul_ck");
301                 if (IS_ERR(emul_ck)) {
302                         printk(KERN_ERR "could not get emul_ck\n");
303                         clk_put(osc_ck);
304                         return -ENODEV;
305                 }
306         }
307
308         prcm_setup_regs();
309
310         /*
311          * We copy the assembler sleep/wakeup routines to SRAM.
312          * These routines need to be in SRAM as that's the only
313          * memory the MPU can see when it wakes up after the entire
314          * chip enters idle.
315          */
316         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
317                                             omap24xx_cpu_suspend_sz);
318
319         arm_pm_idle = omap2_pm_idle;
320
321         return 0;
322 }