4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/platform_data/gpio-omap.h>
19 #include <linux/platform_data/hsmmc-omap.h>
20 #include <linux/platform_data/spi-omap2-mcspi.h>
21 #include <plat/dmtimer.h>
23 #include "omap_hwmod_common_data.h"
29 * DM816X hardware modules integration data
31 * Note: This is incomplete and at present, not generated from h/w database.
35 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
36 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
38 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140
39 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144
40 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148
41 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c
42 #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150
43 #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154
44 #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158
45 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c
46 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160
47 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164
48 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168
49 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c
50 #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190
51 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194
52 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198
53 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c
54 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8
55 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4
56 #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0
57 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4
58 #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4
59 #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8
60 #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec
61 #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0
62 #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4
63 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8
64 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc
65 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200
66 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204
68 /* Registers specific to dm814x */
69 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c
70 #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170
71 #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174
72 #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178
73 #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180
74 #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184
75 #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188
76 #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4
77 #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8
78 #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc
79 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0
80 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218
81 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c
82 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220
83 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224
84 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228
86 /* Registers specific to dm816x */
87 #define DM816X_DM_ALWON_BASE 0x1400
88 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
89 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
90 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
91 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
92 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
93 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
94 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
95 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE)
96 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE)
97 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE)
98 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
99 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE)
100 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE)
101 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE)
104 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
105 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
107 #define DM81XX_CM_DEFAULT_OFFSET 0x500
108 #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET)
110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
112 .name = "alwon_l3_slow",
113 .clkdm_name = "alwon_l3s_clkdm",
114 .class = &l3_hwmod_class,
115 .flags = HWMOD_NO_IDLEST,
118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
119 .name = "default_l3_slow",
120 .clkdm_name = "default_l3_slow_clkdm",
121 .class = &l3_hwmod_class,
122 .flags = HWMOD_NO_IDLEST,
125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
127 .clkdm_name = "alwon_l3_med_clkdm",
128 .class = &l3_hwmod_class,
129 .flags = HWMOD_NO_IDLEST,
132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
134 .clkdm_name = "alwon_l3_fast_clkdm",
135 .class = &l3_hwmod_class,
136 .flags = HWMOD_NO_IDLEST,
140 * L4 standard peripherals, see TRM table 1-12 for devices using this.
141 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
143 static struct omap_hwmod dm81xx_l4_ls_hwmod = {
145 .clkdm_name = "alwon_l3s_clkdm",
146 .class = &l4_hwmod_class,
147 .flags = HWMOD_NO_IDLEST,
151 * L4 high-speed peripherals. For devices using this, please see the TRM
152 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
153 * table 1-73 for devices using 250MHz SYSCLK5 clock.
155 static struct omap_hwmod dm81xx_l4_hs_hwmod = {
157 .clkdm_name = "alwon_l3_med_clkdm",
158 .class = &l4_hwmod_class,
159 .flags = HWMOD_NO_IDLEST,
162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
164 .master = &dm81xx_alwon_l3_slow_hwmod,
165 .slave = &dm81xx_l4_ls_hwmod,
166 .user = OCP_USER_MPU,
169 /* L3 med -> L4 fast peripheral interface running at 250MHz */
170 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
171 .master = &dm81xx_alwon_l3_med_hwmod,
172 .slave = &dm81xx_l4_hs_hwmod,
173 .user = OCP_USER_MPU,
177 static struct omap_hwmod dm814x_mpu_hwmod = {
179 .clkdm_name = "alwon_l3s_clkdm",
180 .class = &mpu_hwmod_class,
181 .flags = HWMOD_INIT_NO_IDLE,
182 .main_clk = "mpu_ck",
185 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
186 .modulemode = MODULEMODE_SWCTRL,
191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
192 .master = &dm814x_mpu_hwmod,
193 .slave = &dm81xx_alwon_l3_slow_hwmod,
194 .user = OCP_USER_MPU,
197 /* L3 med peripheral interface running at 200MHz */
198 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
199 .master = &dm814x_mpu_hwmod,
200 .slave = &dm81xx_alwon_l3_med_hwmod,
201 .user = OCP_USER_MPU,
204 static struct omap_hwmod dm816x_mpu_hwmod = {
206 .clkdm_name = "alwon_mpu_clkdm",
207 .class = &mpu_hwmod_class,
208 .flags = HWMOD_INIT_NO_IDLE,
209 .main_clk = "mpu_ck",
212 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
213 .modulemode = MODULEMODE_SWCTRL,
218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
219 .master = &dm816x_mpu_hwmod,
220 .slave = &dm81xx_alwon_l3_slow_hwmod,
221 .user = OCP_USER_MPU,
224 /* L3 med peripheral interface running at 250MHz */
225 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
226 .master = &dm816x_mpu_hwmod,
227 .slave = &dm81xx_alwon_l3_med_hwmod,
228 .user = OCP_USER_MPU,
232 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
235 .sysc_flags = SYSC_HAS_SIDLEMODE,
236 .idlemodes = SIDLE_FORCE | SIDLE_NO |
237 SIDLE_SMART | SIDLE_SMART_WKUP,
238 .sysc_fields = &omap_hwmod_sysc_type3,
241 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
243 .sysc = &ti81xx_rtc_sysc,
246 struct omap_hwmod ti81xx_rtc_hwmod = {
248 .class = &ti81xx_rtc_hwmod_class,
249 .clkdm_name = "alwon_l3s_clkdm",
250 .flags = HWMOD_NO_IDLEST,
251 .main_clk = "sysclk18_ck",
254 .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
255 .modulemode = MODULEMODE_SWCTRL,
260 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
261 .master = &dm81xx_l4_ls_hwmod,
262 .slave = &ti81xx_rtc_hwmod,
264 .user = OCP_USER_MPU,
268 static struct omap_hwmod_class_sysconfig uart_sysc = {
272 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
273 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
274 SYSS_HAS_RESET_STATUS,
275 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
277 .sysc_fields = &omap_hwmod_sysc_type1,
280 static struct omap_hwmod_class uart_class = {
285 static struct omap_hwmod dm81xx_uart1_hwmod = {
287 .clkdm_name = "alwon_l3s_clkdm",
288 .main_clk = "sysclk10_ck",
291 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
292 .modulemode = MODULEMODE_SWCTRL,
295 .class = &uart_class,
296 .flags = DEBUG_TI81XXUART1_FLAGS,
299 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
300 .master = &dm81xx_l4_ls_hwmod,
301 .slave = &dm81xx_uart1_hwmod,
303 .user = OCP_USER_MPU,
306 static struct omap_hwmod dm81xx_uart2_hwmod = {
308 .clkdm_name = "alwon_l3s_clkdm",
309 .main_clk = "sysclk10_ck",
312 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
313 .modulemode = MODULEMODE_SWCTRL,
316 .class = &uart_class,
317 .flags = DEBUG_TI81XXUART2_FLAGS,
320 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
321 .master = &dm81xx_l4_ls_hwmod,
322 .slave = &dm81xx_uart2_hwmod,
324 .user = OCP_USER_MPU,
327 static struct omap_hwmod dm81xx_uart3_hwmod = {
329 .clkdm_name = "alwon_l3s_clkdm",
330 .main_clk = "sysclk10_ck",
333 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
334 .modulemode = MODULEMODE_SWCTRL,
337 .class = &uart_class,
338 .flags = DEBUG_TI81XXUART3_FLAGS,
341 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
342 .master = &dm81xx_l4_ls_hwmod,
343 .slave = &dm81xx_uart3_hwmod,
345 .user = OCP_USER_MPU,
348 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
352 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
353 SYSS_HAS_RESET_STATUS,
354 .sysc_fields = &omap_hwmod_sysc_type1,
357 static struct omap_hwmod_class wd_timer_class = {
359 .sysc = &wd_timer_sysc,
360 .pre_shutdown = &omap2_wd_timer_disable,
361 .reset = &omap2_wd_timer_reset,
364 static struct omap_hwmod dm81xx_wd_timer_hwmod = {
366 .clkdm_name = "alwon_l3s_clkdm",
367 .main_clk = "sysclk18_ck",
368 .flags = HWMOD_NO_IDLEST,
371 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
372 .modulemode = MODULEMODE_SWCTRL,
375 .class = &wd_timer_class,
378 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
379 .master = &dm81xx_l4_ls_hwmod,
380 .slave = &dm81xx_wd_timer_hwmod,
382 .user = OCP_USER_MPU,
386 static struct omap_hwmod_class_sysconfig i2c_sysc = {
390 .sysc_flags = SYSC_HAS_SIDLEMODE |
391 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
393 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
394 .sysc_fields = &omap_hwmod_sysc_type1,
397 static struct omap_hwmod_class i2c_class = {
402 static struct omap_hwmod dm81xx_i2c1_hwmod = {
404 .clkdm_name = "alwon_l3s_clkdm",
405 .main_clk = "sysclk10_ck",
408 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
409 .modulemode = MODULEMODE_SWCTRL,
415 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
416 .master = &dm81xx_l4_ls_hwmod,
417 .slave = &dm81xx_i2c1_hwmod,
419 .user = OCP_USER_MPU,
422 static struct omap_hwmod dm81xx_i2c2_hwmod = {
424 .clkdm_name = "alwon_l3s_clkdm",
425 .main_clk = "sysclk10_ck",
428 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
429 .modulemode = MODULEMODE_SWCTRL,
435 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
439 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
441 SYSS_HAS_RESET_STATUS,
442 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
443 .sysc_fields = &omap_hwmod_sysc_type1,
446 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
447 .master = &dm81xx_l4_ls_hwmod,
448 .slave = &dm81xx_i2c2_hwmod,
450 .user = OCP_USER_MPU,
453 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
455 .sysc = &dm81xx_elm_sysc,
458 static struct omap_hwmod dm81xx_elm_hwmod = {
460 .clkdm_name = "alwon_l3s_clkdm",
461 .class = &dm81xx_elm_hwmod_class,
462 .main_clk = "sysclk6_ck",
465 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
466 .master = &dm81xx_l4_ls_hwmod,
467 .slave = &dm81xx_elm_hwmod,
469 .user = OCP_USER_MPU,
472 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
476 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
477 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
478 SYSS_HAS_RESET_STATUS,
479 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
481 .sysc_fields = &omap_hwmod_sysc_type1,
484 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
486 .sysc = &dm81xx_gpio_sysc,
490 static struct omap_gpio_dev_attr gpio_dev_attr = {
495 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
496 { .role = "dbclk", .clk = "sysclk18_ck" },
499 static struct omap_hwmod dm81xx_gpio1_hwmod = {
501 .clkdm_name = "alwon_l3s_clkdm",
502 .class = &dm81xx_gpio_hwmod_class,
503 .main_clk = "sysclk6_ck",
506 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
507 .modulemode = MODULEMODE_SWCTRL,
510 .opt_clks = gpio1_opt_clks,
511 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
512 .dev_attr = &gpio_dev_attr,
515 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
516 .master = &dm81xx_l4_ls_hwmod,
517 .slave = &dm81xx_gpio1_hwmod,
519 .user = OCP_USER_MPU,
522 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
523 { .role = "dbclk", .clk = "sysclk18_ck" },
526 static struct omap_hwmod dm81xx_gpio2_hwmod = {
528 .clkdm_name = "alwon_l3s_clkdm",
529 .class = &dm81xx_gpio_hwmod_class,
530 .main_clk = "sysclk6_ck",
533 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
534 .modulemode = MODULEMODE_SWCTRL,
537 .opt_clks = gpio2_opt_clks,
538 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
539 .dev_attr = &gpio_dev_attr,
542 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
543 .master = &dm81xx_l4_ls_hwmod,
544 .slave = &dm81xx_gpio2_hwmod,
546 .user = OCP_USER_MPU,
549 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
553 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
554 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
555 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
556 .sysc_fields = &omap_hwmod_sysc_type1,
559 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
561 .sysc = &dm81xx_gpmc_sysc,
564 static struct omap_hwmod dm81xx_gpmc_hwmod = {
566 .clkdm_name = "alwon_l3s_clkdm",
567 .class = &dm81xx_gpmc_hwmod_class,
568 .main_clk = "sysclk6_ck",
569 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
570 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
573 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
574 .modulemode = MODULEMODE_SWCTRL,
579 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
580 .master = &dm81xx_alwon_l3_slow_hwmod,
581 .slave = &dm81xx_gpmc_hwmod,
582 .user = OCP_USER_MPU,
585 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
588 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
590 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
591 .sysc_fields = &omap_hwmod_sysc_type2,
594 static struct omap_hwmod_class dm81xx_usbotg_class = {
596 .sysc = &dm81xx_usbhsotg_sysc,
599 static struct omap_hwmod dm814x_usbss_hwmod = {
600 .name = "usb_otg_hs",
601 .clkdm_name = "default_l3_slow_clkdm",
602 .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */
605 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
606 .modulemode = MODULEMODE_SWCTRL,
609 .class = &dm81xx_usbotg_class,
612 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
613 .master = &dm81xx_default_l3_slow_hwmod,
614 .slave = &dm814x_usbss_hwmod,
616 .user = OCP_USER_MPU,
619 static struct omap_hwmod dm816x_usbss_hwmod = {
620 .name = "usb_otg_hs",
621 .clkdm_name = "default_l3_slow_clkdm",
622 .main_clk = "sysclk6_ck",
625 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
626 .modulemode = MODULEMODE_SWCTRL,
629 .class = &dm81xx_usbotg_class,
632 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
633 .master = &dm81xx_default_l3_slow_hwmod,
634 .slave = &dm816x_usbss_hwmod,
636 .user = OCP_USER_MPU,
639 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
643 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
644 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
646 .sysc_fields = &omap_hwmod_sysc_type2,
649 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
651 .sysc = &dm816x_timer_sysc,
654 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
655 .timer_capability = OMAP_TIMER_ALWON,
658 static struct omap_hwmod dm814x_timer1_hwmod = {
660 .clkdm_name = "alwon_l3s_clkdm",
661 .main_clk = "timer1_fck",
662 .dev_attr = &capability_alwon_dev_attr,
663 .class = &dm816x_timer_hwmod_class,
664 .flags = HWMOD_NO_IDLEST,
667 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
668 .master = &dm81xx_l4_ls_hwmod,
669 .slave = &dm814x_timer1_hwmod,
671 .user = OCP_USER_MPU,
674 static struct omap_hwmod dm816x_timer1_hwmod = {
676 .clkdm_name = "alwon_l3s_clkdm",
677 .main_clk = "timer1_fck",
680 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
681 .modulemode = MODULEMODE_SWCTRL,
684 .dev_attr = &capability_alwon_dev_attr,
685 .class = &dm816x_timer_hwmod_class,
688 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
689 .master = &dm81xx_l4_ls_hwmod,
690 .slave = &dm816x_timer1_hwmod,
692 .user = OCP_USER_MPU,
695 static struct omap_hwmod dm814x_timer2_hwmod = {
697 .clkdm_name = "alwon_l3s_clkdm",
698 .main_clk = "timer2_fck",
699 .dev_attr = &capability_alwon_dev_attr,
700 .class = &dm816x_timer_hwmod_class,
701 .flags = HWMOD_NO_IDLEST,
704 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
705 .master = &dm81xx_l4_ls_hwmod,
706 .slave = &dm814x_timer2_hwmod,
708 .user = OCP_USER_MPU,
711 static struct omap_hwmod dm816x_timer2_hwmod = {
713 .clkdm_name = "alwon_l3s_clkdm",
714 .main_clk = "timer2_fck",
717 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
718 .modulemode = MODULEMODE_SWCTRL,
721 .dev_attr = &capability_alwon_dev_attr,
722 .class = &dm816x_timer_hwmod_class,
725 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
726 .master = &dm81xx_l4_ls_hwmod,
727 .slave = &dm816x_timer2_hwmod,
729 .user = OCP_USER_MPU,
732 static struct omap_hwmod dm816x_timer3_hwmod = {
734 .clkdm_name = "alwon_l3s_clkdm",
735 .main_clk = "timer3_fck",
738 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
739 .modulemode = MODULEMODE_SWCTRL,
742 .dev_attr = &capability_alwon_dev_attr,
743 .class = &dm816x_timer_hwmod_class,
746 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
747 .master = &dm81xx_l4_ls_hwmod,
748 .slave = &dm816x_timer3_hwmod,
750 .user = OCP_USER_MPU,
753 static struct omap_hwmod dm816x_timer4_hwmod = {
755 .clkdm_name = "alwon_l3s_clkdm",
756 .main_clk = "timer4_fck",
759 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
760 .modulemode = MODULEMODE_SWCTRL,
763 .dev_attr = &capability_alwon_dev_attr,
764 .class = &dm816x_timer_hwmod_class,
767 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
768 .master = &dm81xx_l4_ls_hwmod,
769 .slave = &dm816x_timer4_hwmod,
771 .user = OCP_USER_MPU,
774 static struct omap_hwmod dm816x_timer5_hwmod = {
776 .clkdm_name = "alwon_l3s_clkdm",
777 .main_clk = "timer5_fck",
780 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
781 .modulemode = MODULEMODE_SWCTRL,
784 .dev_attr = &capability_alwon_dev_attr,
785 .class = &dm816x_timer_hwmod_class,
788 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
789 .master = &dm81xx_l4_ls_hwmod,
790 .slave = &dm816x_timer5_hwmod,
792 .user = OCP_USER_MPU,
795 static struct omap_hwmod dm816x_timer6_hwmod = {
797 .clkdm_name = "alwon_l3s_clkdm",
798 .main_clk = "timer6_fck",
801 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
802 .modulemode = MODULEMODE_SWCTRL,
805 .dev_attr = &capability_alwon_dev_attr,
806 .class = &dm816x_timer_hwmod_class,
809 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
810 .master = &dm81xx_l4_ls_hwmod,
811 .slave = &dm816x_timer6_hwmod,
813 .user = OCP_USER_MPU,
816 static struct omap_hwmod dm816x_timer7_hwmod = {
818 .clkdm_name = "alwon_l3s_clkdm",
819 .main_clk = "timer7_fck",
822 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
823 .modulemode = MODULEMODE_SWCTRL,
826 .dev_attr = &capability_alwon_dev_attr,
827 .class = &dm816x_timer_hwmod_class,
830 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
831 .master = &dm81xx_l4_ls_hwmod,
832 .slave = &dm816x_timer7_hwmod,
834 .user = OCP_USER_MPU,
838 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
842 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
843 SYSS_HAS_RESET_STATUS,
844 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
846 .sysc_fields = &omap_hwmod_sysc_type3,
849 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
851 .sysc = &dm814x_cpgmac_sysc,
854 static struct omap_hwmod dm814x_cpgmac0_hwmod = {
856 .class = &dm814x_cpgmac0_hwmod_class,
857 .clkdm_name = "alwon_ethernet_clkdm",
858 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
859 .main_clk = "cpsw_125mhz_gclk",
862 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
863 .modulemode = MODULEMODE_SWCTRL,
868 static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
869 .name = "davinci_mdio",
872 static struct omap_hwmod dm814x_mdio_hwmod = {
873 .name = "davinci_mdio",
874 .class = &dm814x_mdio_hwmod_class,
875 .clkdm_name = "alwon_ethernet_clkdm",
876 .main_clk = "cpsw_125mhz_gclk",
879 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
880 .master = &dm81xx_l4_hs_hwmod,
881 .slave = &dm814x_cpgmac0_hwmod,
882 .clk = "cpsw_125mhz_gclk",
883 .user = OCP_USER_MPU,
886 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
887 .master = &dm814x_cpgmac0_hwmod,
888 .slave = &dm814x_mdio_hwmod,
889 .user = OCP_USER_MPU,
890 .flags = HWMOD_NO_IDLEST,
894 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
897 .sysc_flags = SYSC_HAS_SOFTRESET,
898 .sysc_fields = &omap_hwmod_sysc_type2,
901 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
903 .sysc = &dm816x_emac_sysc,
907 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
908 * driver probed before EMAC0, we let MDIO do the clock idling.
910 static struct omap_hwmod dm816x_emac0_hwmod = {
912 .clkdm_name = "alwon_ethernet_clkdm",
913 .class = &dm816x_emac_hwmod_class,
914 .flags = HWMOD_NO_IDLEST,
917 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
918 .master = &dm81xx_l4_hs_hwmod,
919 .slave = &dm816x_emac0_hwmod,
921 .user = OCP_USER_MPU,
924 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
925 .name = "davinci_mdio",
926 .sysc = &dm816x_emac_sysc,
929 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
930 .name = "davinci_mdio",
931 .class = &dm81xx_mdio_hwmod_class,
932 .clkdm_name = "alwon_ethernet_clkdm",
933 .main_clk = "sysclk24_ck",
934 .flags = HWMOD_NO_IDLEST,
936 * REVISIT: This should be moved to the emac0_hwmod
937 * once we have a better way to handle device slaves.
941 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
942 .modulemode = MODULEMODE_SWCTRL,
947 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
948 .master = &dm81xx_l4_hs_hwmod,
949 .slave = &dm81xx_emac0_mdio_hwmod,
950 .user = OCP_USER_MPU,
953 static struct omap_hwmod dm816x_emac1_hwmod = {
955 .clkdm_name = "alwon_ethernet_clkdm",
956 .main_clk = "sysclk24_ck",
957 .flags = HWMOD_NO_IDLEST,
960 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
961 .modulemode = MODULEMODE_SWCTRL,
964 .class = &dm816x_emac_hwmod_class,
967 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
968 .master = &dm81xx_l4_hs_hwmod,
969 .slave = &dm816x_emac1_hwmod,
971 .user = OCP_USER_MPU,
974 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
978 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
979 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
980 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
981 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
982 .sysc_fields = &omap_hwmod_sysc_type1,
985 static struct omap_hwmod_class dm81xx_mmc_class = {
987 .sysc = &dm81xx_mmc_sysc,
990 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
991 { .role = "dbck", .clk = "sysclk18_ck", },
994 static struct omap_hsmmc_dev_attr mmc_dev_attr = {
997 static struct omap_hwmod dm814x_mmc1_hwmod = {
999 .clkdm_name = "alwon_l3s_clkdm",
1000 .opt_clks = dm81xx_mmc_opt_clks,
1001 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1002 .main_clk = "sysclk8_ck",
1005 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
1006 .modulemode = MODULEMODE_SWCTRL,
1009 .dev_attr = &mmc_dev_attr,
1010 .class = &dm81xx_mmc_class,
1013 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
1014 .master = &dm81xx_l4_ls_hwmod,
1015 .slave = &dm814x_mmc1_hwmod,
1016 .clk = "sysclk6_ck",
1017 .user = OCP_USER_MPU,
1018 .flags = OMAP_FIREWALL_L4
1021 static struct omap_hwmod dm814x_mmc2_hwmod = {
1023 .clkdm_name = "alwon_l3s_clkdm",
1024 .opt_clks = dm81xx_mmc_opt_clks,
1025 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1026 .main_clk = "sysclk8_ck",
1029 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
1030 .modulemode = MODULEMODE_SWCTRL,
1033 .dev_attr = &mmc_dev_attr,
1034 .class = &dm81xx_mmc_class,
1037 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
1038 .master = &dm81xx_l4_ls_hwmod,
1039 .slave = &dm814x_mmc2_hwmod,
1040 .clk = "sysclk6_ck",
1041 .user = OCP_USER_MPU,
1042 .flags = OMAP_FIREWALL_L4
1045 static struct omap_hwmod dm814x_mmc3_hwmod = {
1047 .clkdm_name = "alwon_l3_med_clkdm",
1048 .opt_clks = dm81xx_mmc_opt_clks,
1049 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1050 .main_clk = "sysclk8_ck",
1053 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
1054 .modulemode = MODULEMODE_SWCTRL,
1057 .dev_attr = &mmc_dev_attr,
1058 .class = &dm81xx_mmc_class,
1061 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
1062 .master = &dm81xx_alwon_l3_med_hwmod,
1063 .slave = &dm814x_mmc3_hwmod,
1064 .clk = "sysclk4_ck",
1065 .user = OCP_USER_MPU,
1068 static struct omap_hwmod dm816x_mmc1_hwmod = {
1070 .clkdm_name = "alwon_l3s_clkdm",
1071 .opt_clks = dm81xx_mmc_opt_clks,
1072 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1073 .main_clk = "sysclk10_ck",
1076 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
1077 .modulemode = MODULEMODE_SWCTRL,
1080 .dev_attr = &mmc_dev_attr,
1081 .class = &dm81xx_mmc_class,
1084 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
1085 .master = &dm81xx_l4_ls_hwmod,
1086 .slave = &dm816x_mmc1_hwmod,
1087 .clk = "sysclk6_ck",
1088 .user = OCP_USER_MPU,
1089 .flags = OMAP_FIREWALL_L4
1092 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
1096 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1097 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1098 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1099 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1100 .sysc_fields = &omap_hwmod_sysc_type1,
1103 static struct omap_hwmod_class dm816x_mcspi_class = {
1105 .sysc = &dm816x_mcspi_sysc,
1106 .rev = OMAP3_MCSPI_REV,
1109 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
1110 .num_chipselect = 4,
1113 static struct omap_hwmod dm81xx_mcspi1_hwmod = {
1115 .clkdm_name = "alwon_l3s_clkdm",
1116 .main_clk = "sysclk10_ck",
1119 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1120 .modulemode = MODULEMODE_SWCTRL,
1123 .class = &dm816x_mcspi_class,
1124 .dev_attr = &dm816x_mcspi1_dev_attr,
1127 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1128 .master = &dm81xx_l4_ls_hwmod,
1129 .slave = &dm81xx_mcspi1_hwmod,
1130 .clk = "sysclk6_ck",
1131 .user = OCP_USER_MPU,
1134 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
1138 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1139 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1140 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1141 .sysc_fields = &omap_hwmod_sysc_type1,
1144 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
1146 .sysc = &dm81xx_mailbox_sysc,
1149 static struct omap_hwmod dm81xx_mailbox_hwmod = {
1151 .clkdm_name = "alwon_l3s_clkdm",
1152 .class = &dm81xx_mailbox_hwmod_class,
1153 .main_clk = "sysclk6_ck",
1156 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
1157 .modulemode = MODULEMODE_SWCTRL,
1162 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1163 .master = &dm81xx_l4_ls_hwmod,
1164 .slave = &dm81xx_mailbox_hwmod,
1165 .clk = "sysclk6_ck",
1166 .user = OCP_USER_MPU,
1169 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
1173 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1174 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1175 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1176 .sysc_fields = &omap_hwmod_sysc_type1,
1179 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
1181 .sysc = &dm81xx_spinbox_sysc,
1184 static struct omap_hwmod dm81xx_spinbox_hwmod = {
1186 .clkdm_name = "alwon_l3s_clkdm",
1187 .class = &dm81xx_spinbox_hwmod_class,
1188 .main_clk = "sysclk6_ck",
1191 .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
1192 .modulemode = MODULEMODE_SWCTRL,
1197 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
1198 .master = &dm81xx_l4_ls_hwmod,
1199 .slave = &dm81xx_spinbox_hwmod,
1200 .clk = "sysclk6_ck",
1201 .user = OCP_USER_MPU,
1204 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
1208 static struct omap_hwmod dm81xx_tpcc_hwmod = {
1210 .class = &dm81xx_tpcc_hwmod_class,
1211 .clkdm_name = "alwon_l3s_clkdm",
1212 .main_clk = "sysclk4_ck",
1215 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
1216 .modulemode = MODULEMODE_SWCTRL,
1221 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
1222 .master = &dm81xx_alwon_l3_fast_hwmod,
1223 .slave = &dm81xx_tpcc_hwmod,
1224 .clk = "sysclk4_ck",
1225 .user = OCP_USER_MPU,
1228 static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = {
1230 .pa_start = 0x49800000,
1231 .pa_end = 0x49800000 + SZ_8K - 1,
1232 .flags = ADDR_TYPE_RT,
1237 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
1241 static struct omap_hwmod dm81xx_tptc0_hwmod = {
1243 .class = &dm81xx_tptc0_hwmod_class,
1244 .clkdm_name = "alwon_l3s_clkdm",
1245 .main_clk = "sysclk4_ck",
1248 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
1249 .modulemode = MODULEMODE_SWCTRL,
1254 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
1255 .master = &dm81xx_alwon_l3_fast_hwmod,
1256 .slave = &dm81xx_tptc0_hwmod,
1257 .clk = "sysclk4_ck",
1258 .addr = dm81xx_tptc0_addr_space,
1259 .user = OCP_USER_MPU,
1262 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
1263 .master = &dm81xx_tptc0_hwmod,
1264 .slave = &dm81xx_alwon_l3_fast_hwmod,
1265 .clk = "sysclk4_ck",
1266 .addr = dm81xx_tptc0_addr_space,
1267 .user = OCP_USER_MPU,
1270 static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = {
1272 .pa_start = 0x49900000,
1273 .pa_end = 0x49900000 + SZ_8K - 1,
1274 .flags = ADDR_TYPE_RT,
1279 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
1283 static struct omap_hwmod dm81xx_tptc1_hwmod = {
1285 .class = &dm81xx_tptc1_hwmod_class,
1286 .clkdm_name = "alwon_l3s_clkdm",
1287 .main_clk = "sysclk4_ck",
1290 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
1291 .modulemode = MODULEMODE_SWCTRL,
1296 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
1297 .master = &dm81xx_alwon_l3_fast_hwmod,
1298 .slave = &dm81xx_tptc1_hwmod,
1299 .clk = "sysclk4_ck",
1300 .addr = dm81xx_tptc1_addr_space,
1301 .user = OCP_USER_MPU,
1304 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1305 .master = &dm81xx_tptc1_hwmod,
1306 .slave = &dm81xx_alwon_l3_fast_hwmod,
1307 .clk = "sysclk4_ck",
1308 .addr = dm81xx_tptc1_addr_space,
1309 .user = OCP_USER_MPU,
1312 static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = {
1314 .pa_start = 0x49a00000,
1315 .pa_end = 0x49a00000 + SZ_8K - 1,
1316 .flags = ADDR_TYPE_RT,
1321 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1325 static struct omap_hwmod dm81xx_tptc2_hwmod = {
1327 .class = &dm81xx_tptc2_hwmod_class,
1328 .clkdm_name = "alwon_l3s_clkdm",
1329 .main_clk = "sysclk4_ck",
1332 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1333 .modulemode = MODULEMODE_SWCTRL,
1338 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1339 .master = &dm81xx_alwon_l3_fast_hwmod,
1340 .slave = &dm81xx_tptc2_hwmod,
1341 .clk = "sysclk4_ck",
1342 .addr = dm81xx_tptc2_addr_space,
1343 .user = OCP_USER_MPU,
1346 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1347 .master = &dm81xx_tptc2_hwmod,
1348 .slave = &dm81xx_alwon_l3_fast_hwmod,
1349 .clk = "sysclk4_ck",
1350 .addr = dm81xx_tptc2_addr_space,
1351 .user = OCP_USER_MPU,
1354 static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = {
1356 .pa_start = 0x49b00000,
1357 .pa_end = 0x49b00000 + SZ_8K - 1,
1358 .flags = ADDR_TYPE_RT,
1363 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1367 static struct omap_hwmod dm81xx_tptc3_hwmod = {
1369 .class = &dm81xx_tptc3_hwmod_class,
1370 .clkdm_name = "alwon_l3s_clkdm",
1371 .main_clk = "sysclk4_ck",
1374 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1375 .modulemode = MODULEMODE_SWCTRL,
1380 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1381 .master = &dm81xx_alwon_l3_fast_hwmod,
1382 .slave = &dm81xx_tptc3_hwmod,
1383 .clk = "sysclk4_ck",
1384 .addr = dm81xx_tptc3_addr_space,
1385 .user = OCP_USER_MPU,
1388 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1389 .master = &dm81xx_tptc3_hwmod,
1390 .slave = &dm81xx_alwon_l3_fast_hwmod,
1391 .clk = "sysclk4_ck",
1392 .addr = dm81xx_tptc3_addr_space,
1393 .user = OCP_USER_MPU,
1397 * REVISIT: Test and enable the following once clocks work:
1398 * dm81xx_l4_ls__mailbox
1400 * Also note that some devices share a single clkctrl_offs..
1401 * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1403 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1404 &dm814x_mpu__alwon_l3_slow,
1405 &dm814x_mpu__alwon_l3_med,
1406 &dm81xx_alwon_l3_slow__l4_ls,
1407 &dm81xx_alwon_l3_slow__l4_hs,
1408 &dm81xx_l4_ls__uart1,
1409 &dm81xx_l4_ls__uart2,
1410 &dm81xx_l4_ls__uart3,
1411 &dm81xx_l4_ls__wd_timer1,
1412 &dm81xx_l4_ls__i2c1,
1413 &dm81xx_l4_ls__i2c2,
1414 &dm81xx_l4_ls__gpio1,
1415 &dm81xx_l4_ls__gpio2,
1417 &dm81xx_l4_ls__mcspi1,
1418 &dm814x_l4_ls__mmc1,
1419 &dm814x_l4_ls__mmc2,
1421 &dm81xx_alwon_l3_fast__tpcc,
1422 &dm81xx_alwon_l3_fast__tptc0,
1423 &dm81xx_alwon_l3_fast__tptc1,
1424 &dm81xx_alwon_l3_fast__tptc2,
1425 &dm81xx_alwon_l3_fast__tptc3,
1426 &dm81xx_tptc0__alwon_l3_fast,
1427 &dm81xx_tptc1__alwon_l3_fast,
1428 &dm81xx_tptc2__alwon_l3_fast,
1429 &dm81xx_tptc3__alwon_l3_fast,
1430 &dm814x_l4_ls__timer1,
1431 &dm814x_l4_ls__timer2,
1432 &dm814x_l4_hs__cpgmac0,
1433 &dm814x_cpgmac0__mdio,
1434 &dm81xx_alwon_l3_slow__gpmc,
1435 &dm814x_default_l3_slow__usbss,
1436 &dm814x_alwon_l3_med__mmc3,
1440 int __init dm814x_hwmod_init(void)
1443 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1446 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1447 &dm816x_mpu__alwon_l3_slow,
1448 &dm816x_mpu__alwon_l3_med,
1449 &dm81xx_alwon_l3_slow__l4_ls,
1450 &dm81xx_alwon_l3_slow__l4_hs,
1451 &dm81xx_l4_ls__uart1,
1452 &dm81xx_l4_ls__uart2,
1453 &dm81xx_l4_ls__uart3,
1454 &dm81xx_l4_ls__wd_timer1,
1455 &dm81xx_l4_ls__i2c1,
1456 &dm81xx_l4_ls__i2c2,
1457 &dm81xx_l4_ls__gpio1,
1458 &dm81xx_l4_ls__gpio2,
1461 &dm816x_l4_ls__mmc1,
1462 &dm816x_l4_ls__timer1,
1463 &dm816x_l4_ls__timer2,
1464 &dm816x_l4_ls__timer3,
1465 &dm816x_l4_ls__timer4,
1466 &dm816x_l4_ls__timer5,
1467 &dm816x_l4_ls__timer6,
1468 &dm816x_l4_ls__timer7,
1469 &dm81xx_l4_ls__mcspi1,
1470 &dm81xx_l4_ls__mailbox,
1471 &dm81xx_l4_ls__spinbox,
1472 &dm81xx_l4_hs__emac0,
1473 &dm81xx_emac0__mdio,
1474 &dm816x_l4_hs__emac1,
1475 &dm81xx_alwon_l3_fast__tpcc,
1476 &dm81xx_alwon_l3_fast__tptc0,
1477 &dm81xx_alwon_l3_fast__tptc1,
1478 &dm81xx_alwon_l3_fast__tptc2,
1479 &dm81xx_alwon_l3_fast__tptc3,
1480 &dm81xx_tptc0__alwon_l3_fast,
1481 &dm81xx_tptc1__alwon_l3_fast,
1482 &dm81xx_tptc2__alwon_l3_fast,
1483 &dm81xx_tptc3__alwon_l3_fast,
1484 &dm81xx_alwon_l3_slow__gpmc,
1485 &dm816x_default_l3_slow__usbss,
1489 int __init dm816x_hwmod_init(void)
1492 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);