arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_7xx.h"
  34 #include "cm2_7xx.h"
  35 #include "prm7xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "soc.h"
  39
  40 /* Base offset for all DRA7XX interrupts external to MPUSS */
  41 #define DRA7XX_IRQ_GIC_START    32
  42
  43 /* Base offset for all DRA7XX dma requests */
  44 #define DRA7XX_DMA_REQ_START    1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'dmm' class
  53  * instance(s): dmm
  54  */
  55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  56         .name   = "dmm",
  57 };
  58
  59 /* dmm */
  60 static struct omap_hwmod dra7xx_dmm_hwmod = {
  61         .name           = "dmm",
  62         .class          = &dra7xx_dmm_hwmod_class,
  63         .clkdm_name     = "emif_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  67                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'l3' class
  74  * instance(s): l3_instr, l3_main_1, l3_main_2
  75  */
  76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  77         .name   = "l3",
  78 };
  79
  80 /* l3_instr */
  81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  82         .name           = "l3_instr",
  83         .class          = &dra7xx_l3_hwmod_class,
  84         .clkdm_name     = "l3instr_clkdm",
  85         .prcm = {
  86                 .omap4 = {
  87                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  88                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  89                         .modulemode   = MODULEMODE_HWCTRL,
  90                 },
  91         },
  92 };
  93
  94 /* l3_main_1 */
  95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  96         .name           = "l3_main_1",
  97         .class          = &dra7xx_l3_hwmod_class,
  98         .clkdm_name     = "l3main1_clkdm",
  99         .prcm = {
 100                 .omap4 = {
 101                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 102                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 103                 },
 104         },
 105 };
 106
 107 /* l3_main_2 */
 108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
 109         .name           = "l3_main_2",
 110         .class          = &dra7xx_l3_hwmod_class,
 111         .clkdm_name     = "l3instr_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
 115                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
 116                         .modulemode   = MODULEMODE_HWCTRL,
 117                 },
 118         },
 119 };
 120
 121 /*
 122  * 'l4' class
 123  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 124  */
 125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 126         .name   = "l4",
 127 };
 128
 129 /* l4_cfg */
 130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 131         .name           = "l4_cfg",
 132         .class          = &dra7xx_l4_hwmod_class,
 133         .clkdm_name     = "l4cfg_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 137                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 138                 },
 139         },
 140 };
 141
 142 /* l4_per1 */
 143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 144         .name           = "l4_per1",
 145         .class          = &dra7xx_l4_hwmod_class,
 146         .clkdm_name     = "l4per_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 150                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 151                 },
 152         },
 153 };
 154
 155 /* l4_per2 */
 156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 157         .name           = "l4_per2",
 158         .class          = &dra7xx_l4_hwmod_class,
 159         .clkdm_name     = "l4per2_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 163                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 164                 },
 165         },
 166 };
 167
 168 /* l4_per3 */
 169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 170         .name           = "l4_per3",
 171         .class          = &dra7xx_l4_hwmod_class,
 172         .clkdm_name     = "l4per3_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 176                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 177                 },
 178         },
 179 };
 180
 181 /* l4_wkup */
 182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 183         .name           = "l4_wkup",
 184         .class          = &dra7xx_l4_hwmod_class,
 185         .clkdm_name     = "wkupaon_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 189                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 190                 },
 191         },
 192 };
 193
 194 /*
 195  * 'atl' class
 196  *
 197  */
 198
 199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 200         .name   = "atl",
 201 };
 202
 203 /* atl */
 204 static struct omap_hwmod dra7xx_atl_hwmod = {
 205         .name           = "atl",
 206         .class          = &dra7xx_atl_hwmod_class,
 207         .clkdm_name     = "atl_clkdm",
 208         .main_clk       = "atl_gfclk_mux",
 209         .prcm = {
 210                 .omap4 = {
 211                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 212                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 213                         .modulemode   = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 /*
 219  * 'bb2d' class
 220  *
 221  */
 222
 223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 224         .name   = "bb2d",
 225 };
 226
 227 /* bb2d */
 228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 229         .name           = "bb2d",
 230         .class          = &dra7xx_bb2d_hwmod_class,
 231         .clkdm_name     = "dss_clkdm",
 232         .main_clk       = "dpll_core_h24x2_ck",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 236                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 237                         .modulemode   = MODULEMODE_SWCTRL,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * 'counter' class
 244  *
 245  */
 246
 247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 248         .rev_offs       = 0x0000,
 249         .sysc_offs      = 0x0010,
 250         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 251         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 252                            SIDLE_SMART_WKUP),
 253         .sysc_fields    = &omap_hwmod_sysc_type1,
 254 };
 255
 256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 257         .name   = "counter",
 258         .sysc   = &dra7xx_counter_sysc,
 259 };
 260
 261 /* counter_32k */
 262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 263         .name           = "counter_32k",
 264         .class          = &dra7xx_counter_hwmod_class,
 265         .clkdm_name     = "wkupaon_clkdm",
 266         .flags          = HWMOD_SWSUP_SIDLE,
 267         .main_clk       = "wkupaon_iclk_mux",
 268         .prcm = {
 269                 .omap4 = {
 270                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 271                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'ctrl_module' class
 278  *
 279  */
 280
 281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 282         .name   = "ctrl_module",
 283 };
 284
 285 /* ctrl_module_wkup */
 286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 287         .name           = "ctrl_module_wkup",
 288         .class          = &dra7xx_ctrl_module_hwmod_class,
 289         .clkdm_name     = "wkupaon_clkdm",
 290         .prcm = {
 291                 .omap4 = {
 292                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 293                 },
 294         },
 295 };
 296
 297 /*
 298  * 'gmac' class
 299  * cpsw/gmac sub system
 300  */
 301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 302         .rev_offs       = 0x0,
 303         .sysc_offs      = 0x8,
 304         .syss_offs      = 0x4,
 305         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 306                            SYSS_HAS_RESET_STATUS),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 308                            MSTANDBY_NO),
 309         .sysc_fields    = &omap_hwmod_sysc_type3,
 310 };
 311
 312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 313         .name           = "gmac",
 314         .sysc           = &dra7xx_gmac_sysc,
 315 };
 316
 317 static struct omap_hwmod dra7xx_gmac_hwmod = {
 318         .name           = "gmac",
 319         .class          = &dra7xx_gmac_hwmod_class,
 320         .clkdm_name     = "gmac_clkdm",
 321         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 322         .main_clk       = "dpll_gmac_ck",
 323         .mpu_rt_idx     = 1,
 324         .prcm           = {
 325                 .omap4  = {
 326                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 327                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 328                         .modulemode     = MODULEMODE_SWCTRL,
 329                 },
 330         },
 331 };
 332
 333 /*
 334  * 'mdio' class
 335  */
 336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 337         .name           = "davinci_mdio",
 338 };
 339
 340 static struct omap_hwmod dra7xx_mdio_hwmod = {
 341         .name           = "davinci_mdio",
 342         .class          = &dra7xx_mdio_hwmod_class,
 343         .clkdm_name     = "gmac_clkdm",
 344         .main_clk       = "dpll_gmac_ck",
 345 };
 346
 347 /*
 348  * 'dcan' class
 349  *
 350  */
 351
 352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 353         .name   = "dcan",
 354 };
 355
 356 /* dcan1 */
 357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 358         .name           = "dcan1",
 359         .class          = &dra7xx_dcan_hwmod_class,
 360         .clkdm_name     = "wkupaon_clkdm",
 361         .main_clk       = "dcan1_sys_clk_mux",
 362         .prcm = {
 363                 .omap4 = {
 364                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 365                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 366                         .modulemode   = MODULEMODE_SWCTRL,
 367                 },
 368         },
 369 };
 370
 371 /* dcan2 */
 372 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 373         .name           = "dcan2",
 374         .class          = &dra7xx_dcan_hwmod_class,
 375         .clkdm_name     = "l4per2_clkdm",
 376         .main_clk       = "sys_clkin1",
 377         .prcm = {
 378                 .omap4 = {
 379                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 380                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 381                         .modulemode   = MODULEMODE_SWCTRL,
 382                 },
 383         },
 384 };
 385
 386 /* pwmss  */
 387 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
 388         .rev_offs       = 0x0,
 389         .sysc_offs      = 0x4,
 390         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
 391         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 392         .sysc_fields    = &omap_hwmod_sysc_type2,
 393 };
 394
 395 /*
 396  * epwmss class
 397  */
 398 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
 399         .name           = "epwmss",
 400         .sysc           = &dra7xx_epwmss_sysc,
 401 };
 402
 403 /* epwmss0 */
 404 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
 405         .name           = "epwmss0",
 406         .class          = &dra7xx_epwmss_hwmod_class,
 407         .clkdm_name     = "l4per2_clkdm",
 408         .main_clk       = "l4_root_clk_div",
 409         .prcm           = {
 410                 .omap4  = {
 411                         .modulemode     = MODULEMODE_SWCTRL,
 412                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
 413                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
 414                 },
 415         },
 416 };
 417
 418 /* epwmss1 */
 419 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
 420         .name           = "epwmss1",
 421         .class          = &dra7xx_epwmss_hwmod_class,
 422         .clkdm_name     = "l4per2_clkdm",
 423         .main_clk       = "l4_root_clk_div",
 424         .prcm           = {
 425                 .omap4  = {
 426                         .modulemode     = MODULEMODE_SWCTRL,
 427                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
 428                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
 429                 },
 430         },
 431 };
 432
 433 /* epwmss2 */
 434 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
 435         .name           = "epwmss2",
 436         .class          = &dra7xx_epwmss_hwmod_class,
 437         .clkdm_name     = "l4per2_clkdm",
 438         .main_clk       = "l4_root_clk_div",
 439         .prcm           = {
 440                 .omap4  = {
 441                         .modulemode     = MODULEMODE_SWCTRL,
 442                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
 443                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
 444                 },
 445         },
 446 };
 447
 448 /*
 449  * 'dma' class
 450  *
 451  */
 452
 453 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 454         .rev_offs       = 0x0000,
 455         .sysc_offs      = 0x002c,
 456         .syss_offs      = 0x0028,
 457         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 458                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 459                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 460                            SYSS_HAS_RESET_STATUS),
 461         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 462                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 463                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 464         .sysc_fields    = &omap_hwmod_sysc_type1,
 465 };
 466
 467 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 468         .name   = "dma",
 469         .sysc   = &dra7xx_dma_sysc,
 470 };
 471
 472 /* dma dev_attr */
 473 static struct omap_dma_dev_attr dma_dev_attr = {
 474         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 475                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 476         .lch_count      = 32,
 477 };
 478
 479 /* dma_system */
 480 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 481         .name           = "dma_system",
 482         .class          = &dra7xx_dma_hwmod_class,
 483         .clkdm_name     = "dma_clkdm",
 484         .main_clk       = "l3_iclk_div",
 485         .prcm = {
 486                 .omap4 = {
 487                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 488                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 489                 },
 490         },
 491         .dev_attr       = &dma_dev_attr,
 492 };
 493
 494 /*
 495  * 'tpcc' class
 496  *
 497  */
 498 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
 499         .name           = "tpcc",
 500 };
 501
 502 static struct omap_hwmod dra7xx_tpcc_hwmod = {
 503         .name           = "tpcc",
 504         .class          = &dra7xx_tpcc_hwmod_class,
 505         .clkdm_name     = "l3main1_clkdm",
 506         .main_clk       = "l3_iclk_div",
 507         .prcm           = {
 508                 .omap4  = {
 509                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
 510                         .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
 511                 },
 512         },
 513 };
 514
 515 /*
 516  * 'tptc' class
 517  *
 518  */
 519 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
 520         .name           = "tptc",
 521 };
 522
 523 /* tptc0 */
 524 static struct omap_hwmod dra7xx_tptc0_hwmod = {
 525         .name           = "tptc0",
 526         .class          = &dra7xx_tptc_hwmod_class,
 527         .clkdm_name     = "l3main1_clkdm",
 528         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 529         .main_clk       = "l3_iclk_div",
 530         .prcm           = {
 531                 .omap4  = {
 532                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
 533                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
 534                         .modulemode   = MODULEMODE_HWCTRL,
 535                 },
 536         },
 537 };
 538
 539 /* tptc1 */
 540 static struct omap_hwmod dra7xx_tptc1_hwmod = {
 541         .name           = "tptc1",
 542         .class          = &dra7xx_tptc_hwmod_class,
 543         .clkdm_name     = "l3main1_clkdm",
 544         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 545         .main_clk       = "l3_iclk_div",
 546         .prcm           = {
 547                 .omap4  = {
 548                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
 549                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
 550                         .modulemode   = MODULEMODE_HWCTRL,
 551                 },
 552         },
 553 };
 554
 555 /*
 556  * 'dss' class
 557  *
 558  */
 559
 560 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 561         .rev_offs       = 0x0000,
 562         .syss_offs      = 0x0014,
 563         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 564 };
 565
 566 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 567         .name   = "dss",
 568         .sysc   = &dra7xx_dss_sysc,
 569         .reset  = omap_dss_reset,
 570 };
 571
 572 /* dss */
 573 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
 574         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
 575         { .dma_req = -1 }
 576 };
 577
 578 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 579         { .role = "dss_clk", .clk = "dss_dss_clk" },
 580         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 581         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 582         { .role = "video2_clk", .clk = "dss_video2_clk" },
 583         { .role = "video1_clk", .clk = "dss_video1_clk" },
 584         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 585         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 586 };
 587
 588 static struct omap_hwmod dra7xx_dss_hwmod = {
 589         .name           = "dss_core",
 590         .class          = &dra7xx_dss_hwmod_class,
 591         .clkdm_name     = "dss_clkdm",
 592         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 593         .sdma_reqs      = dra7xx_dss_sdma_reqs,
 594         .main_clk       = "dss_dss_clk",
 595         .prcm = {
 596                 .omap4 = {
 597                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 598                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 599                         .modulemode   = MODULEMODE_SWCTRL,
 600                 },
 601         },
 602         .opt_clks       = dss_opt_clks,
 603         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 604 };
 605
 606 /*
 607  * 'dispc' class
 608  * display controller
 609  */
 610
 611 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 612         .rev_offs       = 0x0000,
 613         .sysc_offs      = 0x0010,
 614         .syss_offs      = 0x0014,
 615         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 616                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 617                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 618                            SYSS_HAS_RESET_STATUS),
 619         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 620                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 621         .sysc_fields    = &omap_hwmod_sysc_type1,
 622 };
 623
 624 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 625         .name   = "dispc",
 626         .sysc   = &dra7xx_dispc_sysc,
 627 };
 628
 629 /* dss_dispc */
 630 /* dss_dispc dev_attr */
 631 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 632         .has_framedonetv_irq    = 1,
 633         .manager_count          = 4,
 634 };
 635
 636 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 637         .name           = "dss_dispc",
 638         .class          = &dra7xx_dispc_hwmod_class,
 639         .clkdm_name     = "dss_clkdm",
 640         .main_clk       = "dss_dss_clk",
 641         .prcm = {
 642                 .omap4 = {
 643                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 644                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 645                 },
 646         },
 647         .dev_attr       = &dss_dispc_dev_attr,
 648         .parent_hwmod   = &dra7xx_dss_hwmod,
 649 };
 650
 651 /*
 652  * 'hdmi' class
 653  * hdmi controller
 654  */
 655
 656 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 657         .rev_offs       = 0x0000,
 658         .sysc_offs      = 0x0010,
 659         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 660                            SYSC_HAS_SOFTRESET),
 661         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 662                            SIDLE_SMART_WKUP),
 663         .sysc_fields    = &omap_hwmod_sysc_type2,
 664 };
 665
 666 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 667         .name   = "hdmi",
 668         .sysc   = &dra7xx_hdmi_sysc,
 669 };
 670
 671 /* dss_hdmi */
 672
 673 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 674         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 675 };
 676
 677 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 678         .name           = "dss_hdmi",
 679         .class          = &dra7xx_hdmi_hwmod_class,
 680         .clkdm_name     = "dss_clkdm",
 681         .main_clk       = "dss_48mhz_clk",
 682         .prcm = {
 683                 .omap4 = {
 684                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 685                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 686                 },
 687         },
 688         .opt_clks       = dss_hdmi_opt_clks,
 689         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 690         .parent_hwmod   = &dra7xx_dss_hwmod,
 691 };
 692
 693 /* AES (the 'P' (public) device) */
 694 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
 695         .rev_offs       = 0x0080,
 696         .sysc_offs      = 0x0084,
 697         .syss_offs      = 0x0088,
 698         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 699 };
 700
 701 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
 702         .name   = "aes",
 703         .sysc   = &dra7xx_aes_sysc,
 704         .rev    = 2,
 705 };
 706
 707 /* AES1 */
 708 static struct omap_hwmod dra7xx_aes1_hwmod = {
 709         .name           = "aes1",
 710         .class          = &dra7xx_aes_hwmod_class,
 711         .clkdm_name     = "l4sec_clkdm",
 712         .main_clk       = "l3_iclk_div",
 713         .prcm = {
 714                 .omap4 = {
 715                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 716                         .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
 717                         .modulemode   = MODULEMODE_HWCTRL,
 718                 },
 719         },
 720 };
 721
 722 /* AES2 */
 723 static struct omap_hwmod dra7xx_aes2_hwmod = {
 724         .name           = "aes2",
 725         .class          = &dra7xx_aes_hwmod_class,
 726         .clkdm_name     = "l4sec_clkdm",
 727         .main_clk       = "l3_iclk_div",
 728         .prcm = {
 729                 .omap4 = {
 730                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 731                         .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
 732                         .modulemode   = MODULEMODE_HWCTRL,
 733                 },
 734         },
 735 };
 736
 737 /* sha0 HIB2 (the 'P' (public) device) */
 738 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
 739         .rev_offs       = 0x100,
 740         .sysc_offs      = 0x110,
 741         .syss_offs      = 0x114,
 742         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 743 };
 744
 745 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
 746         .name           = "sham",
 747         .sysc           = &dra7xx_sha0_sysc,
 748         .rev            = 2,
 749 };
 750
 751 struct omap_hwmod dra7xx_sha0_hwmod = {
 752         .name           = "sham",
 753         .class          = &dra7xx_sha0_hwmod_class,
 754         .clkdm_name     = "l4sec_clkdm",
 755         .main_clk       = "l3_iclk_div",
 756         .prcm           = {
 757                 .omap4 = {
 758                         .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 759                         .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 760                         .modulemode   = MODULEMODE_HWCTRL,
 761                 },
 762         },
 763 };
 764
 765 /*
 766  * 'elm' class
 767  *
 768  */
 769
 770 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 771         .rev_offs       = 0x0000,
 772         .sysc_offs      = 0x0010,
 773         .syss_offs      = 0x0014,
 774         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 775                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 776                            SYSS_HAS_RESET_STATUS),
 777         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 778                            SIDLE_SMART_WKUP),
 779         .sysc_fields    = &omap_hwmod_sysc_type1,
 780 };
 781
 782 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 783         .name   = "elm",
 784         .sysc   = &dra7xx_elm_sysc,
 785 };
 786
 787 /* elm */
 788
 789 static struct omap_hwmod dra7xx_elm_hwmod = {
 790         .name           = "elm",
 791         .class          = &dra7xx_elm_hwmod_class,
 792         .clkdm_name     = "l4per_clkdm",
 793         .main_clk       = "l3_iclk_div",
 794         .prcm = {
 795                 .omap4 = {
 796                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 797                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 798                 },
 799         },
 800 };
 801
 802 /*
 803  * 'gpio' class
 804  *
 805  */
 806
 807 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 808         .rev_offs       = 0x0000,
 809         .sysc_offs      = 0x0010,
 810         .syss_offs      = 0x0114,
 811         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 812                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 813                            SYSS_HAS_RESET_STATUS),
 814         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 815                            SIDLE_SMART_WKUP),
 816         .sysc_fields    = &omap_hwmod_sysc_type1,
 817 };
 818
 819 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 820         .name   = "gpio",
 821         .sysc   = &dra7xx_gpio_sysc,
 822         .rev    = 2,
 823 };
 824
 825 /* gpio dev_attr */
 826 static struct omap_gpio_dev_attr gpio_dev_attr = {
 827         .bank_width     = 32,
 828         .dbck_flag      = true,
 829 };
 830
 831 /* gpio1 */
 832 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 833         { .role = "dbclk", .clk = "gpio1_dbclk" },
 834 };
 835
 836 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 837         .name           = "gpio1",
 838         .class          = &dra7xx_gpio_hwmod_class,
 839         .clkdm_name     = "wkupaon_clkdm",
 840         .main_clk       = "wkupaon_iclk_mux",
 841         .prcm = {
 842                 .omap4 = {
 843                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 844                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 845                         .modulemode   = MODULEMODE_HWCTRL,
 846                 },
 847         },
 848         .opt_clks       = gpio1_opt_clks,
 849         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 850         .dev_attr       = &gpio_dev_attr,
 851 };
 852
 853 /* gpio2 */
 854 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 855         { .role = "dbclk", .clk = "gpio2_dbclk" },
 856 };
 857
 858 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 859         .name           = "gpio2",
 860         .class          = &dra7xx_gpio_hwmod_class,
 861         .clkdm_name     = "l4per_clkdm",
 862         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 863         .main_clk       = "l3_iclk_div",
 864         .prcm = {
 865                 .omap4 = {
 866                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 867                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 868                         .modulemode   = MODULEMODE_HWCTRL,
 869                 },
 870         },
 871         .opt_clks       = gpio2_opt_clks,
 872         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 873         .dev_attr       = &gpio_dev_attr,
 874 };
 875
 876 /* gpio3 */
 877 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 878         { .role = "dbclk", .clk = "gpio3_dbclk" },
 879 };
 880
 881 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 882         .name           = "gpio3",
 883         .class          = &dra7xx_gpio_hwmod_class,
 884         .clkdm_name     = "l4per_clkdm",
 885         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 886         .main_clk       = "l3_iclk_div",
 887         .prcm = {
 888                 .omap4 = {
 889                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 890                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 891                         .modulemode   = MODULEMODE_HWCTRL,
 892                 },
 893         },
 894         .opt_clks       = gpio3_opt_clks,
 895         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 896         .dev_attr       = &gpio_dev_attr,
 897 };
 898
 899 /* gpio4 */
 900 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 901         { .role = "dbclk", .clk = "gpio4_dbclk" },
 902 };
 903
 904 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 905         .name           = "gpio4",
 906         .class          = &dra7xx_gpio_hwmod_class,
 907         .clkdm_name     = "l4per_clkdm",
 908         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 909         .main_clk       = "l3_iclk_div",
 910         .prcm = {
 911                 .omap4 = {
 912                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 913                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 914                         .modulemode   = MODULEMODE_HWCTRL,
 915                 },
 916         },
 917         .opt_clks       = gpio4_opt_clks,
 918         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 919         .dev_attr       = &gpio_dev_attr,
 920 };
 921
 922 /* gpio5 */
 923 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 924         { .role = "dbclk", .clk = "gpio5_dbclk" },
 925 };
 926
 927 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 928         .name           = "gpio5",
 929         .class          = &dra7xx_gpio_hwmod_class,
 930         .clkdm_name     = "l4per_clkdm",
 931         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 932         .main_clk       = "l3_iclk_div",
 933         .prcm = {
 934                 .omap4 = {
 935                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 936                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 937                         .modulemode   = MODULEMODE_HWCTRL,
 938                 },
 939         },
 940         .opt_clks       = gpio5_opt_clks,
 941         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 942         .dev_attr       = &gpio_dev_attr,
 943 };
 944
 945 /* gpio6 */
 946 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 947         { .role = "dbclk", .clk = "gpio6_dbclk" },
 948 };
 949
 950 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 951         .name           = "gpio6",
 952         .class          = &dra7xx_gpio_hwmod_class,
 953         .clkdm_name     = "l4per_clkdm",
 954         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 955         .main_clk       = "l3_iclk_div",
 956         .prcm = {
 957                 .omap4 = {
 958                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 959                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 960                         .modulemode   = MODULEMODE_HWCTRL,
 961                 },
 962         },
 963         .opt_clks       = gpio6_opt_clks,
 964         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 965         .dev_attr       = &gpio_dev_attr,
 966 };
 967
 968 /* gpio7 */
 969 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 970         { .role = "dbclk", .clk = "gpio7_dbclk" },
 971 };
 972
 973 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 974         .name           = "gpio7",
 975         .class          = &dra7xx_gpio_hwmod_class,
 976         .clkdm_name     = "l4per_clkdm",
 977         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 978         .main_clk       = "l3_iclk_div",
 979         .prcm = {
 980                 .omap4 = {
 981                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 982                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 983                         .modulemode   = MODULEMODE_HWCTRL,
 984                 },
 985         },
 986         .opt_clks       = gpio7_opt_clks,
 987         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 988         .dev_attr       = &gpio_dev_attr,
 989 };
 990
 991 /* gpio8 */
 992 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 993         { .role = "dbclk", .clk = "gpio8_dbclk" },
 994 };
 995
 996 static struct omap_hwmod dra7xx_gpio8_hwmod = {
 997         .name           = "gpio8",
 998         .class          = &dra7xx_gpio_hwmod_class,
 999         .clkdm_name     = "l4per_clkdm",
1000         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1001         .main_clk       = "l3_iclk_div",
1002         .prcm = {
1003                 .omap4 = {
1004                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1005                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1006                         .modulemode   = MODULEMODE_HWCTRL,
1007                 },
1008         },
1009         .opt_clks       = gpio8_opt_clks,
1010         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
1011         .dev_attr       = &gpio_dev_attr,
1012 };
1013
1014 /*
1015  * 'gpmc' class
1016  *
1017  */
1018
1019 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1020         .rev_offs       = 0x0000,
1021         .sysc_offs      = 0x0010,
1022         .syss_offs      = 0x0014,
1023         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1024                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1025         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1026         .sysc_fields    = &omap_hwmod_sysc_type1,
1027 };
1028
1029 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1030         .name   = "gpmc",
1031         .sysc   = &dra7xx_gpmc_sysc,
1032 };
1033
1034 /* gpmc */
1035
1036 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1037         .name           = "gpmc",
1038         .class          = &dra7xx_gpmc_hwmod_class,
1039         .clkdm_name     = "l3main1_clkdm",
1040         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1041         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1042         .main_clk       = "l3_iclk_div",
1043         .prcm = {
1044                 .omap4 = {
1045                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1046                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1047                         .modulemode   = MODULEMODE_HWCTRL,
1048                 },
1049         },
1050 };
1051
1052 /*
1053  * 'hdq1w' class
1054  *
1055  */
1056
1057 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1058         .rev_offs       = 0x0000,
1059         .sysc_offs      = 0x0014,
1060         .syss_offs      = 0x0018,
1061         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1062                            SYSS_HAS_RESET_STATUS),
1063         .sysc_fields    = &omap_hwmod_sysc_type1,
1064 };
1065
1066 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1067         .name   = "hdq1w",
1068         .sysc   = &dra7xx_hdq1w_sysc,
1069 };
1070
1071 /* hdq1w */
1072
1073 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1074         .name           = "hdq1w",
1075         .class          = &dra7xx_hdq1w_hwmod_class,
1076         .clkdm_name     = "l4per_clkdm",
1077         .flags          = HWMOD_INIT_NO_RESET,
1078         .main_clk       = "func_12m_fclk",
1079         .prcm = {
1080                 .omap4 = {
1081                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1082                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1083                         .modulemode   = MODULEMODE_SWCTRL,
1084                 },
1085         },
1086 };
1087
1088 /*
1089  * 'i2c' class
1090  *
1091  */
1092
1093 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1094         .sysc_offs      = 0x0010,
1095         .syss_offs      = 0x0090,
1096         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1097                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1098                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1099         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1100                            SIDLE_SMART_WKUP),
1101         .sysc_fields    = &omap_hwmod_sysc_type1,
1102 };
1103
1104 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1105         .name   = "i2c",
1106         .sysc   = &dra7xx_i2c_sysc,
1107         .reset  = &omap_i2c_reset,
1108         .rev    = OMAP_I2C_IP_VERSION_2,
1109 };
1110
1111 /* i2c dev_attr */
1112 static struct omap_i2c_dev_attr i2c_dev_attr = {
1113         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1114 };
1115
1116 /* i2c1 */
1117 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1118         .name           = "i2c1",
1119         .class          = &dra7xx_i2c_hwmod_class,
1120         .clkdm_name     = "l4per_clkdm",
1121         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1122         .main_clk       = "func_96m_fclk",
1123         .prcm = {
1124                 .omap4 = {
1125                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1126                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1127                         .modulemode   = MODULEMODE_SWCTRL,
1128                 },
1129         },
1130         .dev_attr       = &i2c_dev_attr,
1131 };
1132
1133 /* i2c2 */
1134 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1135         .name           = "i2c2",
1136         .class          = &dra7xx_i2c_hwmod_class,
1137         .clkdm_name     = "l4per_clkdm",
1138         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1139         .main_clk       = "func_96m_fclk",
1140         .prcm = {
1141                 .omap4 = {
1142                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1143                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1144                         .modulemode   = MODULEMODE_SWCTRL,
1145                 },
1146         },
1147         .dev_attr       = &i2c_dev_attr,
1148 };
1149
1150 /* i2c3 */
1151 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1152         .name           = "i2c3",
1153         .class          = &dra7xx_i2c_hwmod_class,
1154         .clkdm_name     = "l4per_clkdm",
1155         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1156         .main_clk       = "func_96m_fclk",
1157         .prcm = {
1158                 .omap4 = {
1159                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1160                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1161                         .modulemode   = MODULEMODE_SWCTRL,
1162                 },
1163         },
1164         .dev_attr       = &i2c_dev_attr,
1165 };
1166
1167 /* i2c4 */
1168 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1169         .name           = "i2c4",
1170         .class          = &dra7xx_i2c_hwmod_class,
1171         .clkdm_name     = "l4per_clkdm",
1172         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1173         .main_clk       = "func_96m_fclk",
1174         .prcm = {
1175                 .omap4 = {
1176                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1177                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1178                         .modulemode   = MODULEMODE_SWCTRL,
1179                 },
1180         },
1181         .dev_attr       = &i2c_dev_attr,
1182 };
1183
1184 /* i2c5 */
1185 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1186         .name           = "i2c5",
1187         .class          = &dra7xx_i2c_hwmod_class,
1188         .clkdm_name     = "ipu_clkdm",
1189         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1190         .main_clk       = "func_96m_fclk",
1191         .prcm = {
1192                 .omap4 = {
1193                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1194                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1195                         .modulemode   = MODULEMODE_SWCTRL,
1196                 },
1197         },
1198         .dev_attr       = &i2c_dev_attr,
1199 };
1200
1201 /*
1202  * 'mailbox' class
1203  *
1204  */
1205
1206 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1207         .rev_offs       = 0x0000,
1208         .sysc_offs      = 0x0010,
1209         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1210                            SYSC_HAS_SOFTRESET),
1211         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1212         .sysc_fields    = &omap_hwmod_sysc_type2,
1213 };
1214
1215 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1216         .name   = "mailbox",
1217         .sysc   = &dra7xx_mailbox_sysc,
1218 };
1219
1220 /* mailbox1 */
1221 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1222         .name           = "mailbox1",
1223         .class          = &dra7xx_mailbox_hwmod_class,
1224         .clkdm_name     = "l4cfg_clkdm",
1225         .prcm = {
1226                 .omap4 = {
1227                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1228                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1229                 },
1230         },
1231 };
1232
1233 /* mailbox2 */
1234 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1235         .name           = "mailbox2",
1236         .class          = &dra7xx_mailbox_hwmod_class,
1237         .clkdm_name     = "l4cfg_clkdm",
1238         .prcm = {
1239                 .omap4 = {
1240                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1241                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1242                 },
1243         },
1244 };
1245
1246 /* mailbox3 */
1247 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1248         .name           = "mailbox3",
1249         .class          = &dra7xx_mailbox_hwmod_class,
1250         .clkdm_name     = "l4cfg_clkdm",
1251         .prcm = {
1252                 .omap4 = {
1253                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1254                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1255                 },
1256         },
1257 };
1258
1259 /* mailbox4 */
1260 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1261         .name           = "mailbox4",
1262         .class          = &dra7xx_mailbox_hwmod_class,
1263         .clkdm_name     = "l4cfg_clkdm",
1264         .prcm = {
1265                 .omap4 = {
1266                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1267                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1268                 },
1269         },
1270 };
1271
1272 /* mailbox5 */
1273 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1274         .name           = "mailbox5",
1275         .class          = &dra7xx_mailbox_hwmod_class,
1276         .clkdm_name     = "l4cfg_clkdm",
1277         .prcm = {
1278                 .omap4 = {
1279                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1280                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1281                 },
1282         },
1283 };
1284
1285 /* mailbox6 */
1286 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1287         .name           = "mailbox6",
1288         .class          = &dra7xx_mailbox_hwmod_class,
1289         .clkdm_name     = "l4cfg_clkdm",
1290         .prcm = {
1291                 .omap4 = {
1292                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1293                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1294                 },
1295         },
1296 };
1297
1298 /* mailbox7 */
1299 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1300         .name           = "mailbox7",
1301         .class          = &dra7xx_mailbox_hwmod_class,
1302         .clkdm_name     = "l4cfg_clkdm",
1303         .prcm = {
1304                 .omap4 = {
1305                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1306                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1307                 },
1308         },
1309 };
1310
1311 /* mailbox8 */
1312 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1313         .name           = "mailbox8",
1314         .class          = &dra7xx_mailbox_hwmod_class,
1315         .clkdm_name     = "l4cfg_clkdm",
1316         .prcm = {
1317                 .omap4 = {
1318                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1319                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1320                 },
1321         },
1322 };
1323
1324 /* mailbox9 */
1325 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1326         .name           = "mailbox9",
1327         .class          = &dra7xx_mailbox_hwmod_class,
1328         .clkdm_name     = "l4cfg_clkdm",
1329         .prcm = {
1330                 .omap4 = {
1331                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1332                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1333                 },
1334         },
1335 };
1336
1337 /* mailbox10 */
1338 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1339         .name           = "mailbox10",
1340         .class          = &dra7xx_mailbox_hwmod_class,
1341         .clkdm_name     = "l4cfg_clkdm",
1342         .prcm = {
1343                 .omap4 = {
1344                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1345                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1346                 },
1347         },
1348 };
1349
1350 /* mailbox11 */
1351 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1352         .name           = "mailbox11",
1353         .class          = &dra7xx_mailbox_hwmod_class,
1354         .clkdm_name     = "l4cfg_clkdm",
1355         .prcm = {
1356                 .omap4 = {
1357                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1358                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1359                 },
1360         },
1361 };
1362
1363 /* mailbox12 */
1364 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1365         .name           = "mailbox12",
1366         .class          = &dra7xx_mailbox_hwmod_class,
1367         .clkdm_name     = "l4cfg_clkdm",
1368         .prcm = {
1369                 .omap4 = {
1370                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1371                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1372                 },
1373         },
1374 };
1375
1376 /* mailbox13 */
1377 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1378         .name           = "mailbox13",
1379         .class          = &dra7xx_mailbox_hwmod_class,
1380         .clkdm_name     = "l4cfg_clkdm",
1381         .prcm = {
1382                 .omap4 = {
1383                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1384                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1385                 },
1386         },
1387 };
1388
1389 /*
1390  * 'mcspi' class
1391  *
1392  */
1393
1394 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1395         .rev_offs       = 0x0000,
1396         .sysc_offs      = 0x0010,
1397         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1398                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1399         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1400                            SIDLE_SMART_WKUP),
1401         .sysc_fields    = &omap_hwmod_sysc_type2,
1402 };
1403
1404 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1405         .name   = "mcspi",
1406         .sysc   = &dra7xx_mcspi_sysc,
1407         .rev    = OMAP4_MCSPI_REV,
1408 };
1409
1410 /* mcspi1 */
1411 /* mcspi1 dev_attr */
1412 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1413         .num_chipselect = 4,
1414 };
1415
1416 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1417         .name           = "mcspi1",
1418         .class          = &dra7xx_mcspi_hwmod_class,
1419         .clkdm_name     = "l4per_clkdm",
1420         .main_clk       = "func_48m_fclk",
1421         .prcm = {
1422                 .omap4 = {
1423                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1424                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1425                         .modulemode   = MODULEMODE_SWCTRL,
1426                 },
1427         },
1428         .dev_attr       = &mcspi1_dev_attr,
1429 };
1430
1431 /* mcspi2 */
1432 /* mcspi2 dev_attr */
1433 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1434         .num_chipselect = 2,
1435 };
1436
1437 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1438         .name           = "mcspi2",
1439         .class          = &dra7xx_mcspi_hwmod_class,
1440         .clkdm_name     = "l4per_clkdm",
1441         .main_clk       = "func_48m_fclk",
1442         .prcm = {
1443                 .omap4 = {
1444                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1445                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1446                         .modulemode   = MODULEMODE_SWCTRL,
1447                 },
1448         },
1449         .dev_attr       = &mcspi2_dev_attr,
1450 };
1451
1452 /* mcspi3 */
1453 /* mcspi3 dev_attr */
1454 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1455         .num_chipselect = 2,
1456 };
1457
1458 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1459         .name           = "mcspi3",
1460         .class          = &dra7xx_mcspi_hwmod_class,
1461         .clkdm_name     = "l4per_clkdm",
1462         .main_clk       = "func_48m_fclk",
1463         .prcm = {
1464                 .omap4 = {
1465                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1466                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1467                         .modulemode   = MODULEMODE_SWCTRL,
1468                 },
1469         },
1470         .dev_attr       = &mcspi3_dev_attr,
1471 };
1472
1473 /* mcspi4 */
1474 /* mcspi4 dev_attr */
1475 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1476         .num_chipselect = 1,
1477 };
1478
1479 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1480         .name           = "mcspi4",
1481         .class          = &dra7xx_mcspi_hwmod_class,
1482         .clkdm_name     = "l4per_clkdm",
1483         .main_clk       = "func_48m_fclk",
1484         .prcm = {
1485                 .omap4 = {
1486                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1487                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1488                         .modulemode   = MODULEMODE_SWCTRL,
1489                 },
1490         },
1491         .dev_attr       = &mcspi4_dev_attr,
1492 };
1493
1494 /*
1495  * 'mcasp' class
1496  *
1497  */
1498 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1499         .sysc_offs      = 0x0004,
1500         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1501         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1502         .sysc_fields    = &omap_hwmod_sysc_type3,
1503 };
1504
1505 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1506         .name   = "mcasp",
1507         .sysc   = &dra7xx_mcasp_sysc,
1508 };
1509
1510 /* mcasp1 */
1511 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1512         { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1513         { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1514 };
1515
1516 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1517         .name           = "mcasp1",
1518         .class          = &dra7xx_mcasp_hwmod_class,
1519         .clkdm_name     = "ipu_clkdm",
1520         .main_clk       = "mcasp1_aux_gfclk_mux",
1521         .flags          = HWMOD_OPT_CLKS_NEEDED,
1522         .prcm = {
1523                 .omap4 = {
1524                         .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1525                         .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1526                         .modulemode   = MODULEMODE_SWCTRL,
1527                 },
1528         },
1529         .opt_clks       = mcasp1_opt_clks,
1530         .opt_clks_cnt   = ARRAY_SIZE(mcasp1_opt_clks),
1531 };
1532
1533 /* mcasp2 */
1534 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1535         { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1536         { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1537 };
1538
1539 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1540         .name           = "mcasp2",
1541         .class          = &dra7xx_mcasp_hwmod_class,
1542         .clkdm_name     = "l4per2_clkdm",
1543         .main_clk       = "mcasp2_aux_gfclk_mux",
1544         .flags          = HWMOD_OPT_CLKS_NEEDED,
1545         .prcm = {
1546                 .omap4 = {
1547                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1548                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1549                         .modulemode   = MODULEMODE_SWCTRL,
1550                 },
1551         },
1552         .opt_clks       = mcasp2_opt_clks,
1553         .opt_clks_cnt   = ARRAY_SIZE(mcasp2_opt_clks),
1554 };
1555
1556 /* mcasp3 */
1557 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1558         { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1559 };
1560
1561 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1562         .name           = "mcasp3",
1563         .class          = &dra7xx_mcasp_hwmod_class,
1564         .clkdm_name     = "l4per2_clkdm",
1565         .main_clk       = "mcasp3_aux_gfclk_mux",
1566         .flags          = HWMOD_OPT_CLKS_NEEDED,
1567         .prcm = {
1568                 .omap4 = {
1569                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1570                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1571                         .modulemode   = MODULEMODE_SWCTRL,
1572                 },
1573         },
1574         .opt_clks       = mcasp3_opt_clks,
1575         .opt_clks_cnt   = ARRAY_SIZE(mcasp3_opt_clks),
1576 };
1577
1578 /* mcasp4 */
1579 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1580         { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1581 };
1582
1583 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1584         .name           = "mcasp4",
1585         .class          = &dra7xx_mcasp_hwmod_class,
1586         .clkdm_name     = "l4per2_clkdm",
1587         .main_clk       = "mcasp4_aux_gfclk_mux",
1588         .flags          = HWMOD_OPT_CLKS_NEEDED,
1589         .prcm = {
1590                 .omap4 = {
1591                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1592                         .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1593                         .modulemode   = MODULEMODE_SWCTRL,
1594                 },
1595         },
1596         .opt_clks       = mcasp4_opt_clks,
1597         .opt_clks_cnt   = ARRAY_SIZE(mcasp4_opt_clks),
1598 };
1599
1600 /* mcasp5 */
1601 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1602         { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1603 };
1604
1605 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1606         .name           = "mcasp5",
1607         .class          = &dra7xx_mcasp_hwmod_class,
1608         .clkdm_name     = "l4per2_clkdm",
1609         .main_clk       = "mcasp5_aux_gfclk_mux",
1610         .flags          = HWMOD_OPT_CLKS_NEEDED,
1611         .prcm = {
1612                 .omap4 = {
1613                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1614                         .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1615                         .modulemode   = MODULEMODE_SWCTRL,
1616                 },
1617         },
1618         .opt_clks       = mcasp5_opt_clks,
1619         .opt_clks_cnt   = ARRAY_SIZE(mcasp5_opt_clks),
1620 };
1621
1622 /* mcasp6 */
1623 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1624         { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1625 };
1626
1627 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1628         .name           = "mcasp6",
1629         .class          = &dra7xx_mcasp_hwmod_class,
1630         .clkdm_name     = "l4per2_clkdm",
1631         .main_clk       = "mcasp6_aux_gfclk_mux",
1632         .flags          = HWMOD_OPT_CLKS_NEEDED,
1633         .prcm = {
1634                 .omap4 = {
1635                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1636                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1637                         .modulemode   = MODULEMODE_SWCTRL,
1638                 },
1639         },
1640         .opt_clks       = mcasp6_opt_clks,
1641         .opt_clks_cnt   = ARRAY_SIZE(mcasp6_opt_clks),
1642 };
1643
1644 /* mcasp7 */
1645 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1646         { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1647 };
1648
1649 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1650         .name           = "mcasp7",
1651         .class          = &dra7xx_mcasp_hwmod_class,
1652         .clkdm_name     = "l4per2_clkdm",
1653         .main_clk       = "mcasp7_aux_gfclk_mux",
1654         .flags          = HWMOD_OPT_CLKS_NEEDED,
1655         .prcm = {
1656                 .omap4 = {
1657                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1658                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1659                         .modulemode   = MODULEMODE_SWCTRL,
1660                 },
1661         },
1662         .opt_clks       = mcasp7_opt_clks,
1663         .opt_clks_cnt   = ARRAY_SIZE(mcasp7_opt_clks),
1664 };
1665
1666 /* mcasp8 */
1667 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1668         { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1669 };
1670
1671 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1672         .name           = "mcasp8",
1673         .class          = &dra7xx_mcasp_hwmod_class,
1674         .clkdm_name     = "l4per2_clkdm",
1675         .main_clk       = "mcasp8_aux_gfclk_mux",
1676         .flags          = HWMOD_OPT_CLKS_NEEDED,
1677         .prcm = {
1678                 .omap4 = {
1679                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1680                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1681                         .modulemode   = MODULEMODE_SWCTRL,
1682                 },
1683         },
1684         .opt_clks       = mcasp8_opt_clks,
1685         .opt_clks_cnt   = ARRAY_SIZE(mcasp8_opt_clks),
1686 };
1687
1688 /*
1689  * 'mmc' class
1690  *
1691  */
1692
1693 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1694         .rev_offs       = 0x0000,
1695         .sysc_offs      = 0x0010,
1696         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1697                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1698                            SYSC_HAS_SOFTRESET),
1699         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1700                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1701                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1702         .sysc_fields    = &omap_hwmod_sysc_type2,
1703 };
1704
1705 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1706         .name   = "mmc",
1707         .sysc   = &dra7xx_mmc_sysc,
1708 };
1709
1710 /* mmc1 */
1711 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1712         { .role = "clk32k", .clk = "mmc1_clk32k" },
1713 };
1714
1715 /* mmc1 dev_attr */
1716 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1717         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1718 };
1719
1720 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1721         .name           = "mmc1",
1722         .class          = &dra7xx_mmc_hwmod_class,
1723         .clkdm_name     = "l3init_clkdm",
1724         .main_clk       = "mmc1_fclk_div",
1725         .prcm = {
1726                 .omap4 = {
1727                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1728                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1729                         .modulemode   = MODULEMODE_SWCTRL,
1730                 },
1731         },
1732         .opt_clks       = mmc1_opt_clks,
1733         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1734         .dev_attr       = &mmc1_dev_attr,
1735 };
1736
1737 /* mmc2 */
1738 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1739         { .role = "clk32k", .clk = "mmc2_clk32k" },
1740 };
1741
1742 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1743         .name           = "mmc2",
1744         .class          = &dra7xx_mmc_hwmod_class,
1745         .clkdm_name     = "l3init_clkdm",
1746         .main_clk       = "mmc2_fclk_div",
1747         .prcm = {
1748                 .omap4 = {
1749                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1750                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1751                         .modulemode   = MODULEMODE_SWCTRL,
1752                 },
1753         },
1754         .opt_clks       = mmc2_opt_clks,
1755         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1756 };
1757
1758 /* mmc3 */
1759 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1760         { .role = "clk32k", .clk = "mmc3_clk32k" },
1761 };
1762
1763 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1764         .name           = "mmc3",
1765         .class          = &dra7xx_mmc_hwmod_class,
1766         .clkdm_name     = "l4per_clkdm",
1767         .main_clk       = "mmc3_gfclk_div",
1768         .prcm = {
1769                 .omap4 = {
1770                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1771                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1772                         .modulemode   = MODULEMODE_SWCTRL,
1773                 },
1774         },
1775         .opt_clks       = mmc3_opt_clks,
1776         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1777 };
1778
1779 /* mmc4 */
1780 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1781         { .role = "clk32k", .clk = "mmc4_clk32k" },
1782 };
1783
1784 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1785         .name           = "mmc4",
1786         .class          = &dra7xx_mmc_hwmod_class,
1787         .clkdm_name     = "l4per_clkdm",
1788         .main_clk       = "mmc4_gfclk_div",
1789         .prcm = {
1790                 .omap4 = {
1791                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1792                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1793                         .modulemode   = MODULEMODE_SWCTRL,
1794                 },
1795         },
1796         .opt_clks       = mmc4_opt_clks,
1797         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1798 };
1799
1800 /*
1801  * 'mpu' class
1802  *
1803  */
1804
1805 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1806         .name   = "mpu",
1807 };
1808
1809 /* mpu */
1810 static struct omap_hwmod dra7xx_mpu_hwmod = {
1811         .name           = "mpu",
1812         .class          = &dra7xx_mpu_hwmod_class,
1813         .clkdm_name     = "mpu_clkdm",
1814         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1815         .main_clk       = "dpll_mpu_m2_ck",
1816         .prcm = {
1817                 .omap4 = {
1818                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1819                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1820                 },
1821         },
1822 };
1823
1824 /*
1825  * 'ocp2scp' class
1826  *
1827  */
1828
1829 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1830         .rev_offs       = 0x0000,
1831         .sysc_offs      = 0x0010,
1832         .syss_offs      = 0x0014,
1833         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1834                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1835         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1836         .sysc_fields    = &omap_hwmod_sysc_type1,
1837 };
1838
1839 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1840         .name   = "ocp2scp",
1841         .sysc   = &dra7xx_ocp2scp_sysc,
1842 };
1843
1844 /* ocp2scp1 */
1845 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1846         .name           = "ocp2scp1",
1847         .class          = &dra7xx_ocp2scp_hwmod_class,
1848         .clkdm_name     = "l3init_clkdm",
1849         .main_clk       = "l4_root_clk_div",
1850         .prcm = {
1851                 .omap4 = {
1852                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1853                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1854                         .modulemode   = MODULEMODE_HWCTRL,
1855                 },
1856         },
1857 };
1858
1859 /* ocp2scp3 */
1860 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1861         .name           = "ocp2scp3",
1862         .class          = &dra7xx_ocp2scp_hwmod_class,
1863         .clkdm_name     = "l3init_clkdm",
1864         .main_clk       = "l4_root_clk_div",
1865         .prcm = {
1866                 .omap4 = {
1867                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1868                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1869                         .modulemode   = MODULEMODE_HWCTRL,
1870                 },
1871         },
1872 };
1873
1874 /*
1875  * 'PCIE' class
1876  *
1877  */
1878
1879 /*
1880  * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1881  * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1882  * associated with an IP automatically leaving the driver to handle that
1883  * by itself. This does not work for PCIeSS which needs the reset lines
1884  * deasserted for the driver to start accessing registers.
1885  *
1886  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1887  * lines after asserting them.
1888  */
1889 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1890 {
1891         int i;
1892
1893         for (i = 0; i < oh->rst_lines_cnt; i++) {
1894                 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1895                 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1896         }
1897
1898         return 0;
1899 }
1900
1901 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1902         .name   = "pcie",
1903         .reset  = dra7xx_pciess_reset,
1904 };
1905
1906 /* pcie1 */
1907 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1908         { .name = "pcie", .rst_shift = 0 },
1909 };
1910
1911 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1912         .name           = "pcie1",
1913         .class          = &dra7xx_pciess_hwmod_class,
1914         .clkdm_name     = "pcie_clkdm",
1915         .rst_lines      = dra7xx_pciess1_resets,
1916         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
1917         .main_clk       = "l4_root_clk_div",
1918         .prcm = {
1919                 .omap4 = {
1920                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1921                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1922                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1923                         .modulemode   = MODULEMODE_SWCTRL,
1924                 },
1925         },
1926 };
1927
1928 /* pcie2 */
1929 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1930         { .name = "pcie", .rst_shift = 1 },
1931 };
1932
1933 /* pcie2 */
1934 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1935         .name           = "pcie2",
1936         .class          = &dra7xx_pciess_hwmod_class,
1937         .clkdm_name     = "pcie_clkdm",
1938         .rst_lines      = dra7xx_pciess2_resets,
1939         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
1940         .main_clk       = "l4_root_clk_div",
1941         .prcm = {
1942                 .omap4 = {
1943                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1944                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1945                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1946                         .modulemode   = MODULEMODE_SWCTRL,
1947                 },
1948         },
1949 };
1950
1951 /*
1952  * 'qspi' class
1953  *
1954  */
1955
1956 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1957         .sysc_offs      = 0x0010,
1958         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1959         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1960                            SIDLE_SMART_WKUP),
1961         .sysc_fields    = &omap_hwmod_sysc_type2,
1962 };
1963
1964 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1965         .name   = "qspi",
1966         .sysc   = &dra7xx_qspi_sysc,
1967 };
1968
1969 /* qspi */
1970 static struct omap_hwmod dra7xx_qspi_hwmod = {
1971         .name           = "qspi",
1972         .class          = &dra7xx_qspi_hwmod_class,
1973         .clkdm_name     = "l4per2_clkdm",
1974         .main_clk       = "qspi_gfclk_div",
1975         .prcm = {
1976                 .omap4 = {
1977                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1978                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1979                         .modulemode   = MODULEMODE_SWCTRL,
1980                 },
1981         },
1982 };
1983
1984 /*
1985  * 'rtcss' class
1986  *
1987  */
1988 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1989         .sysc_offs      = 0x0078,
1990         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1991         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1992                            SIDLE_SMART_WKUP),
1993         .sysc_fields    = &omap_hwmod_sysc_type3,
1994 };
1995
1996 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1997         .name   = "rtcss",
1998         .sysc   = &dra7xx_rtcss_sysc,
1999         .unlock = &omap_hwmod_rtc_unlock,
2000         .lock   = &omap_hwmod_rtc_lock,
2001 };
2002
2003 /* rtcss */
2004 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2005         .name           = "rtcss",
2006         .class          = &dra7xx_rtcss_hwmod_class,
2007         .clkdm_name     = "rtc_clkdm",
2008         .main_clk       = "sys_32k_ck",
2009         .prcm = {
2010                 .omap4 = {
2011                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2012                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2013                         .modulemode   = MODULEMODE_SWCTRL,
2014                 },
2015         },
2016 };
2017
2018 /*
2019  * 'sata' class
2020  *
2021  */
2022
2023 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2024         .sysc_offs      = 0x0000,
2025         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2026         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2027                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2028                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2029         .sysc_fields    = &omap_hwmod_sysc_type2,
2030 };
2031
2032 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2033         .name   = "sata",
2034         .sysc   = &dra7xx_sata_sysc,
2035 };
2036
2037 /* sata */
2038
2039 static struct omap_hwmod dra7xx_sata_hwmod = {
2040         .name           = "sata",
2041         .class          = &dra7xx_sata_hwmod_class,
2042         .clkdm_name     = "l3init_clkdm",
2043         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2044         .main_clk       = "func_48m_fclk",
2045         .mpu_rt_idx     = 1,
2046         .prcm = {
2047                 .omap4 = {
2048                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2049                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2050                         .modulemode   = MODULEMODE_SWCTRL,
2051                 },
2052         },
2053 };
2054
2055 /*
2056  * 'smartreflex' class
2057  *
2058  */
2059
2060 /* The IP is not compliant to type1 / type2 scheme */
2061 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2062         .sidle_shift    = 24,
2063         .enwkup_shift   = 26,
2064 };
2065
2066 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2067         .sysc_offs      = 0x0038,
2068         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2069         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2070                            SIDLE_SMART_WKUP),
2071         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2072 };
2073
2074 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2075         .name   = "smartreflex",
2076         .sysc   = &dra7xx_smartreflex_sysc,
2077         .rev    = 2,
2078 };
2079
2080 /* smartreflex_core */
2081 /* smartreflex_core dev_attr */
2082 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2083         .sensor_voltdm_name     = "core",
2084 };
2085
2086 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2087         .name           = "smartreflex_core",
2088         .class          = &dra7xx_smartreflex_hwmod_class,
2089         .clkdm_name     = "coreaon_clkdm",
2090         .main_clk       = "wkupaon_iclk_mux",
2091         .prcm = {
2092                 .omap4 = {
2093                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2094                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2095                         .modulemode   = MODULEMODE_SWCTRL,
2096                 },
2097         },
2098         .dev_attr       = &smartreflex_core_dev_attr,
2099 };
2100
2101 /* smartreflex_mpu */
2102 /* smartreflex_mpu dev_attr */
2103 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2104         .sensor_voltdm_name     = "mpu",
2105 };
2106
2107 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2108         .name           = "smartreflex_mpu",
2109         .class          = &dra7xx_smartreflex_hwmod_class,
2110         .clkdm_name     = "coreaon_clkdm",
2111         .main_clk       = "wkupaon_iclk_mux",
2112         .prcm = {
2113                 .omap4 = {
2114                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2115                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2116                         .modulemode   = MODULEMODE_SWCTRL,
2117                 },
2118         },
2119         .dev_attr       = &smartreflex_mpu_dev_attr,
2120 };
2121
2122 /*
2123  * 'spinlock' class
2124  *
2125  */
2126
2127 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2128         .rev_offs       = 0x0000,
2129         .sysc_offs      = 0x0010,
2130         .syss_offs      = 0x0014,
2131         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2132                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2133                            SYSS_HAS_RESET_STATUS),
2134         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2135         .sysc_fields    = &omap_hwmod_sysc_type1,
2136 };
2137
2138 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2139         .name   = "spinlock",
2140         .sysc   = &dra7xx_spinlock_sysc,
2141 };
2142
2143 /* spinlock */
2144 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2145         .name           = "spinlock",
2146         .class          = &dra7xx_spinlock_hwmod_class,
2147         .clkdm_name     = "l4cfg_clkdm",
2148         .main_clk       = "l3_iclk_div",
2149         .prcm = {
2150                 .omap4 = {
2151                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2152                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2153                 },
2154         },
2155 };
2156
2157 /*
2158  * 'timer' class
2159  *
2160  * This class contains several variants: ['timer_1ms', 'timer_secure',
2161  * 'timer']
2162  */
2163
2164 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2165         .rev_offs       = 0x0000,
2166         .sysc_offs      = 0x0010,
2167         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2168                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2169         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2170                            SIDLE_SMART_WKUP),
2171         .sysc_fields    = &omap_hwmod_sysc_type2,
2172 };
2173
2174 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2175         .name   = "timer",
2176         .sysc   = &dra7xx_timer_1ms_sysc,
2177 };
2178
2179 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2180         .rev_offs       = 0x0000,
2181         .sysc_offs      = 0x0010,
2182         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2183                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2184         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2185                            SIDLE_SMART_WKUP),
2186         .sysc_fields    = &omap_hwmod_sysc_type2,
2187 };
2188
2189 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2190         .name   = "timer",
2191         .sysc   = &dra7xx_timer_sysc,
2192 };
2193
2194 /* timer1 */
2195 static struct omap_hwmod dra7xx_timer1_hwmod = {
2196         .name           = "timer1",
2197         .class          = &dra7xx_timer_1ms_hwmod_class,
2198         .clkdm_name     = "wkupaon_clkdm",
2199         .main_clk       = "timer1_gfclk_mux",
2200         .prcm = {
2201                 .omap4 = {
2202                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2203                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2204                         .modulemode   = MODULEMODE_SWCTRL,
2205                 },
2206         },
2207 };
2208
2209 /* timer2 */
2210 static struct omap_hwmod dra7xx_timer2_hwmod = {
2211         .name           = "timer2",
2212         .class          = &dra7xx_timer_1ms_hwmod_class,
2213         .clkdm_name     = "l4per_clkdm",
2214         .main_clk       = "timer2_gfclk_mux",
2215         .prcm = {
2216                 .omap4 = {
2217                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2218                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2219                         .modulemode   = MODULEMODE_SWCTRL,
2220                 },
2221         },
2222 };
2223
2224 /* timer3 */
2225 static struct omap_hwmod dra7xx_timer3_hwmod = {
2226         .name           = "timer3",
2227         .class          = &dra7xx_timer_hwmod_class,
2228         .clkdm_name     = "l4per_clkdm",
2229         .main_clk       = "timer3_gfclk_mux",
2230         .prcm = {
2231                 .omap4 = {
2232                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2233                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2234                         .modulemode   = MODULEMODE_SWCTRL,
2235                 },
2236         },
2237 };
2238
2239 /* timer4 */
2240 static struct omap_hwmod dra7xx_timer4_hwmod = {
2241         .name           = "timer4",
2242         .class          = &dra7xx_timer_hwmod_class,
2243         .clkdm_name     = "l4per_clkdm",
2244         .main_clk       = "timer4_gfclk_mux",
2245         .prcm = {
2246                 .omap4 = {
2247                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2248                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2249                         .modulemode   = MODULEMODE_SWCTRL,
2250                 },
2251         },
2252 };
2253
2254 /* timer5 */
2255 static struct omap_hwmod dra7xx_timer5_hwmod = {
2256         .name           = "timer5",
2257         .class          = &dra7xx_timer_hwmod_class,
2258         .clkdm_name     = "ipu_clkdm",
2259         .main_clk       = "timer5_gfclk_mux",
2260         .prcm = {
2261                 .omap4 = {
2262                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2263                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2264                         .modulemode   = MODULEMODE_SWCTRL,
2265                 },
2266         },
2267 };
2268
2269 /* timer6 */
2270 static struct omap_hwmod dra7xx_timer6_hwmod = {
2271         .name           = "timer6",
2272         .class          = &dra7xx_timer_hwmod_class,
2273         .clkdm_name     = "ipu_clkdm",
2274         .main_clk       = "timer6_gfclk_mux",
2275         .prcm = {
2276                 .omap4 = {
2277                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2278                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2279                         .modulemode   = MODULEMODE_SWCTRL,
2280                 },
2281         },
2282 };
2283
2284 /* timer7 */
2285 static struct omap_hwmod dra7xx_timer7_hwmod = {
2286         .name           = "timer7",
2287         .class          = &dra7xx_timer_hwmod_class,
2288         .clkdm_name     = "ipu_clkdm",
2289         .main_clk       = "timer7_gfclk_mux",
2290         .prcm = {
2291                 .omap4 = {
2292                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2293                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2294                         .modulemode   = MODULEMODE_SWCTRL,
2295                 },
2296         },
2297 };
2298
2299 /* timer8 */
2300 static struct omap_hwmod dra7xx_timer8_hwmod = {
2301         .name           = "timer8",
2302         .class          = &dra7xx_timer_hwmod_class,
2303         .clkdm_name     = "ipu_clkdm",
2304         .main_clk       = "timer8_gfclk_mux",
2305         .prcm = {
2306                 .omap4 = {
2307                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2308                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2309                         .modulemode   = MODULEMODE_SWCTRL,
2310                 },
2311         },
2312 };
2313
2314 /* timer9 */
2315 static struct omap_hwmod dra7xx_timer9_hwmod = {
2316         .name           = "timer9",
2317         .class          = &dra7xx_timer_hwmod_class,
2318         .clkdm_name     = "l4per_clkdm",
2319         .main_clk       = "timer9_gfclk_mux",
2320         .prcm = {
2321                 .omap4 = {
2322                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2323                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2324                         .modulemode   = MODULEMODE_SWCTRL,
2325                 },
2326         },
2327 };
2328
2329 /* timer10 */
2330 static struct omap_hwmod dra7xx_timer10_hwmod = {
2331         .name           = "timer10",
2332         .class          = &dra7xx_timer_1ms_hwmod_class,
2333         .clkdm_name     = "l4per_clkdm",
2334         .main_clk       = "timer10_gfclk_mux",
2335         .prcm = {
2336                 .omap4 = {
2337                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2338                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2339                         .modulemode   = MODULEMODE_SWCTRL,
2340                 },
2341         },
2342 };
2343
2344 /* timer11 */
2345 static struct omap_hwmod dra7xx_timer11_hwmod = {
2346         .name           = "timer11",
2347         .class          = &dra7xx_timer_hwmod_class,
2348         .clkdm_name     = "l4per_clkdm",
2349         .main_clk       = "timer11_gfclk_mux",
2350         .prcm = {
2351                 .omap4 = {
2352                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2353                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2354                         .modulemode   = MODULEMODE_SWCTRL,
2355                 },
2356         },
2357 };
2358
2359 /* timer12 */
2360 static struct omap_hwmod dra7xx_timer12_hwmod = {
2361         .name           = "timer12",
2362         .class          = &dra7xx_timer_hwmod_class,
2363         .clkdm_name     = "wkupaon_clkdm",
2364         .main_clk       = "secure_32k_clk_src_ck",
2365         .prcm = {
2366                 .omap4 = {
2367                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2368                         .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2369                 },
2370         },
2371 };
2372
2373 /* timer13 */
2374 static struct omap_hwmod dra7xx_timer13_hwmod = {
2375         .name           = "timer13",
2376         .class          = &dra7xx_timer_hwmod_class,
2377         .clkdm_name     = "l4per3_clkdm",
2378         .main_clk       = "timer13_gfclk_mux",
2379         .prcm = {
2380                 .omap4 = {
2381                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2382                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2383                         .modulemode   = MODULEMODE_SWCTRL,
2384                 },
2385         },
2386 };
2387
2388 /* timer14 */
2389 static struct omap_hwmod dra7xx_timer14_hwmod = {
2390         .name           = "timer14",
2391         .class          = &dra7xx_timer_hwmod_class,
2392         .clkdm_name     = "l4per3_clkdm",
2393         .main_clk       = "timer14_gfclk_mux",
2394         .prcm = {
2395                 .omap4 = {
2396                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2397                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2398                         .modulemode   = MODULEMODE_SWCTRL,
2399                 },
2400         },
2401 };
2402
2403 /* timer15 */
2404 static struct omap_hwmod dra7xx_timer15_hwmod = {
2405         .name           = "timer15",
2406         .class          = &dra7xx_timer_hwmod_class,
2407         .clkdm_name     = "l4per3_clkdm",
2408         .main_clk       = "timer15_gfclk_mux",
2409         .prcm = {
2410                 .omap4 = {
2411                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2412                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2413                         .modulemode   = MODULEMODE_SWCTRL,
2414                 },
2415         },
2416 };
2417
2418 /* timer16 */
2419 static struct omap_hwmod dra7xx_timer16_hwmod = {
2420         .name           = "timer16",
2421         .class          = &dra7xx_timer_hwmod_class,
2422         .clkdm_name     = "l4per3_clkdm",
2423         .main_clk       = "timer16_gfclk_mux",
2424         .prcm = {
2425                 .omap4 = {
2426                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2427                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2428                         .modulemode   = MODULEMODE_SWCTRL,
2429                 },
2430         },
2431 };
2432
2433 /*
2434  * 'uart' class
2435  *
2436  */
2437
2438 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2439         .rev_offs       = 0x0050,
2440         .sysc_offs      = 0x0054,
2441         .syss_offs      = 0x0058,
2442         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2443                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2444                            SYSS_HAS_RESET_STATUS),
2445         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2446                            SIDLE_SMART_WKUP),
2447         .sysc_fields    = &omap_hwmod_sysc_type1,
2448 };
2449
2450 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2451         .name   = "uart",
2452         .sysc   = &dra7xx_uart_sysc,
2453 };
2454
2455 /* uart1 */
2456 static struct omap_hwmod dra7xx_uart1_hwmod = {
2457         .name           = "uart1",
2458         .class          = &dra7xx_uart_hwmod_class,
2459         .clkdm_name     = "l4per_clkdm",
2460         .main_clk       = "uart1_gfclk_mux",
2461         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2462         .prcm = {
2463                 .omap4 = {
2464                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2465                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2466                         .modulemode   = MODULEMODE_SWCTRL,
2467                 },
2468         },
2469 };
2470
2471 /* uart2 */
2472 static struct omap_hwmod dra7xx_uart2_hwmod = {
2473         .name           = "uart2",
2474         .class          = &dra7xx_uart_hwmod_class,
2475         .clkdm_name     = "l4per_clkdm",
2476         .main_clk       = "uart2_gfclk_mux",
2477         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2478         .prcm = {
2479                 .omap4 = {
2480                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2481                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2482                         .modulemode   = MODULEMODE_SWCTRL,
2483                 },
2484         },
2485 };
2486
2487 /* uart3 */
2488 static struct omap_hwmod dra7xx_uart3_hwmod = {
2489         .name           = "uart3",
2490         .class          = &dra7xx_uart_hwmod_class,
2491         .clkdm_name     = "l4per_clkdm",
2492         .main_clk       = "uart3_gfclk_mux",
2493         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2494         .prcm = {
2495                 .omap4 = {
2496                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2497                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2498                         .modulemode   = MODULEMODE_SWCTRL,
2499                 },
2500         },
2501 };
2502
2503 /* uart4 */
2504 static struct omap_hwmod dra7xx_uart4_hwmod = {
2505         .name           = "uart4",
2506         .class          = &dra7xx_uart_hwmod_class,
2507         .clkdm_name     = "l4per_clkdm",
2508         .main_clk       = "uart4_gfclk_mux",
2509         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2510         .prcm = {
2511                 .omap4 = {
2512                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2513                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2514                         .modulemode   = MODULEMODE_SWCTRL,
2515                 },
2516         },
2517 };
2518
2519 /* uart5 */
2520 static struct omap_hwmod dra7xx_uart5_hwmod = {
2521         .name           = "uart5",
2522         .class          = &dra7xx_uart_hwmod_class,
2523         .clkdm_name     = "l4per_clkdm",
2524         .main_clk       = "uart5_gfclk_mux",
2525         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2526         .prcm = {
2527                 .omap4 = {
2528                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2529                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2530                         .modulemode   = MODULEMODE_SWCTRL,
2531                 },
2532         },
2533 };
2534
2535 /* uart6 */
2536 static struct omap_hwmod dra7xx_uart6_hwmod = {
2537         .name           = "uart6",
2538         .class          = &dra7xx_uart_hwmod_class,
2539         .clkdm_name     = "ipu_clkdm",
2540         .main_clk       = "uart6_gfclk_mux",
2541         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2542         .prcm = {
2543                 .omap4 = {
2544                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2545                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2546                         .modulemode   = MODULEMODE_SWCTRL,
2547                 },
2548         },
2549 };
2550
2551 /* uart7 */
2552 static struct omap_hwmod dra7xx_uart7_hwmod = {
2553         .name           = "uart7",
2554         .class          = &dra7xx_uart_hwmod_class,
2555         .clkdm_name     = "l4per2_clkdm",
2556         .main_clk       = "uart7_gfclk_mux",
2557         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2558         .prcm = {
2559                 .omap4 = {
2560                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2561                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2562                         .modulemode   = MODULEMODE_SWCTRL,
2563                 },
2564         },
2565 };
2566
2567 /* uart8 */
2568 static struct omap_hwmod dra7xx_uart8_hwmod = {
2569         .name           = "uart8",
2570         .class          = &dra7xx_uart_hwmod_class,
2571         .clkdm_name     = "l4per2_clkdm",
2572         .main_clk       = "uart8_gfclk_mux",
2573         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2574         .prcm = {
2575                 .omap4 = {
2576                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2577                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2578                         .modulemode   = MODULEMODE_SWCTRL,
2579                 },
2580         },
2581 };
2582
2583 /* uart9 */
2584 static struct omap_hwmod dra7xx_uart9_hwmod = {
2585         .name           = "uart9",
2586         .class          = &dra7xx_uart_hwmod_class,
2587         .clkdm_name     = "l4per2_clkdm",
2588         .main_clk       = "uart9_gfclk_mux",
2589         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2590         .prcm = {
2591                 .omap4 = {
2592                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2593                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2594                         .modulemode   = MODULEMODE_SWCTRL,
2595                 },
2596         },
2597 };
2598
2599 /* uart10 */
2600 static struct omap_hwmod dra7xx_uart10_hwmod = {
2601         .name           = "uart10",
2602         .class          = &dra7xx_uart_hwmod_class,
2603         .clkdm_name     = "wkupaon_clkdm",
2604         .main_clk       = "uart10_gfclk_mux",
2605         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2606         .prcm = {
2607                 .omap4 = {
2608                         .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2609                         .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2610                         .modulemode   = MODULEMODE_SWCTRL,
2611                 },
2612         },
2613 };
2614
2615 /* DES (the 'P' (public) device) */
2616 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2617         .rev_offs       = 0x0030,
2618         .sysc_offs      = 0x0034,
2619         .syss_offs      = 0x0038,
2620         .sysc_flags     = SYSS_HAS_RESET_STATUS,
2621 };
2622
2623 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2624         .name   = "des",
2625         .sysc   = &dra7xx_des_sysc,
2626 };
2627
2628 /* DES */
2629 static struct omap_hwmod dra7xx_des_hwmod = {
2630         .name           = "des",
2631         .class          = &dra7xx_des_hwmod_class,
2632         .clkdm_name     = "l4sec_clkdm",
2633         .main_clk       = "l3_iclk_div",
2634         .prcm = {
2635                 .omap4 = {
2636                         .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2637                         .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2638                         .modulemode   = MODULEMODE_HWCTRL,
2639                 },
2640         },
2641 };
2642
2643 /* rng */
2644 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2645         .rev_offs       = 0x1fe0,
2646         .sysc_offs      = 0x1fe4,
2647         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2648         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
2649         .sysc_fields    = &omap_hwmod_sysc_type1,
2650 };
2651
2652 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2653         .name           = "rng",
2654         .sysc           = &dra7xx_rng_sysc,
2655 };
2656
2657 static struct omap_hwmod dra7xx_rng_hwmod = {
2658         .name           = "rng",
2659         .class          = &dra7xx_rng_hwmod_class,
2660         .flags          = HWMOD_SWSUP_SIDLE,
2661         .clkdm_name     = "l4sec_clkdm",
2662         .prcm = {
2663                 .omap4 = {
2664                         .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2665                         .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2666                         .modulemode   = MODULEMODE_HWCTRL,
2667                 },
2668         },
2669 };
2670
2671 /*
2672  * 'usb_otg_ss' class
2673  *
2674  */
2675
2676 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2677         .rev_offs       = 0x0000,
2678         .sysc_offs      = 0x0010,
2679         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2680                            SYSC_HAS_SIDLEMODE),
2681         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2682                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2683                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2684         .sysc_fields    = &omap_hwmod_sysc_type2,
2685 };
2686
2687 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2688         .name   = "usb_otg_ss",
2689         .sysc   = &dra7xx_usb_otg_ss_sysc,
2690 };
2691
2692 /* usb_otg_ss1 */
2693 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2694         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2695 };
2696
2697 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2698         .name           = "usb_otg_ss1",
2699         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2700         .clkdm_name     = "l3init_clkdm",
2701         .main_clk       = "dpll_core_h13x2_ck",
2702         .prcm = {
2703                 .omap4 = {
2704                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2705                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2706                         .modulemode   = MODULEMODE_HWCTRL,
2707                 },
2708         },
2709         .opt_clks       = usb_otg_ss1_opt_clks,
2710         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2711 };
2712
2713 /* usb_otg_ss2 */
2714 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2715         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2716 };
2717
2718 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2719         .name           = "usb_otg_ss2",
2720         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2721         .clkdm_name     = "l3init_clkdm",
2722         .main_clk       = "dpll_core_h13x2_ck",
2723         .prcm = {
2724                 .omap4 = {
2725                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2726                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2727                         .modulemode   = MODULEMODE_HWCTRL,
2728                 },
2729         },
2730         .opt_clks       = usb_otg_ss2_opt_clks,
2731         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2732 };
2733
2734 /* usb_otg_ss3 */
2735 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2736         .name           = "usb_otg_ss3",
2737         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2738         .clkdm_name     = "l3init_clkdm",
2739         .main_clk       = "dpll_core_h13x2_ck",
2740         .prcm = {
2741                 .omap4 = {
2742                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2743                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2744                         .modulemode   = MODULEMODE_HWCTRL,
2745                 },
2746         },
2747 };
2748
2749 /* usb_otg_ss4 */
2750 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2751         .name           = "usb_otg_ss4",
2752         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2753         .clkdm_name     = "l3init_clkdm",
2754         .main_clk       = "dpll_core_h13x2_ck",
2755         .prcm = {
2756                 .omap4 = {
2757                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2758                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2759                         .modulemode   = MODULEMODE_HWCTRL,
2760                 },
2761         },
2762 };
2763
2764 /*
2765  * 'vcp' class
2766  *
2767  */
2768
2769 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2770         .name   = "vcp",
2771 };
2772
2773 /* vcp1 */
2774 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2775         .name           = "vcp1",
2776         .class          = &dra7xx_vcp_hwmod_class,
2777         .clkdm_name     = "l3main1_clkdm",
2778         .main_clk       = "l3_iclk_div",
2779         .prcm = {
2780                 .omap4 = {
2781                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2782                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2783                 },
2784         },
2785 };
2786
2787 /* vcp2 */
2788 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2789         .name           = "vcp2",
2790         .class          = &dra7xx_vcp_hwmod_class,
2791         .clkdm_name     = "l3main1_clkdm",
2792         .main_clk       = "l3_iclk_div",
2793         .prcm = {
2794                 .omap4 = {
2795                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2796                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2797                 },
2798         },
2799 };
2800
2801 /*
2802  * 'wd_timer' class
2803  *
2804  */
2805
2806 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2807         .rev_offs       = 0x0000,
2808         .sysc_offs      = 0x0010,
2809         .syss_offs      = 0x0014,
2810         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2811                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2812         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2813                            SIDLE_SMART_WKUP),
2814         .sysc_fields    = &omap_hwmod_sysc_type1,
2815 };
2816
2817 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2818         .name           = "wd_timer",
2819         .sysc           = &dra7xx_wd_timer_sysc,
2820         .pre_shutdown   = &omap2_wd_timer_disable,
2821         .reset          = &omap2_wd_timer_reset,
2822 };
2823
2824 /* wd_timer2 */
2825 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2826         .name           = "wd_timer2",
2827         .class          = &dra7xx_wd_timer_hwmod_class,
2828         .clkdm_name     = "wkupaon_clkdm",
2829         .main_clk       = "sys_32k_ck",
2830         .prcm = {
2831                 .omap4 = {
2832                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2833                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2834                         .modulemode   = MODULEMODE_SWCTRL,
2835                 },
2836         },
2837 };
2838
2839
2840 /*
2841  * Interfaces
2842  */
2843
2844 /* l3_main_1 -> dmm */
2845 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2846         .master         = &dra7xx_l3_main_1_hwmod,
2847         .slave          = &dra7xx_dmm_hwmod,
2848         .clk            = "l3_iclk_div",
2849         .user           = OCP_USER_SDMA,
2850 };
2851
2852 /* l3_main_2 -> l3_instr */
2853 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2854         .master         = &dra7xx_l3_main_2_hwmod,
2855         .slave          = &dra7xx_l3_instr_hwmod,
2856         .clk            = "l3_iclk_div",
2857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2858 };
2859
2860 /* l4_cfg -> l3_main_1 */
2861 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2862         .master         = &dra7xx_l4_cfg_hwmod,
2863         .slave          = &dra7xx_l3_main_1_hwmod,
2864         .clk            = "l3_iclk_div",
2865         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2866 };
2867
2868 /* mpu -> l3_main_1 */
2869 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2870         .master         = &dra7xx_mpu_hwmod,
2871         .slave          = &dra7xx_l3_main_1_hwmod,
2872         .clk            = "l3_iclk_div",
2873         .user           = OCP_USER_MPU,
2874 };
2875
2876 /* l3_main_1 -> l3_main_2 */
2877 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2878         .master         = &dra7xx_l3_main_1_hwmod,
2879         .slave          = &dra7xx_l3_main_2_hwmod,
2880         .clk            = "l3_iclk_div",
2881         .user           = OCP_USER_MPU,
2882 };
2883
2884 /* l4_cfg -> l3_main_2 */
2885 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2886         .master         = &dra7xx_l4_cfg_hwmod,
2887         .slave          = &dra7xx_l3_main_2_hwmod,
2888         .clk            = "l3_iclk_div",
2889         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2890 };
2891
2892 /* l3_main_1 -> l4_cfg */
2893 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2894         .master         = &dra7xx_l3_main_1_hwmod,
2895         .slave          = &dra7xx_l4_cfg_hwmod,
2896         .clk            = "l3_iclk_div",
2897         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2898 };
2899
2900 /* l3_main_1 -> l4_per1 */
2901 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2902         .master         = &dra7xx_l3_main_1_hwmod,
2903         .slave          = &dra7xx_l4_per1_hwmod,
2904         .clk            = "l3_iclk_div",
2905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2906 };
2907
2908 /* l3_main_1 -> l4_per2 */
2909 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2910         .master         = &dra7xx_l3_main_1_hwmod,
2911         .slave          = &dra7xx_l4_per2_hwmod,
2912         .clk            = "l3_iclk_div",
2913         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2914 };
2915
2916 /* l3_main_1 -> l4_per3 */
2917 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2918         .master         = &dra7xx_l3_main_1_hwmod,
2919         .slave          = &dra7xx_l4_per3_hwmod,
2920         .clk            = "l3_iclk_div",
2921         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2922 };
2923
2924 /* l3_main_1 -> l4_wkup */
2925 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2926         .master         = &dra7xx_l3_main_1_hwmod,
2927         .slave          = &dra7xx_l4_wkup_hwmod,
2928         .clk            = "wkupaon_iclk_mux",
2929         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2930 };
2931
2932 /* l4_per2 -> atl */
2933 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2934         .master         = &dra7xx_l4_per2_hwmod,
2935         .slave          = &dra7xx_atl_hwmod,
2936         .clk            = "l3_iclk_div",
2937         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2938 };
2939
2940 /* l3_main_1 -> bb2d */
2941 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2942         .master         = &dra7xx_l3_main_1_hwmod,
2943         .slave          = &dra7xx_bb2d_hwmod,
2944         .clk            = "l3_iclk_div",
2945         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2946 };
2947
2948 /* l4_wkup -> counter_32k */
2949 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2950         .master         = &dra7xx_l4_wkup_hwmod,
2951         .slave          = &dra7xx_counter_32k_hwmod,
2952         .clk            = "wkupaon_iclk_mux",
2953         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2954 };
2955
2956 /* l4_wkup -> ctrl_module_wkup */
2957 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2958         .master         = &dra7xx_l4_wkup_hwmod,
2959         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2960         .clk            = "wkupaon_iclk_mux",
2961         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2962 };
2963
2964 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2965         .master         = &dra7xx_l4_per2_hwmod,
2966         .slave          = &dra7xx_gmac_hwmod,
2967         .clk            = "dpll_gmac_ck",
2968         .user           = OCP_USER_MPU,
2969 };
2970
2971 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2972         .master         = &dra7xx_gmac_hwmod,
2973         .slave          = &dra7xx_mdio_hwmod,
2974         .user           = OCP_USER_MPU,
2975 };
2976
2977 /* l4_wkup -> dcan1 */
2978 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2979         .master         = &dra7xx_l4_wkup_hwmod,
2980         .slave          = &dra7xx_dcan1_hwmod,
2981         .clk            = "wkupaon_iclk_mux",
2982         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2983 };
2984
2985 /* l4_per2 -> dcan2 */
2986 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2987         .master         = &dra7xx_l4_per2_hwmod,
2988         .slave          = &dra7xx_dcan2_hwmod,
2989         .clk            = "l3_iclk_div",
2990         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2991 };
2992
2993 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2994         {
2995                 .pa_start       = 0x4a056000,
2996                 .pa_end         = 0x4a056fff,
2997                 .flags          = ADDR_TYPE_RT
2998         },
2999         { }
3000 };
3001
3002 /* l4_cfg -> dma_system */
3003 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3004         .master         = &dra7xx_l4_cfg_hwmod,
3005         .slave          = &dra7xx_dma_system_hwmod,
3006         .clk            = "l3_iclk_div",
3007         .addr           = dra7xx_dma_system_addrs,
3008         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3009 };
3010
3011 /* l3_main_1 -> tpcc */
3012 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
3013         .master         = &dra7xx_l3_main_1_hwmod,
3014         .slave          = &dra7xx_tpcc_hwmod,
3015         .clk            = "l3_iclk_div",
3016         .user           = OCP_USER_MPU,
3017 };
3018
3019 /* l3_main_1 -> tptc0 */
3020 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
3021         .master         = &dra7xx_l3_main_1_hwmod,
3022         .slave          = &dra7xx_tptc0_hwmod,
3023         .clk            = "l3_iclk_div",
3024         .user           = OCP_USER_MPU,
3025 };
3026
3027 /* l3_main_1 -> tptc1 */
3028 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
3029         .master         = &dra7xx_l3_main_1_hwmod,
3030         .slave          = &dra7xx_tptc1_hwmod,
3031         .clk            = "l3_iclk_div",
3032         .user           = OCP_USER_MPU,
3033 };
3034
3035 /* l3_main_1 -> dss */
3036 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3037         .master         = &dra7xx_l3_main_1_hwmod,
3038         .slave          = &dra7xx_dss_hwmod,
3039         .clk            = "l3_iclk_div",
3040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3041 };
3042
3043 /* l3_main_1 -> dispc */
3044 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3045         .master         = &dra7xx_l3_main_1_hwmod,
3046         .slave          = &dra7xx_dss_dispc_hwmod,
3047         .clk            = "l3_iclk_div",
3048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3049 };
3050
3051 /* l3_main_1 -> dispc */
3052 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3053         .master         = &dra7xx_l3_main_1_hwmod,
3054         .slave          = &dra7xx_dss_hdmi_hwmod,
3055         .clk            = "l3_iclk_div",
3056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3057 };
3058
3059 /* l3_main_1 -> aes1 */
3060 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3061         .master         = &dra7xx_l3_main_1_hwmod,
3062         .slave          = &dra7xx_aes1_hwmod,
3063         .clk            = "l3_iclk_div",
3064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3065 };
3066
3067 /* l3_main_1 -> aes2 */
3068 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3069         .master         = &dra7xx_l3_main_1_hwmod,
3070         .slave          = &dra7xx_aes2_hwmod,
3071         .clk            = "l3_iclk_div",
3072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3073 };
3074
3075 /* l3_main_1 -> sha0 */
3076 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3077         .master         = &dra7xx_l3_main_1_hwmod,
3078         .slave          = &dra7xx_sha0_hwmod,
3079         .clk            = "l3_iclk_div",
3080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3081 };
3082
3083 /* l4_per2 -> mcasp1 */
3084 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3085         .master         = &dra7xx_l4_per2_hwmod,
3086         .slave          = &dra7xx_mcasp1_hwmod,
3087         .clk            = "l4_root_clk_div",
3088         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3089 };
3090
3091 /* l3_main_1 -> mcasp1 */
3092 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3093         .master         = &dra7xx_l3_main_1_hwmod,
3094         .slave          = &dra7xx_mcasp1_hwmod,
3095         .clk            = "l3_iclk_div",
3096         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3097 };
3098
3099 /* l4_per2 -> mcasp2 */
3100 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3101         .master         = &dra7xx_l4_per2_hwmod,
3102         .slave          = &dra7xx_mcasp2_hwmod,
3103         .clk            = "l4_root_clk_div",
3104         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3105 };
3106
3107 /* l3_main_1 -> mcasp2 */
3108 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3109         .master         = &dra7xx_l3_main_1_hwmod,
3110         .slave          = &dra7xx_mcasp2_hwmod,
3111         .clk            = "l3_iclk_div",
3112         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3113 };
3114
3115 /* l4_per2 -> mcasp3 */
3116 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3117         .master         = &dra7xx_l4_per2_hwmod,
3118         .slave          = &dra7xx_mcasp3_hwmod,
3119         .clk            = "l4_root_clk_div",
3120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3121 };
3122
3123 /* l3_main_1 -> mcasp3 */
3124 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3125         .master         = &dra7xx_l3_main_1_hwmod,
3126         .slave          = &dra7xx_mcasp3_hwmod,
3127         .clk            = "l3_iclk_div",
3128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3129 };
3130
3131 /* l4_per2 -> mcasp4 */
3132 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3133         .master         = &dra7xx_l4_per2_hwmod,
3134         .slave          = &dra7xx_mcasp4_hwmod,
3135         .clk            = "l4_root_clk_div",
3136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3137 };
3138
3139 /* l4_per2 -> mcasp5 */
3140 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3141         .master         = &dra7xx_l4_per2_hwmod,
3142         .slave          = &dra7xx_mcasp5_hwmod,
3143         .clk            = "l4_root_clk_div",
3144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3145 };
3146
3147 /* l4_per2 -> mcasp6 */
3148 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3149         .master         = &dra7xx_l4_per2_hwmod,
3150         .slave          = &dra7xx_mcasp6_hwmod,
3151         .clk            = "l4_root_clk_div",
3152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3153 };
3154
3155 /* l4_per2 -> mcasp7 */
3156 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3157         .master         = &dra7xx_l4_per2_hwmod,
3158         .slave          = &dra7xx_mcasp7_hwmod,
3159         .clk            = "l4_root_clk_div",
3160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3161 };
3162
3163 /* l4_per2 -> mcasp8 */
3164 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3165         .master         = &dra7xx_l4_per2_hwmod,
3166         .slave          = &dra7xx_mcasp8_hwmod,
3167         .clk            = "l4_root_clk_div",
3168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3169 };
3170
3171 /* l4_per1 -> elm */
3172 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3173         .master         = &dra7xx_l4_per1_hwmod,
3174         .slave          = &dra7xx_elm_hwmod,
3175         .clk            = "l3_iclk_div",
3176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3177 };
3178
3179 /* l4_wkup -> gpio1 */
3180 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3181         .master         = &dra7xx_l4_wkup_hwmod,
3182         .slave          = &dra7xx_gpio1_hwmod,
3183         .clk            = "wkupaon_iclk_mux",
3184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3185 };
3186
3187 /* l4_per1 -> gpio2 */
3188 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3189         .master         = &dra7xx_l4_per1_hwmod,
3190         .slave          = &dra7xx_gpio2_hwmod,
3191         .clk            = "l3_iclk_div",
3192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3193 };
3194
3195 /* l4_per1 -> gpio3 */
3196 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3197         .master         = &dra7xx_l4_per1_hwmod,
3198         .slave          = &dra7xx_gpio3_hwmod,
3199         .clk            = "l3_iclk_div",
3200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3201 };
3202
3203 /* l4_per1 -> gpio4 */
3204 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3205         .master         = &dra7xx_l4_per1_hwmod,
3206         .slave          = &dra7xx_gpio4_hwmod,
3207         .clk            = "l3_iclk_div",
3208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3209 };
3210
3211 /* l4_per1 -> gpio5 */
3212 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3213         .master         = &dra7xx_l4_per1_hwmod,
3214         .slave          = &dra7xx_gpio5_hwmod,
3215         .clk            = "l3_iclk_div",
3216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3217 };
3218
3219 /* l4_per1 -> gpio6 */
3220 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3221         .master         = &dra7xx_l4_per1_hwmod,
3222         .slave          = &dra7xx_gpio6_hwmod,
3223         .clk            = "l3_iclk_div",
3224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3225 };
3226
3227 /* l4_per1 -> gpio7 */
3228 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3229         .master         = &dra7xx_l4_per1_hwmod,
3230         .slave          = &dra7xx_gpio7_hwmod,
3231         .clk            = "l3_iclk_div",
3232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3233 };
3234
3235 /* l4_per1 -> gpio8 */
3236 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3237         .master         = &dra7xx_l4_per1_hwmod,
3238         .slave          = &dra7xx_gpio8_hwmod,
3239         .clk            = "l3_iclk_div",
3240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3241 };
3242
3243 /* l3_main_1 -> gpmc */
3244 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3245         .master         = &dra7xx_l3_main_1_hwmod,
3246         .slave          = &dra7xx_gpmc_hwmod,
3247         .clk            = "l3_iclk_div",
3248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3249 };
3250
3251 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3252         {
3253                 .pa_start       = 0x480b2000,
3254                 .pa_end         = 0x480b201f,
3255                 .flags          = ADDR_TYPE_RT
3256         },
3257         { }
3258 };
3259
3260 /* l4_per1 -> hdq1w */
3261 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3262         .master         = &dra7xx_l4_per1_hwmod,
3263         .slave          = &dra7xx_hdq1w_hwmod,
3264         .clk            = "l3_iclk_div",
3265         .addr           = dra7xx_hdq1w_addrs,
3266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3267 };
3268
3269 /* l4_per1 -> i2c1 */
3270 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3271         .master         = &dra7xx_l4_per1_hwmod,
3272         .slave          = &dra7xx_i2c1_hwmod,
3273         .clk            = "l3_iclk_div",
3274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3275 };
3276
3277 /* l4_per1 -> i2c2 */
3278 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3279         .master         = &dra7xx_l4_per1_hwmod,
3280         .slave          = &dra7xx_i2c2_hwmod,
3281         .clk            = "l3_iclk_div",
3282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3283 };
3284
3285 /* l4_per1 -> i2c3 */
3286 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3287         .master         = &dra7xx_l4_per1_hwmod,
3288         .slave          = &dra7xx_i2c3_hwmod,
3289         .clk            = "l3_iclk_div",
3290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3291 };
3292
3293 /* l4_per1 -> i2c4 */
3294 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3295         .master         = &dra7xx_l4_per1_hwmod,
3296         .slave          = &dra7xx_i2c4_hwmod,
3297         .clk            = "l3_iclk_div",
3298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3299 };
3300
3301 /* l4_per1 -> i2c5 */
3302 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3303         .master         = &dra7xx_l4_per1_hwmod,
3304         .slave          = &dra7xx_i2c5_hwmod,
3305         .clk            = "l3_iclk_div",
3306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3307 };
3308
3309 /* l4_cfg -> mailbox1 */
3310 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3311         .master         = &dra7xx_l4_cfg_hwmod,
3312         .slave          = &dra7xx_mailbox1_hwmod,
3313         .clk            = "l3_iclk_div",
3314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3315 };
3316
3317 /* l4_per3 -> mailbox2 */
3318 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3319         .master         = &dra7xx_l4_per3_hwmod,
3320         .slave          = &dra7xx_mailbox2_hwmod,
3321         .clk            = "l3_iclk_div",
3322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3323 };
3324
3325 /* l4_per3 -> mailbox3 */
3326 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3327         .master         = &dra7xx_l4_per3_hwmod,
3328         .slave          = &dra7xx_mailbox3_hwmod,
3329         .clk            = "l3_iclk_div",
3330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3331 };
3332
3333 /* l4_per3 -> mailbox4 */
3334 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3335         .master         = &dra7xx_l4_per3_hwmod,
3336         .slave          = &dra7xx_mailbox4_hwmod,
3337         .clk            = "l3_iclk_div",
3338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3339 };
3340
3341 /* l4_per3 -> mailbox5 */
3342 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3343         .master         = &dra7xx_l4_per3_hwmod,
3344         .slave          = &dra7xx_mailbox5_hwmod,
3345         .clk            = "l3_iclk_div",
3346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3347 };
3348
3349 /* l4_per3 -> mailbox6 */
3350 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3351         .master         = &dra7xx_l4_per3_hwmod,
3352         .slave          = &dra7xx_mailbox6_hwmod,
3353         .clk            = "l3_iclk_div",
3354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3355 };
3356
3357 /* l4_per3 -> mailbox7 */
3358 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3359         .master         = &dra7xx_l4_per3_hwmod,
3360         .slave          = &dra7xx_mailbox7_hwmod,
3361         .clk            = "l3_iclk_div",
3362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3363 };
3364
3365 /* l4_per3 -> mailbox8 */
3366 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3367         .master         = &dra7xx_l4_per3_hwmod,
3368         .slave          = &dra7xx_mailbox8_hwmod,
3369         .clk            = "l3_iclk_div",
3370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3371 };
3372
3373 /* l4_per3 -> mailbox9 */
3374 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3375         .master         = &dra7xx_l4_per3_hwmod,
3376         .slave          = &dra7xx_mailbox9_hwmod,
3377         .clk            = "l3_iclk_div",
3378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3379 };
3380
3381 /* l4_per3 -> mailbox10 */
3382 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3383         .master         = &dra7xx_l4_per3_hwmod,
3384         .slave          = &dra7xx_mailbox10_hwmod,
3385         .clk            = "l3_iclk_div",
3386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3387 };
3388
3389 /* l4_per3 -> mailbox11 */
3390 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3391         .master         = &dra7xx_l4_per3_hwmod,
3392         .slave          = &dra7xx_mailbox11_hwmod,
3393         .clk            = "l3_iclk_div",
3394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3395 };
3396
3397 /* l4_per3 -> mailbox12 */
3398 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3399         .master         = &dra7xx_l4_per3_hwmod,
3400         .slave          = &dra7xx_mailbox12_hwmod,
3401         .clk            = "l3_iclk_div",
3402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3403 };
3404
3405 /* l4_per3 -> mailbox13 */
3406 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3407         .master         = &dra7xx_l4_per3_hwmod,
3408         .slave          = &dra7xx_mailbox13_hwmod,
3409         .clk            = "l3_iclk_div",
3410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3411 };
3412
3413 /* l4_per1 -> mcspi1 */
3414 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3415         .master         = &dra7xx_l4_per1_hwmod,
3416         .slave          = &dra7xx_mcspi1_hwmod,
3417         .clk            = "l3_iclk_div",
3418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3419 };
3420
3421 /* l4_per1 -> mcspi2 */
3422 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3423         .master         = &dra7xx_l4_per1_hwmod,
3424         .slave          = &dra7xx_mcspi2_hwmod,
3425         .clk            = "l3_iclk_div",
3426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3427 };
3428
3429 /* l4_per1 -> mcspi3 */
3430 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3431         .master         = &dra7xx_l4_per1_hwmod,
3432         .slave          = &dra7xx_mcspi3_hwmod,
3433         .clk            = "l3_iclk_div",
3434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3435 };
3436
3437 /* l4_per1 -> mcspi4 */
3438 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3439         .master         = &dra7xx_l4_per1_hwmod,
3440         .slave          = &dra7xx_mcspi4_hwmod,
3441         .clk            = "l3_iclk_div",
3442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3443 };
3444
3445 /* l4_per1 -> mmc1 */
3446 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3447         .master         = &dra7xx_l4_per1_hwmod,
3448         .slave          = &dra7xx_mmc1_hwmod,
3449         .clk            = "l3_iclk_div",
3450         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3451 };
3452
3453 /* l4_per1 -> mmc2 */
3454 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3455         .master         = &dra7xx_l4_per1_hwmod,
3456         .slave          = &dra7xx_mmc2_hwmod,
3457         .clk            = "l3_iclk_div",
3458         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3459 };
3460
3461 /* l4_per1 -> mmc3 */
3462 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3463         .master         = &dra7xx_l4_per1_hwmod,
3464         .slave          = &dra7xx_mmc3_hwmod,
3465         .clk            = "l3_iclk_div",
3466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3467 };
3468
3469 /* l4_per1 -> mmc4 */
3470 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3471         .master         = &dra7xx_l4_per1_hwmod,
3472         .slave          = &dra7xx_mmc4_hwmod,
3473         .clk            = "l3_iclk_div",
3474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3475 };
3476
3477 /* l4_cfg -> mpu */
3478 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3479         .master         = &dra7xx_l4_cfg_hwmod,
3480         .slave          = &dra7xx_mpu_hwmod,
3481         .clk            = "l3_iclk_div",
3482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3483 };
3484
3485 /* l4_cfg -> ocp2scp1 */
3486 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3487         .master         = &dra7xx_l4_cfg_hwmod,
3488         .slave          = &dra7xx_ocp2scp1_hwmod,
3489         .clk            = "l4_root_clk_div",
3490         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3491 };
3492
3493 /* l4_cfg -> ocp2scp3 */
3494 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3495         .master         = &dra7xx_l4_cfg_hwmod,
3496         .slave          = &dra7xx_ocp2scp3_hwmod,
3497         .clk            = "l4_root_clk_div",
3498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3499 };
3500
3501 /* l3_main_1 -> pciess1 */
3502 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3503         .master         = &dra7xx_l3_main_1_hwmod,
3504         .slave          = &dra7xx_pciess1_hwmod,
3505         .clk            = "l3_iclk_div",
3506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3507 };
3508
3509 /* l4_cfg -> pciess1 */
3510 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3511         .master         = &dra7xx_l4_cfg_hwmod,
3512         .slave          = &dra7xx_pciess1_hwmod,
3513         .clk            = "l4_root_clk_div",
3514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3515 };
3516
3517 /* l3_main_1 -> pciess2 */
3518 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3519         .master         = &dra7xx_l3_main_1_hwmod,
3520         .slave          = &dra7xx_pciess2_hwmod,
3521         .clk            = "l3_iclk_div",
3522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3523 };
3524
3525 /* l4_cfg -> pciess2 */
3526 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3527         .master         = &dra7xx_l4_cfg_hwmod,
3528         .slave          = &dra7xx_pciess2_hwmod,
3529         .clk            = "l4_root_clk_div",
3530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3531 };
3532
3533 /* l3_main_1 -> qspi */
3534 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3535         .master         = &dra7xx_l3_main_1_hwmod,
3536         .slave          = &dra7xx_qspi_hwmod,
3537         .clk            = "l3_iclk_div",
3538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3539 };
3540
3541 /* l4_per3 -> rtcss */
3542 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3543         .master         = &dra7xx_l4_per3_hwmod,
3544         .slave          = &dra7xx_rtcss_hwmod,
3545         .clk            = "l4_root_clk_div",
3546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3547 };
3548
3549 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3550         {
3551                 .name           = "sysc",
3552                 .pa_start       = 0x4a141100,
3553                 .pa_end         = 0x4a141107,
3554                 .flags          = ADDR_TYPE_RT
3555         },
3556         { }
3557 };
3558
3559 /* l4_cfg -> sata */
3560 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3561         .master         = &dra7xx_l4_cfg_hwmod,
3562         .slave          = &dra7xx_sata_hwmod,
3563         .clk            = "l3_iclk_div",
3564         .addr           = dra7xx_sata_addrs,
3565         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3566 };
3567
3568 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3569         {
3570                 .pa_start       = 0x4a0dd000,
3571                 .pa_end         = 0x4a0dd07f,
3572                 .flags          = ADDR_TYPE_RT
3573         },
3574         { }
3575 };
3576
3577 /* l4_cfg -> smartreflex_core */
3578 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3579         .master         = &dra7xx_l4_cfg_hwmod,
3580         .slave          = &dra7xx_smartreflex_core_hwmod,
3581         .clk            = "l4_root_clk_div",
3582         .addr           = dra7xx_smartreflex_core_addrs,
3583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3584 };
3585
3586 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3587         {
3588                 .pa_start       = 0x4a0d9000,
3589                 .pa_end         = 0x4a0d907f,
3590                 .flags          = ADDR_TYPE_RT
3591         },
3592         { }
3593 };
3594
3595 /* l4_cfg -> smartreflex_mpu */
3596 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3597         .master         = &dra7xx_l4_cfg_hwmod,
3598         .slave          = &dra7xx_smartreflex_mpu_hwmod,
3599         .clk            = "l4_root_clk_div",
3600         .addr           = dra7xx_smartreflex_mpu_addrs,
3601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3602 };
3603
3604 /* l4_cfg -> spinlock */
3605 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3606         .master         = &dra7xx_l4_cfg_hwmod,
3607         .slave          = &dra7xx_spinlock_hwmod,
3608         .clk            = "l3_iclk_div",
3609         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3610 };
3611
3612 /* l4_wkup -> timer1 */
3613 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3614         .master         = &dra7xx_l4_wkup_hwmod,
3615         .slave          = &dra7xx_timer1_hwmod,
3616         .clk            = "wkupaon_iclk_mux",
3617         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3618 };
3619
3620 /* l4_per1 -> timer2 */
3621 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3622         .master         = &dra7xx_l4_per1_hwmod,
3623         .slave          = &dra7xx_timer2_hwmod,
3624         .clk            = "l3_iclk_div",
3625         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3626 };
3627
3628 /* l4_per1 -> timer3 */
3629 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3630         .master         = &dra7xx_l4_per1_hwmod,
3631         .slave          = &dra7xx_timer3_hwmod,
3632         .clk            = "l3_iclk_div",
3633         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3634 };
3635
3636 /* l4_per1 -> timer4 */
3637 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3638         .master         = &dra7xx_l4_per1_hwmod,
3639         .slave          = &dra7xx_timer4_hwmod,
3640         .clk            = "l3_iclk_div",
3641         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3642 };
3643
3644 /* l4_per3 -> timer5 */
3645 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3646         .master         = &dra7xx_l4_per3_hwmod,
3647         .slave          = &dra7xx_timer5_hwmod,
3648         .clk            = "l3_iclk_div",
3649         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3650 };
3651
3652 /* l4_per3 -> timer6 */
3653 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3654         .master         = &dra7xx_l4_per3_hwmod,
3655         .slave          = &dra7xx_timer6_hwmod,
3656         .clk            = "l3_iclk_div",
3657         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3658 };
3659
3660 /* l4_per3 -> timer7 */
3661 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3662         .master         = &dra7xx_l4_per3_hwmod,
3663         .slave          = &dra7xx_timer7_hwmod,
3664         .clk            = "l3_iclk_div",
3665         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3666 };
3667
3668 /* l4_per3 -> timer8 */
3669 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3670         .master         = &dra7xx_l4_per3_hwmod,
3671         .slave          = &dra7xx_timer8_hwmod,
3672         .clk            = "l3_iclk_div",
3673         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3674 };
3675
3676 /* l4_per1 -> timer9 */
3677 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3678         .master         = &dra7xx_l4_per1_hwmod,
3679         .slave          = &dra7xx_timer9_hwmod,
3680         .clk            = "l3_iclk_div",
3681         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3682 };
3683
3684 /* l4_per1 -> timer10 */
3685 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3686         .master         = &dra7xx_l4_per1_hwmod,
3687         .slave          = &dra7xx_timer10_hwmod,
3688         .clk            = "l3_iclk_div",
3689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3690 };
3691
3692 /* l4_per1 -> timer11 */
3693 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3694         .master         = &dra7xx_l4_per1_hwmod,
3695         .slave          = &dra7xx_timer11_hwmod,
3696         .clk            = "l3_iclk_div",
3697         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3698 };
3699
3700 /* l4_wkup -> timer12 */
3701 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3702         .master         = &dra7xx_l4_wkup_hwmod,
3703         .slave          = &dra7xx_timer12_hwmod,
3704         .clk            = "wkupaon_iclk_mux",
3705         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3706 };
3707
3708 /* l4_per3 -> timer13 */
3709 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3710         .master         = &dra7xx_l4_per3_hwmod,
3711         .slave          = &dra7xx_timer13_hwmod,
3712         .clk            = "l3_iclk_div",
3713         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3714 };
3715
3716 /* l4_per3 -> timer14 */
3717 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3718         .master         = &dra7xx_l4_per3_hwmod,
3719         .slave          = &dra7xx_timer14_hwmod,
3720         .clk            = "l3_iclk_div",
3721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3722 };
3723
3724 /* l4_per3 -> timer15 */
3725 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3726         .master         = &dra7xx_l4_per3_hwmod,
3727         .slave          = &dra7xx_timer15_hwmod,
3728         .clk            = "l3_iclk_div",
3729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3730 };
3731
3732 /* l4_per3 -> timer16 */
3733 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3734         .master         = &dra7xx_l4_per3_hwmod,
3735         .slave          = &dra7xx_timer16_hwmod,
3736         .clk            = "l3_iclk_div",
3737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3738 };
3739
3740 /* l4_per1 -> uart1 */
3741 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3742         .master         = &dra7xx_l4_per1_hwmod,
3743         .slave          = &dra7xx_uart1_hwmod,
3744         .clk            = "l3_iclk_div",
3745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3746 };
3747
3748 /* l4_per1 -> uart2 */
3749 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3750         .master         = &dra7xx_l4_per1_hwmod,
3751         .slave          = &dra7xx_uart2_hwmod,
3752         .clk            = "l3_iclk_div",
3753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3754 };
3755
3756 /* l4_per1 -> uart3 */
3757 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3758         .master         = &dra7xx_l4_per1_hwmod,
3759         .slave          = &dra7xx_uart3_hwmod,
3760         .clk            = "l3_iclk_div",
3761         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3762 };
3763
3764 /* l4_per1 -> uart4 */
3765 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3766         .master         = &dra7xx_l4_per1_hwmod,
3767         .slave          = &dra7xx_uart4_hwmod,
3768         .clk            = "l3_iclk_div",
3769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3770 };
3771
3772 /* l4_per1 -> uart5 */
3773 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3774         .master         = &dra7xx_l4_per1_hwmod,
3775         .slave          = &dra7xx_uart5_hwmod,
3776         .clk            = "l3_iclk_div",
3777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3778 };
3779
3780 /* l4_per1 -> uart6 */
3781 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3782         .master         = &dra7xx_l4_per1_hwmod,
3783         .slave          = &dra7xx_uart6_hwmod,
3784         .clk            = "l3_iclk_div",
3785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3786 };
3787
3788 /* l4_per2 -> uart7 */
3789 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3790         .master         = &dra7xx_l4_per2_hwmod,
3791         .slave          = &dra7xx_uart7_hwmod,
3792         .clk            = "l3_iclk_div",
3793         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3794 };
3795
3796 /* l4_per1 -> des */
3797 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3798         .master         = &dra7xx_l4_per1_hwmod,
3799         .slave          = &dra7xx_des_hwmod,
3800         .clk            = "l3_iclk_div",
3801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3802 };
3803
3804 /* l4_per2 -> uart8 */
3805 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3806         .master         = &dra7xx_l4_per2_hwmod,
3807         .slave          = &dra7xx_uart8_hwmod,
3808         .clk            = "l3_iclk_div",
3809         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3810 };
3811
3812 /* l4_per2 -> uart9 */
3813 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3814         .master         = &dra7xx_l4_per2_hwmod,
3815         .slave          = &dra7xx_uart9_hwmod,
3816         .clk            = "l3_iclk_div",
3817         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3818 };
3819
3820 /* l4_wkup -> uart10 */
3821 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3822         .master         = &dra7xx_l4_wkup_hwmod,
3823         .slave          = &dra7xx_uart10_hwmod,
3824         .clk            = "wkupaon_iclk_mux",
3825         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3826 };
3827
3828 /* l4_per1 -> rng */
3829 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3830         .master         = &dra7xx_l4_per1_hwmod,
3831         .slave          = &dra7xx_rng_hwmod,
3832         .user           = OCP_USER_MPU,
3833 };
3834
3835 /* l4_per3 -> usb_otg_ss1 */
3836 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3837         .master         = &dra7xx_l4_per3_hwmod,
3838         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3839         .clk            = "dpll_core_h13x2_ck",
3840         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3841 };
3842
3843 /* l4_per3 -> usb_otg_ss2 */
3844 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3845         .master         = &dra7xx_l4_per3_hwmod,
3846         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3847         .clk            = "dpll_core_h13x2_ck",
3848         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3849 };
3850
3851 /* l4_per3 -> usb_otg_ss3 */
3852 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3853         .master         = &dra7xx_l4_per3_hwmod,
3854         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3855         .clk            = "dpll_core_h13x2_ck",
3856         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3857 };
3858
3859 /* l4_per3 -> usb_otg_ss4 */
3860 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3861         .master         = &dra7xx_l4_per3_hwmod,
3862         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3863         .clk            = "dpll_core_h13x2_ck",
3864         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3865 };
3866
3867 /* l3_main_1 -> vcp1 */
3868 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3869         .master         = &dra7xx_l3_main_1_hwmod,
3870         .slave          = &dra7xx_vcp1_hwmod,
3871         .clk            = "l3_iclk_div",
3872         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3873 };
3874
3875 /* l4_per2 -> vcp1 */
3876 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3877         .master         = &dra7xx_l4_per2_hwmod,
3878         .slave          = &dra7xx_vcp1_hwmod,
3879         .clk            = "l3_iclk_div",
3880         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3881 };
3882
3883 /* l3_main_1 -> vcp2 */
3884 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3885         .master         = &dra7xx_l3_main_1_hwmod,
3886         .slave          = &dra7xx_vcp2_hwmod,
3887         .clk            = "l3_iclk_div",
3888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3889 };
3890
3891 /* l4_per2 -> vcp2 */
3892 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3893         .master         = &dra7xx_l4_per2_hwmod,
3894         .slave          = &dra7xx_vcp2_hwmod,
3895         .clk            = "l3_iclk_div",
3896         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3897 };
3898
3899 /* l4_wkup -> wd_timer2 */
3900 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3901         .master         = &dra7xx_l4_wkup_hwmod,
3902         .slave          = &dra7xx_wd_timer2_hwmod,
3903         .clk            = "wkupaon_iclk_mux",
3904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3905 };
3906
3907 /* l4_per2 -> epwmss0 */
3908 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3909         .master         = &dra7xx_l4_per2_hwmod,
3910         .slave          = &dra7xx_epwmss0_hwmod,
3911         .clk            = "l4_root_clk_div",
3912         .user           = OCP_USER_MPU,
3913 };
3914
3915 /* l4_per2 -> epwmss1 */
3916 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3917         .master         = &dra7xx_l4_per2_hwmod,
3918         .slave          = &dra7xx_epwmss1_hwmod,
3919         .clk            = "l4_root_clk_div",
3920         .user           = OCP_USER_MPU,
3921 };
3922
3923 /* l4_per2 -> epwmss2 */
3924 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3925         .master         = &dra7xx_l4_per2_hwmod,
3926         .slave          = &dra7xx_epwmss2_hwmod,
3927         .clk            = "l4_root_clk_div",
3928         .user           = OCP_USER_MPU,
3929 };
3930
3931 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3932         &dra7xx_l3_main_1__dmm,
3933         &dra7xx_l3_main_2__l3_instr,
3934         &dra7xx_l4_cfg__l3_main_1,
3935         &dra7xx_mpu__l3_main_1,
3936         &dra7xx_l3_main_1__l3_main_2,
3937         &dra7xx_l4_cfg__l3_main_2,
3938         &dra7xx_l3_main_1__l4_cfg,
3939         &dra7xx_l3_main_1__l4_per1,
3940         &dra7xx_l3_main_1__l4_per2,
3941         &dra7xx_l3_main_1__l4_per3,
3942         &dra7xx_l3_main_1__l4_wkup,
3943         &dra7xx_l4_per2__atl,
3944         &dra7xx_l3_main_1__bb2d,
3945         &dra7xx_l4_wkup__counter_32k,
3946         &dra7xx_l4_wkup__ctrl_module_wkup,
3947         &dra7xx_l4_wkup__dcan1,
3948         &dra7xx_l4_per2__dcan2,
3949         &dra7xx_l4_per2__cpgmac0,
3950         &dra7xx_l4_per2__mcasp1,
3951         &dra7xx_l3_main_1__mcasp1,
3952         &dra7xx_l4_per2__mcasp2,
3953         &dra7xx_l3_main_1__mcasp2,
3954         &dra7xx_l4_per2__mcasp3,
3955         &dra7xx_l3_main_1__mcasp3,
3956         &dra7xx_l4_per2__mcasp4,
3957         &dra7xx_l4_per2__mcasp5,
3958         &dra7xx_l4_per2__mcasp6,
3959         &dra7xx_l4_per2__mcasp7,
3960         &dra7xx_l4_per2__mcasp8,
3961         &dra7xx_gmac__mdio,
3962         &dra7xx_l4_cfg__dma_system,
3963         &dra7xx_l3_main_1__tpcc,
3964         &dra7xx_l3_main_1__tptc0,
3965         &dra7xx_l3_main_1__tptc1,
3966         &dra7xx_l3_main_1__dss,
3967         &dra7xx_l3_main_1__dispc,
3968         &dra7xx_l3_main_1__hdmi,
3969         &dra7xx_l3_main_1__aes1,
3970         &dra7xx_l3_main_1__aes2,
3971         &dra7xx_l3_main_1__sha0,
3972         &dra7xx_l4_per1__elm,
3973         &dra7xx_l4_wkup__gpio1,
3974         &dra7xx_l4_per1__gpio2,
3975         &dra7xx_l4_per1__gpio3,
3976         &dra7xx_l4_per1__gpio4,
3977         &dra7xx_l4_per1__gpio5,
3978         &dra7xx_l4_per1__gpio6,
3979         &dra7xx_l4_per1__gpio7,
3980         &dra7xx_l4_per1__gpio8,
3981         &dra7xx_l3_main_1__gpmc,
3982         &dra7xx_l4_per1__hdq1w,
3983         &dra7xx_l4_per1__i2c1,
3984         &dra7xx_l4_per1__i2c2,
3985         &dra7xx_l4_per1__i2c3,
3986         &dra7xx_l4_per1__i2c4,
3987         &dra7xx_l4_per1__i2c5,
3988         &dra7xx_l4_cfg__mailbox1,
3989         &dra7xx_l4_per3__mailbox2,
3990         &dra7xx_l4_per3__mailbox3,
3991         &dra7xx_l4_per3__mailbox4,
3992         &dra7xx_l4_per3__mailbox5,
3993         &dra7xx_l4_per3__mailbox6,
3994         &dra7xx_l4_per3__mailbox7,
3995         &dra7xx_l4_per3__mailbox8,
3996         &dra7xx_l4_per3__mailbox9,
3997         &dra7xx_l4_per3__mailbox10,
3998         &dra7xx_l4_per3__mailbox11,
3999         &dra7xx_l4_per3__mailbox12,
4000         &dra7xx_l4_per3__mailbox13,
4001         &dra7xx_l4_per1__mcspi1,
4002         &dra7xx_l4_per1__mcspi2,
4003         &dra7xx_l4_per1__mcspi3,
4004         &dra7xx_l4_per1__mcspi4,
4005         &dra7xx_l4_per1__mmc1,
4006         &dra7xx_l4_per1__mmc2,
4007         &dra7xx_l4_per1__mmc3,
4008         &dra7xx_l4_per1__mmc4,
4009         &dra7xx_l4_cfg__mpu,
4010         &dra7xx_l4_cfg__ocp2scp1,
4011         &dra7xx_l4_cfg__ocp2scp3,
4012         &dra7xx_l3_main_1__pciess1,
4013         &dra7xx_l4_cfg__pciess1,
4014         &dra7xx_l3_main_1__pciess2,
4015         &dra7xx_l4_cfg__pciess2,
4016         &dra7xx_l3_main_1__qspi,
4017         &dra7xx_l4_cfg__sata,
4018         &dra7xx_l4_cfg__smartreflex_core,
4019         &dra7xx_l4_cfg__smartreflex_mpu,
4020         &dra7xx_l4_cfg__spinlock,
4021         &dra7xx_l4_wkup__timer1,
4022         &dra7xx_l4_per1__timer2,
4023         &dra7xx_l4_per1__timer3,
4024         &dra7xx_l4_per1__timer4,
4025         &dra7xx_l4_per3__timer5,
4026         &dra7xx_l4_per3__timer6,
4027         &dra7xx_l4_per3__timer7,
4028         &dra7xx_l4_per3__timer8,
4029         &dra7xx_l4_per1__timer9,
4030         &dra7xx_l4_per1__timer10,
4031         &dra7xx_l4_per1__timer11,
4032         &dra7xx_l4_per3__timer13,
4033         &dra7xx_l4_per3__timer14,
4034         &dra7xx_l4_per3__timer15,
4035         &dra7xx_l4_per3__timer16,
4036         &dra7xx_l4_per1__uart1,
4037         &dra7xx_l4_per1__uart2,
4038         &dra7xx_l4_per1__uart3,
4039         &dra7xx_l4_per1__uart4,
4040         &dra7xx_l4_per1__uart5,
4041         &dra7xx_l4_per1__uart6,
4042         &dra7xx_l4_per2__uart7,
4043         &dra7xx_l4_per2__uart8,
4044         &dra7xx_l4_per2__uart9,
4045         &dra7xx_l4_wkup__uart10,
4046         &dra7xx_l4_per1__des,
4047         &dra7xx_l4_per3__usb_otg_ss1,
4048         &dra7xx_l4_per3__usb_otg_ss2,
4049         &dra7xx_l4_per3__usb_otg_ss3,
4050         &dra7xx_l3_main_1__vcp1,
4051         &dra7xx_l4_per2__vcp1,
4052         &dra7xx_l3_main_1__vcp2,
4053         &dra7xx_l4_per2__vcp2,
4054         &dra7xx_l4_wkup__wd_timer2,
4055         &dra7xx_l4_per2__epwmss0,
4056         &dra7xx_l4_per2__epwmss1,
4057         &dra7xx_l4_per2__epwmss2,
4058         NULL,
4059 };
4060
4061 /* GP-only hwmod links */
4062 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
4063         &dra7xx_l4_wkup__timer12,
4064         &dra7xx_l4_per1__rng,
4065         NULL,
4066 };
4067
4068 /* SoC variant specific hwmod links */
4069 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4070         &dra7xx_l4_per3__usb_otg_ss4,
4071         NULL,
4072 };
4073
4074 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4075         NULL,
4076 };
4077
4078 static struct omap_hwmod_ocp_if *dra74x_dra72x_hwmod_ocp_ifs[] __initdata = {
4079         &dra7xx_l4_per3__rtcss,
4080         NULL,
4081 };
4082
4083 int __init dra7xx_hwmod_init(void)
4084 {
4085         int ret;
4086
4087         omap_hwmod_init();
4088         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4089
4090         if (!ret && soc_is_dra74x())
4091                 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4092         else if (!ret && soc_is_dra72x())
4093                 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4094
4095         if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4096                 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4097
4098         /* now for the IPs *NOT* in dra71 */
4099         if (!ret && !of_machine_is_compatible("ti,dra718"))
4100                 ret = omap_hwmod_register_links(dra74x_dra72x_hwmod_ocp_ifs);
4101
4102         return ret;
4103 }