2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 * Note that this file is currently not in sync with autogeneration scripts.
16 * The above note to be removed, once it is synced up.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/platform_data/gpio-omap.h>
25 #include <linux/power/smartreflex.h>
26 #include <linux/i2c-omap.h>
28 #include <linux/omap-dma.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
31 #include <linux/platform_data/asoc-ti-mcbsp.h>
32 #include <linux/platform_data/iommu-omap.h>
33 #include <plat/dmtimer.h>
35 #include "omap_hwmod.h"
36 #include "omap_hwmod_common_data.h"
40 #include "prm-regbits-44xx.h"
45 /* Base offset for all OMAP4 interrupts external to MPUSS */
46 #define OMAP44XX_IRQ_GIC_START 32
48 /* Base offset for all OMAP4 dma requests */
49 #define OMAP44XX_DMA_REQ_START 1
59 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
64 static struct omap_hwmod omap44xx_dmm_hwmod = {
66 .class = &omap44xx_dmm_hwmod_class,
67 .clkdm_name = "l3_emif_clkdm",
70 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
71 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
78 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
80 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
85 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
87 .class = &omap44xx_l3_hwmod_class,
88 .clkdm_name = "l3_instr_clkdm",
91 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
92 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
93 .modulemode = MODULEMODE_HWCTRL,
99 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
101 .class = &omap44xx_l3_hwmod_class,
102 .clkdm_name = "l3_1_clkdm",
105 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
106 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
112 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
114 .class = &omap44xx_l3_hwmod_class,
115 .clkdm_name = "l3_2_clkdm",
118 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
119 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
125 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
127 .class = &omap44xx_l3_hwmod_class,
128 .clkdm_name = "l3_instr_clkdm",
131 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
132 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
133 .modulemode = MODULEMODE_HWCTRL,
140 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
142 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
147 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
149 .class = &omap44xx_l4_hwmod_class,
150 .clkdm_name = "abe_clkdm",
153 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
154 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
155 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
156 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
162 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
164 .class = &omap44xx_l4_hwmod_class,
165 .clkdm_name = "l4_cfg_clkdm",
168 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
169 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
175 static struct omap_hwmod omap44xx_l4_per_hwmod = {
177 .class = &omap44xx_l4_hwmod_class,
178 .clkdm_name = "l4_per_clkdm",
181 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
182 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
188 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
190 .class = &omap44xx_l4_hwmod_class,
191 .clkdm_name = "l4_wkup_clkdm",
194 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
195 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
202 * instance(s): mpu_private
204 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
209 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
210 .name = "mpu_private",
211 .class = &omap44xx_mpu_bus_hwmod_class,
212 .clkdm_name = "mpuss_clkdm",
215 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
222 * instance(s): ocp_wp_noc
224 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
225 .name = "ocp_wp_noc",
229 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
230 .name = "ocp_wp_noc",
231 .class = &omap44xx_ocp_wp_noc_hwmod_class,
232 .clkdm_name = "l3_instr_clkdm",
235 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
236 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_HWCTRL,
243 * Modules omap_hwmod structures
245 * The following IPs are excluded for the moment because:
246 * - They do not need an explicit SW control using omap_hwmod API.
247 * - They still need to be validated with the driver
248 * properly adapted to omap_hwmod / omap_device
255 * audio engine sub system
258 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
261 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
262 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
263 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
264 MSTANDBY_SMART_WKUP),
265 .sysc_fields = &omap_hwmod_sysc_type2,
268 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
270 .sysc = &omap44xx_aess_sysc,
271 .enable_preprogram = omap_hwmod_aess_preprogram,
275 static struct omap_hwmod omap44xx_aess_hwmod = {
277 .class = &omap44xx_aess_hwmod_class,
278 .clkdm_name = "abe_clkdm",
279 .main_clk = "aess_fclk",
282 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
283 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
284 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
285 .modulemode = MODULEMODE_SWCTRL,
292 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
296 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
301 static struct omap_hwmod omap44xx_c2c_hwmod = {
303 .class = &omap44xx_c2c_hwmod_class,
304 .clkdm_name = "d2d_clkdm",
307 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
308 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
315 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
318 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
321 .sysc_flags = SYSC_HAS_SIDLEMODE,
322 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
323 .sysc_fields = &omap_hwmod_sysc_type1,
326 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
328 .sysc = &omap44xx_counter_sysc,
332 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
333 .name = "counter_32k",
334 .class = &omap44xx_counter_hwmod_class,
335 .clkdm_name = "l4_wkup_clkdm",
336 .flags = HWMOD_SWSUP_SIDLE,
337 .main_clk = "sys_32k_ck",
340 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
341 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
347 * 'ctrl_module' class
348 * attila core control module + core pad control module + wkup pad control
349 * module + attila wkup control module
352 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
355 .sysc_flags = SYSC_HAS_SIDLEMODE,
356 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
358 .sysc_fields = &omap_hwmod_sysc_type2,
361 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
362 .name = "ctrl_module",
363 .sysc = &omap44xx_ctrl_module_sysc,
366 /* ctrl_module_core */
367 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
368 .name = "ctrl_module_core",
369 .class = &omap44xx_ctrl_module_hwmod_class,
370 .clkdm_name = "l4_cfg_clkdm",
373 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
378 /* ctrl_module_pad_core */
379 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
380 .name = "ctrl_module_pad_core",
381 .class = &omap44xx_ctrl_module_hwmod_class,
382 .clkdm_name = "l4_cfg_clkdm",
385 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
390 /* ctrl_module_wkup */
391 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
392 .name = "ctrl_module_wkup",
393 .class = &omap44xx_ctrl_module_hwmod_class,
394 .clkdm_name = "l4_wkup_clkdm",
397 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
402 /* ctrl_module_pad_wkup */
403 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
404 .name = "ctrl_module_pad_wkup",
405 .class = &omap44xx_ctrl_module_hwmod_class,
406 .clkdm_name = "l4_wkup_clkdm",
409 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
416 * debug and emulation sub system
419 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
424 static struct omap_hwmod omap44xx_debugss_hwmod = {
426 .class = &omap44xx_debugss_hwmod_class,
427 .clkdm_name = "emu_sys_clkdm",
428 .main_clk = "trace_clk_div_ck",
431 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
432 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
439 * dma controller for data exchange between memory to memory (i.e. internal or
440 * external memory) and gp peripherals to memory or memory to gp peripherals
443 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
447 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
448 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
449 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
450 SYSS_HAS_RESET_STATUS),
451 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
452 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
453 .sysc_fields = &omap_hwmod_sysc_type1,
456 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
458 .sysc = &omap44xx_dma_sysc,
462 static struct omap_dma_dev_attr dma_dev_attr = {
463 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
464 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
469 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
470 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
471 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
472 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
473 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
477 static struct omap_hwmod omap44xx_dma_system_hwmod = {
478 .name = "dma_system",
479 .class = &omap44xx_dma_hwmod_class,
480 .clkdm_name = "l3_dma_clkdm",
481 .mpu_irqs = omap44xx_dma_system_irqs,
482 .main_clk = "l3_div_ck",
485 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
486 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
489 .dev_attr = &dma_dev_attr,
494 * digital microphone controller
497 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
500 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
501 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
504 .sysc_fields = &omap_hwmod_sysc_type2,
507 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
509 .sysc = &omap44xx_dmic_sysc,
513 static struct omap_hwmod omap44xx_dmic_hwmod = {
515 .class = &omap44xx_dmic_hwmod_class,
516 .clkdm_name = "abe_clkdm",
517 .main_clk = "func_dmic_abe_gfclk",
520 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
521 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
522 .modulemode = MODULEMODE_SWCTRL,
532 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
537 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
538 { .name = "dsp", .rst_shift = 0 },
541 static struct omap_hwmod omap44xx_dsp_hwmod = {
543 .class = &omap44xx_dsp_hwmod_class,
544 .clkdm_name = "tesla_clkdm",
545 .rst_lines = omap44xx_dsp_resets,
546 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
547 .main_clk = "dpll_iva_m4x2_ck",
550 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
551 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
552 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
553 .modulemode = MODULEMODE_HWCTRL,
563 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
566 .sysc_flags = SYSS_HAS_RESET_STATUS,
569 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
571 .sysc = &omap44xx_dss_sysc,
572 .reset = omap_dss_reset,
576 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
577 { .role = "sys_clk", .clk = "dss_sys_clk" },
578 { .role = "tv_clk", .clk = "dss_tv_clk" },
579 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
582 static struct omap_hwmod omap44xx_dss_hwmod = {
584 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
585 .class = &omap44xx_dss_hwmod_class,
586 .clkdm_name = "l3_dss_clkdm",
587 .main_clk = "dss_dss_clk",
590 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
591 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
594 .opt_clks = dss_opt_clks,
595 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
603 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
607 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
608 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
609 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
610 SYSS_HAS_RESET_STATUS),
611 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
612 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
613 .sysc_fields = &omap_hwmod_sysc_type1,
616 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
618 .sysc = &omap44xx_dispc_sysc,
622 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
623 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
627 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
628 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
632 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
634 .has_framedonetv_irq = 1
637 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
639 .class = &omap44xx_dispc_hwmod_class,
640 .clkdm_name = "l3_dss_clkdm",
641 .mpu_irqs = omap44xx_dss_dispc_irqs,
642 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
643 .main_clk = "dss_dss_clk",
646 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
647 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
650 .dev_attr = &omap44xx_dss_dispc_dev_attr
655 * display serial interface controller
658 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
662 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
663 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
664 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
665 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
666 .sysc_fields = &omap_hwmod_sysc_type1,
669 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
671 .sysc = &omap44xx_dsi_sysc,
675 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
676 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
680 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
681 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
685 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
686 { .role = "sys_clk", .clk = "dss_sys_clk" },
689 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
691 .class = &omap44xx_dsi_hwmod_class,
692 .clkdm_name = "l3_dss_clkdm",
693 .mpu_irqs = omap44xx_dss_dsi1_irqs,
694 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
695 .main_clk = "dss_dss_clk",
698 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
699 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
702 .opt_clks = dss_dsi1_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
707 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
708 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
712 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
713 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
717 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
718 { .role = "sys_clk", .clk = "dss_sys_clk" },
721 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
723 .class = &omap44xx_dsi_hwmod_class,
724 .clkdm_name = "l3_dss_clkdm",
725 .mpu_irqs = omap44xx_dss_dsi2_irqs,
726 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
727 .main_clk = "dss_dss_clk",
730 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
731 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
734 .opt_clks = dss_dsi2_opt_clks,
735 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
743 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
746 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
748 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
750 .sysc_fields = &omap_hwmod_sysc_type2,
753 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
755 .sysc = &omap44xx_hdmi_sysc,
759 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
760 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
764 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
765 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
769 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
770 { .role = "sys_clk", .clk = "dss_sys_clk" },
773 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
775 .class = &omap44xx_hdmi_hwmod_class,
776 .clkdm_name = "l3_dss_clkdm",
778 * HDMI audio requires to use no-idle mode. Hence,
779 * set idle mode by software.
781 .flags = HWMOD_SWSUP_SIDLE,
782 .mpu_irqs = omap44xx_dss_hdmi_irqs,
783 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
784 .main_clk = "dss_48mhz_clk",
787 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
788 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
791 .opt_clks = dss_hdmi_opt_clks,
792 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
797 * remote frame buffer interface
800 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
804 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
805 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
806 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
807 .sysc_fields = &omap_hwmod_sysc_type1,
810 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
812 .sysc = &omap44xx_rfbi_sysc,
816 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
817 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
821 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
822 { .role = "ick", .clk = "dss_fck" },
825 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
827 .class = &omap44xx_rfbi_hwmod_class,
828 .clkdm_name = "l3_dss_clkdm",
829 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
830 .main_clk = "dss_dss_clk",
833 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
834 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
837 .opt_clks = dss_rfbi_opt_clks,
838 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
846 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
851 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
853 .class = &omap44xx_venc_hwmod_class,
854 .clkdm_name = "l3_dss_clkdm",
855 .main_clk = "dss_tv_clk",
858 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
859 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
866 * bch error location module
869 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
873 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
874 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
875 SYSS_HAS_RESET_STATUS),
876 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
877 .sysc_fields = &omap_hwmod_sysc_type1,
880 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
882 .sysc = &omap44xx_elm_sysc,
886 static struct omap_hwmod omap44xx_elm_hwmod = {
888 .class = &omap44xx_elm_hwmod_class,
889 .clkdm_name = "l4_per_clkdm",
892 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
893 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
900 * external memory interface no1
903 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
907 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
909 .sysc = &omap44xx_emif_sysc,
913 static struct omap_hwmod omap44xx_emif1_hwmod = {
915 .class = &omap44xx_emif_hwmod_class,
916 .clkdm_name = "l3_emif_clkdm",
917 .flags = HWMOD_INIT_NO_IDLE,
918 .main_clk = "ddrphy_ck",
921 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
922 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
923 .modulemode = MODULEMODE_HWCTRL,
929 static struct omap_hwmod omap44xx_emif2_hwmod = {
931 .class = &omap44xx_emif_hwmod_class,
932 .clkdm_name = "l3_emif_clkdm",
933 .flags = HWMOD_INIT_NO_IDLE,
934 .main_clk = "ddrphy_ck",
937 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
938 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
939 .modulemode = MODULEMODE_HWCTRL,
946 * face detection hw accelerator module
949 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
953 * FDIF needs 100 OCP clk cycles delay after a softreset before
954 * accessing sysconfig again.
955 * The lowest frequency at the moment for L3 bus is 100 MHz, so
956 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
958 * TODO: Indicate errata when available.
961 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
962 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
963 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
964 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
965 .sysc_fields = &omap_hwmod_sysc_type2,
968 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
970 .sysc = &omap44xx_fdif_sysc,
974 static struct omap_hwmod omap44xx_fdif_hwmod = {
976 .class = &omap44xx_fdif_hwmod_class,
977 .clkdm_name = "iss_clkdm",
978 .main_clk = "fdif_fck",
981 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
982 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
983 .modulemode = MODULEMODE_SWCTRL,
990 * general purpose io module
993 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
997 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
998 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
999 SYSS_HAS_RESET_STATUS),
1000 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1002 .sysc_fields = &omap_hwmod_sysc_type1,
1005 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1007 .sysc = &omap44xx_gpio_sysc,
1012 static struct omap_gpio_dev_attr gpio_dev_attr = {
1018 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1019 { .role = "dbclk", .clk = "gpio1_dbclk" },
1022 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1024 .class = &omap44xx_gpio_hwmod_class,
1025 .clkdm_name = "l4_wkup_clkdm",
1026 .main_clk = "l4_wkup_clk_mux_ck",
1029 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1030 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1031 .modulemode = MODULEMODE_HWCTRL,
1034 .opt_clks = gpio1_opt_clks,
1035 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1036 .dev_attr = &gpio_dev_attr,
1040 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1041 { .role = "dbclk", .clk = "gpio2_dbclk" },
1044 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1046 .class = &omap44xx_gpio_hwmod_class,
1047 .clkdm_name = "l4_per_clkdm",
1048 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1049 .main_clk = "l4_div_ck",
1052 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1053 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1054 .modulemode = MODULEMODE_HWCTRL,
1057 .opt_clks = gpio2_opt_clks,
1058 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1059 .dev_attr = &gpio_dev_attr,
1063 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1064 { .role = "dbclk", .clk = "gpio3_dbclk" },
1067 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1069 .class = &omap44xx_gpio_hwmod_class,
1070 .clkdm_name = "l4_per_clkdm",
1071 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1072 .main_clk = "l4_div_ck",
1075 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1076 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1077 .modulemode = MODULEMODE_HWCTRL,
1080 .opt_clks = gpio3_opt_clks,
1081 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1082 .dev_attr = &gpio_dev_attr,
1086 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1087 { .role = "dbclk", .clk = "gpio4_dbclk" },
1090 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1092 .class = &omap44xx_gpio_hwmod_class,
1093 .clkdm_name = "l4_per_clkdm",
1094 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1095 .main_clk = "l4_div_ck",
1098 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1099 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1100 .modulemode = MODULEMODE_HWCTRL,
1103 .opt_clks = gpio4_opt_clks,
1104 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1105 .dev_attr = &gpio_dev_attr,
1109 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1110 { .role = "dbclk", .clk = "gpio5_dbclk" },
1113 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1115 .class = &omap44xx_gpio_hwmod_class,
1116 .clkdm_name = "l4_per_clkdm",
1117 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1118 .main_clk = "l4_div_ck",
1121 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1122 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1123 .modulemode = MODULEMODE_HWCTRL,
1126 .opt_clks = gpio5_opt_clks,
1127 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1128 .dev_attr = &gpio_dev_attr,
1132 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1133 { .role = "dbclk", .clk = "gpio6_dbclk" },
1136 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1138 .class = &omap44xx_gpio_hwmod_class,
1139 .clkdm_name = "l4_per_clkdm",
1140 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1141 .main_clk = "l4_div_ck",
1144 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1145 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1146 .modulemode = MODULEMODE_HWCTRL,
1149 .opt_clks = gpio6_opt_clks,
1150 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1151 .dev_attr = &gpio_dev_attr,
1156 * general purpose memory controller
1159 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1161 .sysc_offs = 0x0010,
1162 .syss_offs = 0x0014,
1163 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1164 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1165 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1166 .sysc_fields = &omap_hwmod_sysc_type1,
1169 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1171 .sysc = &omap44xx_gpmc_sysc,
1175 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1177 .class = &omap44xx_gpmc_hwmod_class,
1178 .clkdm_name = "l3_2_clkdm",
1180 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1181 * block. It is not being added due to any known bugs with
1182 * resetting the GPMC IP block, but rather because any timings
1183 * set by the bootloader are not being correctly programmed by
1184 * the kernel from the board file or DT data.
1185 * HWMOD_INIT_NO_RESET should be removed ASAP.
1187 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1190 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1191 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1192 .modulemode = MODULEMODE_HWCTRL,
1199 * 2d/3d graphics accelerator
1202 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1203 .rev_offs = 0x1fc00,
1204 .sysc_offs = 0x1fc10,
1205 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1206 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1207 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1208 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1209 .sysc_fields = &omap_hwmod_sysc_type2,
1212 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1214 .sysc = &omap44xx_gpu_sysc,
1218 static struct omap_hwmod omap44xx_gpu_hwmod = {
1220 .class = &omap44xx_gpu_hwmod_class,
1221 .clkdm_name = "l3_gfx_clkdm",
1222 .main_clk = "sgx_clk_mux",
1225 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1226 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1227 .modulemode = MODULEMODE_SWCTRL,
1234 * hdq / 1-wire serial interface controller
1237 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1239 .sysc_offs = 0x0014,
1240 .syss_offs = 0x0018,
1241 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1242 SYSS_HAS_RESET_STATUS),
1243 .sysc_fields = &omap_hwmod_sysc_type1,
1246 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1248 .sysc = &omap44xx_hdq1w_sysc,
1252 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1254 .class = &omap44xx_hdq1w_hwmod_class,
1255 .clkdm_name = "l4_per_clkdm",
1256 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1257 .main_clk = "func_12m_fclk",
1260 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1261 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1262 .modulemode = MODULEMODE_SWCTRL,
1269 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1273 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1275 .sysc_offs = 0x0010,
1276 .syss_offs = 0x0014,
1277 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1278 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1279 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1280 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1281 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1282 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1283 .sysc_fields = &omap_hwmod_sysc_type1,
1286 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1288 .sysc = &omap44xx_hsi_sysc,
1292 static struct omap_hwmod omap44xx_hsi_hwmod = {
1294 .class = &omap44xx_hsi_hwmod_class,
1295 .clkdm_name = "l3_init_clkdm",
1296 .main_clk = "hsi_fck",
1299 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1300 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1301 .modulemode = MODULEMODE_HWCTRL,
1308 * multimaster high-speed i2c controller
1311 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1312 .sysc_offs = 0x0010,
1313 .syss_offs = 0x0090,
1314 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1315 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1316 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1317 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1319 .clockact = CLOCKACT_TEST_ICLK,
1320 .sysc_fields = &omap_hwmod_sysc_type1,
1323 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1325 .sysc = &omap44xx_i2c_sysc,
1326 .rev = OMAP_I2C_IP_VERSION_2,
1327 .reset = &omap_i2c_reset,
1330 static struct omap_i2c_dev_attr i2c_dev_attr = {
1331 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1335 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1337 .class = &omap44xx_i2c_hwmod_class,
1338 .clkdm_name = "l4_per_clkdm",
1339 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1340 .main_clk = "func_96m_fclk",
1343 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1344 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1345 .modulemode = MODULEMODE_SWCTRL,
1348 .dev_attr = &i2c_dev_attr,
1352 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1354 .class = &omap44xx_i2c_hwmod_class,
1355 .clkdm_name = "l4_per_clkdm",
1356 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1357 .main_clk = "func_96m_fclk",
1360 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1361 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1362 .modulemode = MODULEMODE_SWCTRL,
1365 .dev_attr = &i2c_dev_attr,
1369 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1371 .class = &omap44xx_i2c_hwmod_class,
1372 .clkdm_name = "l4_per_clkdm",
1373 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1374 .main_clk = "func_96m_fclk",
1377 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1378 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1379 .modulemode = MODULEMODE_SWCTRL,
1382 .dev_attr = &i2c_dev_attr,
1386 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1388 .class = &omap44xx_i2c_hwmod_class,
1389 .clkdm_name = "l4_per_clkdm",
1390 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1391 .main_clk = "func_96m_fclk",
1394 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1395 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1396 .modulemode = MODULEMODE_SWCTRL,
1399 .dev_attr = &i2c_dev_attr,
1404 * imaging processor unit
1407 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1412 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1413 { .name = "cpu0", .rst_shift = 0 },
1414 { .name = "cpu1", .rst_shift = 1 },
1417 static struct omap_hwmod omap44xx_ipu_hwmod = {
1419 .class = &omap44xx_ipu_hwmod_class,
1420 .clkdm_name = "ducati_clkdm",
1421 .rst_lines = omap44xx_ipu_resets,
1422 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1423 .main_clk = "ducati_clk_mux_ck",
1426 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1427 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1428 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1429 .modulemode = MODULEMODE_HWCTRL,
1436 * external images sensor pixel data processor
1439 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1441 .sysc_offs = 0x0010,
1443 * ISS needs 100 OCP clk cycles delay after a softreset before
1444 * accessing sysconfig again.
1445 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1446 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1448 * TODO: Indicate errata when available.
1451 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1452 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1453 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1454 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1455 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1456 .sysc_fields = &omap_hwmod_sysc_type2,
1459 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1461 .sysc = &omap44xx_iss_sysc,
1465 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1466 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1469 static struct omap_hwmod omap44xx_iss_hwmod = {
1471 .class = &omap44xx_iss_hwmod_class,
1472 .clkdm_name = "iss_clkdm",
1473 .main_clk = "ducati_clk_mux_ck",
1476 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1477 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1478 .modulemode = MODULEMODE_SWCTRL,
1481 .opt_clks = iss_opt_clks,
1482 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1487 * multi-standard video encoder/decoder hardware accelerator
1490 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1495 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1496 { .name = "seq0", .rst_shift = 0 },
1497 { .name = "seq1", .rst_shift = 1 },
1498 { .name = "logic", .rst_shift = 2 },
1501 static struct omap_hwmod omap44xx_iva_hwmod = {
1503 .class = &omap44xx_iva_hwmod_class,
1504 .clkdm_name = "ivahd_clkdm",
1505 .rst_lines = omap44xx_iva_resets,
1506 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1507 .main_clk = "dpll_iva_m5x2_ck",
1510 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1511 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1512 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1513 .modulemode = MODULEMODE_HWCTRL,
1520 * keyboard controller
1523 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1525 .sysc_offs = 0x0010,
1526 .syss_offs = 0x0014,
1527 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1528 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1529 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1530 SYSS_HAS_RESET_STATUS),
1531 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1532 .sysc_fields = &omap_hwmod_sysc_type1,
1535 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1537 .sysc = &omap44xx_kbd_sysc,
1541 static struct omap_hwmod omap44xx_kbd_hwmod = {
1543 .class = &omap44xx_kbd_hwmod_class,
1544 .clkdm_name = "l4_wkup_clkdm",
1545 .main_clk = "sys_32k_ck",
1548 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1549 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1550 .modulemode = MODULEMODE_SWCTRL,
1557 * mailbox module allowing communication between the on-chip processors using a
1558 * queued mailbox-interrupt mechanism.
1561 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1563 .sysc_offs = 0x0010,
1564 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1565 SYSC_HAS_SOFTRESET),
1566 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1567 .sysc_fields = &omap_hwmod_sysc_type2,
1570 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1572 .sysc = &omap44xx_mailbox_sysc,
1576 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1578 .class = &omap44xx_mailbox_hwmod_class,
1579 .clkdm_name = "l4_cfg_clkdm",
1582 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1583 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1590 * multi-channel audio serial port controller
1593 /* The IP is not compliant to type1 / type2 scheme */
1594 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1598 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1599 .sysc_offs = 0x0004,
1600 .sysc_flags = SYSC_HAS_SIDLEMODE,
1601 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1603 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1606 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1608 .sysc = &omap44xx_mcasp_sysc,
1612 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1614 .class = &omap44xx_mcasp_hwmod_class,
1615 .clkdm_name = "abe_clkdm",
1616 .main_clk = "func_mcasp_abe_gfclk",
1619 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1620 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1621 .modulemode = MODULEMODE_SWCTRL,
1628 * multi channel buffered serial port controller
1631 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1632 .sysc_offs = 0x008c,
1633 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1634 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1635 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1636 .sysc_fields = &omap_hwmod_sysc_type1,
1639 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1641 .sysc = &omap44xx_mcbsp_sysc,
1642 .rev = MCBSP_CONFIG_TYPE4,
1646 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1647 { .role = "pad_fck", .clk = "pad_clks_ck" },
1648 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1651 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1653 .class = &omap44xx_mcbsp_hwmod_class,
1654 .clkdm_name = "abe_clkdm",
1655 .main_clk = "func_mcbsp1_gfclk",
1658 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1659 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1660 .modulemode = MODULEMODE_SWCTRL,
1663 .opt_clks = mcbsp1_opt_clks,
1664 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1668 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1669 { .role = "pad_fck", .clk = "pad_clks_ck" },
1670 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1673 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1675 .class = &omap44xx_mcbsp_hwmod_class,
1676 .clkdm_name = "abe_clkdm",
1677 .main_clk = "func_mcbsp2_gfclk",
1680 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1681 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1682 .modulemode = MODULEMODE_SWCTRL,
1685 .opt_clks = mcbsp2_opt_clks,
1686 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1690 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1691 { .role = "pad_fck", .clk = "pad_clks_ck" },
1692 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1695 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1697 .class = &omap44xx_mcbsp_hwmod_class,
1698 .clkdm_name = "abe_clkdm",
1699 .main_clk = "func_mcbsp3_gfclk",
1702 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1703 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1704 .modulemode = MODULEMODE_SWCTRL,
1707 .opt_clks = mcbsp3_opt_clks,
1708 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
1712 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1713 { .role = "pad_fck", .clk = "pad_clks_ck" },
1714 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1717 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1719 .class = &omap44xx_mcbsp_hwmod_class,
1720 .clkdm_name = "l4_per_clkdm",
1721 .main_clk = "per_mcbsp4_gfclk",
1724 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1725 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1726 .modulemode = MODULEMODE_SWCTRL,
1729 .opt_clks = mcbsp4_opt_clks,
1730 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
1735 * multi channel pdm controller (proprietary interface with phoenix power
1739 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1741 .sysc_offs = 0x0010,
1742 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1743 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1744 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1746 .sysc_fields = &omap_hwmod_sysc_type2,
1749 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1751 .sysc = &omap44xx_mcpdm_sysc,
1755 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1757 .class = &omap44xx_mcpdm_hwmod_class,
1758 .clkdm_name = "abe_clkdm",
1760 * It's suspected that the McPDM requires an off-chip main
1761 * functional clock, controlled via I2C. This IP block is
1762 * currently reset very early during boot, before I2C is
1763 * available, so it doesn't seem that we have any choice in
1764 * the kernel other than to avoid resetting it.
1766 * Also, McPDM needs to be configured to NO_IDLE mode when it
1767 * is in used otherwise vital clocks will be gated which
1768 * results 'slow motion' audio playback.
1770 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1771 .main_clk = "pad_clks_ck",
1774 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1775 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1776 .modulemode = MODULEMODE_SWCTRL,
1783 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1787 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1789 .sysc_offs = 0x0010,
1790 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1791 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1792 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1794 .sysc_fields = &omap_hwmod_sysc_type2,
1797 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1799 .sysc = &omap44xx_mcspi_sysc,
1800 .rev = OMAP4_MCSPI_REV,
1804 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1805 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1806 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1807 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1808 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1809 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1810 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1811 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1812 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1816 /* mcspi1 dev_attr */
1817 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1818 .num_chipselect = 4,
1821 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1823 .class = &omap44xx_mcspi_hwmod_class,
1824 .clkdm_name = "l4_per_clkdm",
1825 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
1826 .main_clk = "func_48m_fclk",
1829 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1830 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1831 .modulemode = MODULEMODE_SWCTRL,
1834 .dev_attr = &mcspi1_dev_attr,
1838 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1839 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1840 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1841 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1842 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1846 /* mcspi2 dev_attr */
1847 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1848 .num_chipselect = 2,
1851 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1853 .class = &omap44xx_mcspi_hwmod_class,
1854 .clkdm_name = "l4_per_clkdm",
1855 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
1856 .main_clk = "func_48m_fclk",
1859 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1860 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1861 .modulemode = MODULEMODE_SWCTRL,
1864 .dev_attr = &mcspi2_dev_attr,
1868 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1869 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1870 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1871 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1872 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1876 /* mcspi3 dev_attr */
1877 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1878 .num_chipselect = 2,
1881 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1883 .class = &omap44xx_mcspi_hwmod_class,
1884 .clkdm_name = "l4_per_clkdm",
1885 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
1886 .main_clk = "func_48m_fclk",
1889 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1890 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1891 .modulemode = MODULEMODE_SWCTRL,
1894 .dev_attr = &mcspi3_dev_attr,
1898 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1899 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1900 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1904 /* mcspi4 dev_attr */
1905 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1906 .num_chipselect = 1,
1909 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1911 .class = &omap44xx_mcspi_hwmod_class,
1912 .clkdm_name = "l4_per_clkdm",
1913 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
1914 .main_clk = "func_48m_fclk",
1917 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1918 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1919 .modulemode = MODULEMODE_SWCTRL,
1922 .dev_attr = &mcspi4_dev_attr,
1927 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1930 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1932 .sysc_offs = 0x0010,
1933 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1934 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1935 SYSC_HAS_SOFTRESET),
1936 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1937 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1938 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1939 .sysc_fields = &omap_hwmod_sysc_type2,
1942 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1944 .sysc = &omap44xx_mmc_sysc,
1948 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1949 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1950 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1955 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1956 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1959 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1961 .class = &omap44xx_mmc_hwmod_class,
1962 .clkdm_name = "l3_init_clkdm",
1963 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
1964 .main_clk = "hsmmc1_fclk",
1967 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1968 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1969 .modulemode = MODULEMODE_SWCTRL,
1972 .dev_attr = &mmc1_dev_attr,
1976 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1977 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1978 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1982 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1984 .class = &omap44xx_mmc_hwmod_class,
1985 .clkdm_name = "l3_init_clkdm",
1986 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
1987 .main_clk = "hsmmc2_fclk",
1990 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1991 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1992 .modulemode = MODULEMODE_SWCTRL,
1998 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
1999 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2000 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2004 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2006 .class = &omap44xx_mmc_hwmod_class,
2007 .clkdm_name = "l4_per_clkdm",
2008 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2009 .main_clk = "func_48m_fclk",
2012 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2013 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2014 .modulemode = MODULEMODE_SWCTRL,
2020 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2021 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2022 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2026 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2028 .class = &omap44xx_mmc_hwmod_class,
2029 .clkdm_name = "l4_per_clkdm",
2030 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2031 .main_clk = "func_48m_fclk",
2034 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2035 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2036 .modulemode = MODULEMODE_SWCTRL,
2042 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2043 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2044 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2048 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2050 .class = &omap44xx_mmc_hwmod_class,
2051 .clkdm_name = "l4_per_clkdm",
2052 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2053 .main_clk = "func_48m_fclk",
2056 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2057 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2058 .modulemode = MODULEMODE_SWCTRL,
2065 * The memory management unit performs virtual to physical address translation
2066 * for its requestors.
2069 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2073 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2074 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2075 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2076 .sysc_fields = &omap_hwmod_sysc_type1,
2079 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2086 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2088 .da_end = 0xfffff000,
2089 .nr_tlb_entries = 32,
2092 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2093 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2094 { .name = "mmu_cache", .rst_shift = 2 },
2097 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2099 .pa_start = 0x55082000,
2100 .pa_end = 0x550820ff,
2101 .flags = ADDR_TYPE_RT,
2106 /* l3_main_2 -> mmu_ipu */
2107 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2108 .master = &omap44xx_l3_main_2_hwmod,
2109 .slave = &omap44xx_mmu_ipu_hwmod,
2111 .addr = omap44xx_mmu_ipu_addrs,
2112 .user = OCP_USER_MPU | OCP_USER_SDMA,
2115 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2117 .class = &omap44xx_mmu_hwmod_class,
2118 .clkdm_name = "ducati_clkdm",
2119 .rst_lines = omap44xx_mmu_ipu_resets,
2120 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2121 .main_clk = "ducati_clk_mux_ck",
2124 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2125 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2126 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2127 .modulemode = MODULEMODE_HWCTRL,
2130 .dev_attr = &mmu_ipu_dev_attr,
2135 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2137 .da_end = 0xfffff000,
2138 .nr_tlb_entries = 32,
2141 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2142 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2143 { .name = "mmu_cache", .rst_shift = 1 },
2146 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2148 .pa_start = 0x4a066000,
2149 .pa_end = 0x4a0660ff,
2150 .flags = ADDR_TYPE_RT,
2156 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2157 .master = &omap44xx_l4_cfg_hwmod,
2158 .slave = &omap44xx_mmu_dsp_hwmod,
2160 .addr = omap44xx_mmu_dsp_addrs,
2161 .user = OCP_USER_MPU | OCP_USER_SDMA,
2164 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2166 .class = &omap44xx_mmu_hwmod_class,
2167 .clkdm_name = "tesla_clkdm",
2168 .rst_lines = omap44xx_mmu_dsp_resets,
2169 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2170 .main_clk = "dpll_iva_m4x2_ck",
2173 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2174 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2175 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2176 .modulemode = MODULEMODE_HWCTRL,
2179 .dev_attr = &mmu_dsp_dev_attr,
2187 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2192 static struct omap_hwmod omap44xx_mpu_hwmod = {
2194 .class = &omap44xx_mpu_hwmod_class,
2195 .clkdm_name = "mpuss_clkdm",
2196 .flags = HWMOD_INIT_NO_IDLE,
2197 .main_clk = "dpll_mpu_m2_ck",
2200 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2201 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2208 * top-level core on-chip ram
2211 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2216 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2218 .class = &omap44xx_ocmc_ram_hwmod_class,
2219 .clkdm_name = "l3_2_clkdm",
2222 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2223 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2230 * bridge to transform ocp interface protocol to scp (serial control port)
2234 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2236 .sysc_offs = 0x0010,
2237 .syss_offs = 0x0014,
2238 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2239 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2240 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2241 .sysc_fields = &omap_hwmod_sysc_type1,
2244 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2246 .sysc = &omap44xx_ocp2scp_sysc,
2249 /* ocp2scp_usb_phy */
2250 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2251 .name = "ocp2scp_usb_phy",
2252 .class = &omap44xx_ocp2scp_hwmod_class,
2253 .clkdm_name = "l3_init_clkdm",
2255 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2256 * block as an "optional clock," and normally should never be
2257 * specified as the main_clk for an OMAP IP block. However it
2258 * turns out that this clock is actually the main clock for
2259 * the ocp2scp_usb_phy IP block:
2260 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2261 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2262 * to be the best workaround.
2264 .main_clk = "ocp2scp_usb_phy_phy_48m",
2267 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2268 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2269 .modulemode = MODULEMODE_HWCTRL,
2276 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2277 * + clock manager 1 (in always on power domain) + local prm in mpu
2280 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2285 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2287 .class = &omap44xx_prcm_hwmod_class,
2288 .clkdm_name = "l4_wkup_clkdm",
2289 .flags = HWMOD_NO_IDLEST,
2292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2298 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2299 .name = "cm_core_aon",
2300 .class = &omap44xx_prcm_hwmod_class,
2301 .flags = HWMOD_NO_IDLEST,
2304 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2310 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2312 .class = &omap44xx_prcm_hwmod_class,
2313 .flags = HWMOD_NO_IDLEST,
2316 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2322 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2323 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2324 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2327 static struct omap_hwmod omap44xx_prm_hwmod = {
2329 .class = &omap44xx_prcm_hwmod_class,
2330 .rst_lines = omap44xx_prm_resets,
2331 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2336 * system clock and reset manager
2339 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2344 static struct omap_hwmod omap44xx_scrm_hwmod = {
2346 .class = &omap44xx_scrm_hwmod_class,
2347 .clkdm_name = "l4_wkup_clkdm",
2350 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2357 * shared level 2 memory interface
2360 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2365 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2367 .class = &omap44xx_sl2if_hwmod_class,
2368 .clkdm_name = "ivahd_clkdm",
2371 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2372 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2373 .modulemode = MODULEMODE_HWCTRL,
2380 * bidirectional, multi-drop, multi-channel two-line serial interface between
2381 * the device and external components
2384 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2386 .sysc_offs = 0x0010,
2387 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2388 SYSC_HAS_SOFTRESET),
2389 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2391 .sysc_fields = &omap_hwmod_sysc_type2,
2394 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2396 .sysc = &omap44xx_slimbus_sysc,
2400 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2401 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2402 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2403 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2404 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2407 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2409 .class = &omap44xx_slimbus_hwmod_class,
2410 .clkdm_name = "abe_clkdm",
2413 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2414 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2415 .modulemode = MODULEMODE_SWCTRL,
2418 .opt_clks = slimbus1_opt_clks,
2419 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2423 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2424 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2425 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2426 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2429 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2431 .class = &omap44xx_slimbus_hwmod_class,
2432 .clkdm_name = "l4_per_clkdm",
2435 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2436 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2437 .modulemode = MODULEMODE_SWCTRL,
2440 .opt_clks = slimbus2_opt_clks,
2441 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2445 * 'smartreflex' class
2446 * smartreflex module (monitor silicon performance and outputs a measure of
2447 * performance error)
2450 /* The IP is not compliant to type1 / type2 scheme */
2451 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2456 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2457 .sysc_offs = 0x0038,
2458 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2459 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2461 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2464 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2465 .name = "smartreflex",
2466 .sysc = &omap44xx_smartreflex_sysc,
2470 /* smartreflex_core */
2471 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2472 .sensor_voltdm_name = "core",
2475 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2476 .name = "smartreflex_core",
2477 .class = &omap44xx_smartreflex_hwmod_class,
2478 .clkdm_name = "l4_ao_clkdm",
2480 .main_clk = "smartreflex_core_fck",
2483 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2484 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2485 .modulemode = MODULEMODE_SWCTRL,
2488 .dev_attr = &smartreflex_core_dev_attr,
2491 /* smartreflex_iva */
2492 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2493 .sensor_voltdm_name = "iva",
2496 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2497 .name = "smartreflex_iva",
2498 .class = &omap44xx_smartreflex_hwmod_class,
2499 .clkdm_name = "l4_ao_clkdm",
2500 .main_clk = "smartreflex_iva_fck",
2503 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2504 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2505 .modulemode = MODULEMODE_SWCTRL,
2508 .dev_attr = &smartreflex_iva_dev_attr,
2511 /* smartreflex_mpu */
2512 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2513 .sensor_voltdm_name = "mpu",
2516 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2517 .name = "smartreflex_mpu",
2518 .class = &omap44xx_smartreflex_hwmod_class,
2519 .clkdm_name = "l4_ao_clkdm",
2520 .main_clk = "smartreflex_mpu_fck",
2523 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2524 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2525 .modulemode = MODULEMODE_SWCTRL,
2528 .dev_attr = &smartreflex_mpu_dev_attr,
2533 * spinlock provides hardware assistance for synchronizing the processes
2534 * running on multiple processors
2537 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2539 .sysc_offs = 0x0010,
2540 .syss_offs = 0x0014,
2541 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2542 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2543 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2544 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2546 .sysc_fields = &omap_hwmod_sysc_type1,
2549 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2551 .sysc = &omap44xx_spinlock_sysc,
2555 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2557 .class = &omap44xx_spinlock_hwmod_class,
2558 .clkdm_name = "l4_cfg_clkdm",
2561 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2562 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2569 * general purpose timer module with accurate 1ms tick
2570 * This class contains several variants: ['timer_1ms', 'timer']
2573 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2575 .sysc_offs = 0x0010,
2576 .syss_offs = 0x0014,
2577 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2578 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2579 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2580 SYSS_HAS_RESET_STATUS),
2581 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2582 .clockact = CLOCKACT_TEST_ICLK,
2583 .sysc_fields = &omap_hwmod_sysc_type1,
2586 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2588 .sysc = &omap44xx_timer_1ms_sysc,
2591 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2593 .sysc_offs = 0x0010,
2594 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2595 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2596 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2598 .sysc_fields = &omap_hwmod_sysc_type2,
2601 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2603 .sysc = &omap44xx_timer_sysc,
2606 /* always-on timers dev attribute */
2607 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2608 .timer_capability = OMAP_TIMER_ALWON,
2611 /* pwm timers dev attribute */
2612 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2613 .timer_capability = OMAP_TIMER_HAS_PWM,
2616 /* timers with DSP interrupt dev attribute */
2617 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2618 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
2621 /* pwm timers with DSP interrupt dev attribute */
2622 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2623 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2627 static struct omap_hwmod omap44xx_timer1_hwmod = {
2629 .class = &omap44xx_timer_1ms_hwmod_class,
2630 .clkdm_name = "l4_wkup_clkdm",
2631 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2632 .main_clk = "dmt1_clk_mux",
2635 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2636 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2637 .modulemode = MODULEMODE_SWCTRL,
2640 .dev_attr = &capability_alwon_dev_attr,
2644 static struct omap_hwmod omap44xx_timer2_hwmod = {
2646 .class = &omap44xx_timer_1ms_hwmod_class,
2647 .clkdm_name = "l4_per_clkdm",
2648 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2649 .main_clk = "cm2_dm2_mux",
2652 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2653 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2654 .modulemode = MODULEMODE_SWCTRL,
2660 static struct omap_hwmod omap44xx_timer3_hwmod = {
2662 .class = &omap44xx_timer_hwmod_class,
2663 .clkdm_name = "l4_per_clkdm",
2664 .main_clk = "cm2_dm3_mux",
2667 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2668 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2669 .modulemode = MODULEMODE_SWCTRL,
2675 static struct omap_hwmod omap44xx_timer4_hwmod = {
2677 .class = &omap44xx_timer_hwmod_class,
2678 .clkdm_name = "l4_per_clkdm",
2679 .main_clk = "cm2_dm4_mux",
2682 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2683 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2684 .modulemode = MODULEMODE_SWCTRL,
2690 static struct omap_hwmod omap44xx_timer5_hwmod = {
2692 .class = &omap44xx_timer_hwmod_class,
2693 .clkdm_name = "abe_clkdm",
2694 .main_clk = "timer5_sync_mux",
2697 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2698 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2699 .modulemode = MODULEMODE_SWCTRL,
2702 .dev_attr = &capability_dsp_dev_attr,
2706 static struct omap_hwmod omap44xx_timer6_hwmod = {
2708 .class = &omap44xx_timer_hwmod_class,
2709 .clkdm_name = "abe_clkdm",
2710 .main_clk = "timer6_sync_mux",
2713 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2714 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2715 .modulemode = MODULEMODE_SWCTRL,
2718 .dev_attr = &capability_dsp_dev_attr,
2722 static struct omap_hwmod omap44xx_timer7_hwmod = {
2724 .class = &omap44xx_timer_hwmod_class,
2725 .clkdm_name = "abe_clkdm",
2726 .main_clk = "timer7_sync_mux",
2729 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2730 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2731 .modulemode = MODULEMODE_SWCTRL,
2734 .dev_attr = &capability_dsp_dev_attr,
2738 static struct omap_hwmod omap44xx_timer8_hwmod = {
2740 .class = &omap44xx_timer_hwmod_class,
2741 .clkdm_name = "abe_clkdm",
2742 .main_clk = "timer8_sync_mux",
2745 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2746 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2747 .modulemode = MODULEMODE_SWCTRL,
2750 .dev_attr = &capability_dsp_pwm_dev_attr,
2754 static struct omap_hwmod omap44xx_timer9_hwmod = {
2756 .class = &omap44xx_timer_hwmod_class,
2757 .clkdm_name = "l4_per_clkdm",
2758 .main_clk = "cm2_dm9_mux",
2761 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2762 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2763 .modulemode = MODULEMODE_SWCTRL,
2766 .dev_attr = &capability_pwm_dev_attr,
2770 static struct omap_hwmod omap44xx_timer10_hwmod = {
2772 .class = &omap44xx_timer_1ms_hwmod_class,
2773 .clkdm_name = "l4_per_clkdm",
2774 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2775 .main_clk = "cm2_dm10_mux",
2778 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2779 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2780 .modulemode = MODULEMODE_SWCTRL,
2783 .dev_attr = &capability_pwm_dev_attr,
2787 static struct omap_hwmod omap44xx_timer11_hwmod = {
2789 .class = &omap44xx_timer_hwmod_class,
2790 .clkdm_name = "l4_per_clkdm",
2791 .main_clk = "cm2_dm11_mux",
2794 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2795 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2796 .modulemode = MODULEMODE_SWCTRL,
2799 .dev_attr = &capability_pwm_dev_attr,
2804 * universal asynchronous receiver/transmitter (uart)
2807 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2809 .sysc_offs = 0x0054,
2810 .syss_offs = 0x0058,
2811 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2812 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2813 SYSS_HAS_RESET_STATUS),
2814 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2816 .sysc_fields = &omap_hwmod_sysc_type1,
2819 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2821 .sysc = &omap44xx_uart_sysc,
2825 static struct omap_hwmod omap44xx_uart1_hwmod = {
2827 .class = &omap44xx_uart_hwmod_class,
2828 .clkdm_name = "l4_per_clkdm",
2829 .flags = HWMOD_SWSUP_SIDLE_ACT,
2830 .main_clk = "func_48m_fclk",
2833 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2834 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2835 .modulemode = MODULEMODE_SWCTRL,
2841 static struct omap_hwmod omap44xx_uart2_hwmod = {
2843 .class = &omap44xx_uart_hwmod_class,
2844 .clkdm_name = "l4_per_clkdm",
2845 .flags = HWMOD_SWSUP_SIDLE_ACT,
2846 .main_clk = "func_48m_fclk",
2849 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2850 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2851 .modulemode = MODULEMODE_SWCTRL,
2857 static struct omap_hwmod omap44xx_uart3_hwmod = {
2859 .class = &omap44xx_uart_hwmod_class,
2860 .clkdm_name = "l4_per_clkdm",
2861 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2862 .main_clk = "func_48m_fclk",
2865 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2866 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2867 .modulemode = MODULEMODE_SWCTRL,
2873 static struct omap_hwmod omap44xx_uart4_hwmod = {
2875 .class = &omap44xx_uart_hwmod_class,
2876 .clkdm_name = "l4_per_clkdm",
2877 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2878 .main_clk = "func_48m_fclk",
2881 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2882 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2883 .modulemode = MODULEMODE_SWCTRL,
2889 * 'usb_host_fs' class
2890 * full-speed usb host controller
2893 /* The IP is not compliant to type1 / type2 scheme */
2894 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2900 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2902 .sysc_offs = 0x0210,
2903 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2904 SYSC_HAS_SOFTRESET),
2905 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2907 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
2910 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2911 .name = "usb_host_fs",
2912 .sysc = &omap44xx_usb_host_fs_sysc,
2916 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2917 .name = "usb_host_fs",
2918 .class = &omap44xx_usb_host_fs_hwmod_class,
2919 .clkdm_name = "l3_init_clkdm",
2920 .main_clk = "usb_host_fs_fck",
2923 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2924 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2925 .modulemode = MODULEMODE_SWCTRL,
2931 * 'usb_host_hs' class
2932 * high-speed multi-port usb host controller
2935 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2937 .sysc_offs = 0x0010,
2938 .syss_offs = 0x0014,
2939 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2940 SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2941 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2942 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2943 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2944 .sysc_fields = &omap_hwmod_sysc_type2,
2947 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2948 .name = "usb_host_hs",
2949 .sysc = &omap44xx_usb_host_hs_sysc,
2953 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2954 .name = "usb_host_hs",
2955 .class = &omap44xx_usb_host_hs_hwmod_class,
2956 .clkdm_name = "l3_init_clkdm",
2957 .main_clk = "usb_host_hs_fck",
2960 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2961 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2962 .modulemode = MODULEMODE_SWCTRL,
2967 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2971 * In the following configuration :
2972 * - USBHOST module is set to smart-idle mode
2973 * - PRCM asserts idle_req to the USBHOST module ( This typically
2974 * happens when the system is going to a low power mode : all ports
2975 * have been suspended, the master part of the USBHOST module has
2976 * entered the standby state, and SW has cut the functional clocks)
2977 * - an USBHOST interrupt occurs before the module is able to answer
2978 * idle_ack, typically a remote wakeup IRQ.
2979 * Then the USB HOST module will enter a deadlock situation where it
2980 * is no more accessible nor functional.
2983 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2987 * Errata: USB host EHCI may stall when entering smart-standby mode
2991 * When the USBHOST module is set to smart-standby mode, and when it is
2992 * ready to enter the standby state (i.e. all ports are suspended and
2993 * all attached devices are in suspend mode), then it can wrongly assert
2994 * the Mstandby signal too early while there are still some residual OCP
2995 * transactions ongoing. If this condition occurs, the internal state
2996 * machine may go to an undefined state and the USB link may be stuck
2997 * upon the next resume.
3000 * Don't use smart standby; use only force standby,
3001 * hence HWMOD_SWSUP_MSTANDBY
3004 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3008 * 'usb_otg_hs' class
3009 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3012 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3014 .sysc_offs = 0x0404,
3015 .syss_offs = 0x0408,
3016 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3017 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3018 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3019 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3020 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3022 .sysc_fields = &omap_hwmod_sysc_type1,
3025 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3026 .name = "usb_otg_hs",
3027 .sysc = &omap44xx_usb_otg_hs_sysc,
3031 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3032 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3035 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3036 .name = "usb_otg_hs",
3037 .class = &omap44xx_usb_otg_hs_hwmod_class,
3038 .clkdm_name = "l3_init_clkdm",
3039 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3040 .main_clk = "usb_otg_hs_ick",
3043 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3044 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3045 .modulemode = MODULEMODE_HWCTRL,
3048 .opt_clks = usb_otg_hs_opt_clks,
3049 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3053 * 'usb_tll_hs' class
3054 * usb_tll_hs module is the adapter on the usb_host_hs ports
3057 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3059 .sysc_offs = 0x0010,
3060 .syss_offs = 0x0014,
3061 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3062 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3064 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3065 .sysc_fields = &omap_hwmod_sysc_type1,
3068 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3069 .name = "usb_tll_hs",
3070 .sysc = &omap44xx_usb_tll_hs_sysc,
3073 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3074 .name = "usb_tll_hs",
3075 .class = &omap44xx_usb_tll_hs_hwmod_class,
3076 .clkdm_name = "l3_init_clkdm",
3077 .main_clk = "usb_tll_hs_ick",
3080 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3081 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3082 .modulemode = MODULEMODE_HWCTRL,
3089 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3090 * overflow condition
3093 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3095 .sysc_offs = 0x0010,
3096 .syss_offs = 0x0014,
3097 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3098 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3099 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3101 .sysc_fields = &omap_hwmod_sysc_type1,
3104 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3106 .sysc = &omap44xx_wd_timer_sysc,
3107 .pre_shutdown = &omap2_wd_timer_disable,
3108 .reset = &omap2_wd_timer_reset,
3112 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3113 .name = "wd_timer2",
3114 .class = &omap44xx_wd_timer_hwmod_class,
3115 .clkdm_name = "l4_wkup_clkdm",
3116 .main_clk = "sys_32k_ck",
3119 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3120 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3121 .modulemode = MODULEMODE_SWCTRL,
3127 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3128 .name = "wd_timer3",
3129 .class = &omap44xx_wd_timer_hwmod_class,
3130 .clkdm_name = "abe_clkdm",
3131 .main_clk = "sys_32k_ck",
3134 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3135 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3136 .modulemode = MODULEMODE_SWCTRL,
3146 /* l3_main_1 -> dmm */
3147 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3148 .master = &omap44xx_l3_main_1_hwmod,
3149 .slave = &omap44xx_dmm_hwmod,
3151 .user = OCP_USER_SDMA,
3155 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3156 .master = &omap44xx_mpu_hwmod,
3157 .slave = &omap44xx_dmm_hwmod,
3159 .user = OCP_USER_MPU,
3162 /* iva -> l3_instr */
3163 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3164 .master = &omap44xx_iva_hwmod,
3165 .slave = &omap44xx_l3_instr_hwmod,
3167 .user = OCP_USER_MPU | OCP_USER_SDMA,
3170 /* l3_main_3 -> l3_instr */
3171 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3172 .master = &omap44xx_l3_main_3_hwmod,
3173 .slave = &omap44xx_l3_instr_hwmod,
3175 .user = OCP_USER_MPU | OCP_USER_SDMA,
3178 /* ocp_wp_noc -> l3_instr */
3179 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3180 .master = &omap44xx_ocp_wp_noc_hwmod,
3181 .slave = &omap44xx_l3_instr_hwmod,
3183 .user = OCP_USER_MPU | OCP_USER_SDMA,
3186 /* dsp -> l3_main_1 */
3187 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3188 .master = &omap44xx_dsp_hwmod,
3189 .slave = &omap44xx_l3_main_1_hwmod,
3191 .user = OCP_USER_MPU | OCP_USER_SDMA,
3194 /* dss -> l3_main_1 */
3195 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3196 .master = &omap44xx_dss_hwmod,
3197 .slave = &omap44xx_l3_main_1_hwmod,
3199 .user = OCP_USER_MPU | OCP_USER_SDMA,
3202 /* l3_main_2 -> l3_main_1 */
3203 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3204 .master = &omap44xx_l3_main_2_hwmod,
3205 .slave = &omap44xx_l3_main_1_hwmod,
3207 .user = OCP_USER_MPU | OCP_USER_SDMA,
3210 /* l4_cfg -> l3_main_1 */
3211 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3212 .master = &omap44xx_l4_cfg_hwmod,
3213 .slave = &omap44xx_l3_main_1_hwmod,
3215 .user = OCP_USER_MPU | OCP_USER_SDMA,
3218 /* mmc1 -> l3_main_1 */
3219 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3220 .master = &omap44xx_mmc1_hwmod,
3221 .slave = &omap44xx_l3_main_1_hwmod,
3223 .user = OCP_USER_MPU | OCP_USER_SDMA,
3226 /* mmc2 -> l3_main_1 */
3227 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3228 .master = &omap44xx_mmc2_hwmod,
3229 .slave = &omap44xx_l3_main_1_hwmod,
3231 .user = OCP_USER_MPU | OCP_USER_SDMA,
3234 /* mpu -> l3_main_1 */
3235 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3236 .master = &omap44xx_mpu_hwmod,
3237 .slave = &omap44xx_l3_main_1_hwmod,
3239 .user = OCP_USER_MPU,
3242 /* debugss -> l3_main_2 */
3243 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3244 .master = &omap44xx_debugss_hwmod,
3245 .slave = &omap44xx_l3_main_2_hwmod,
3246 .clk = "dbgclk_mux_ck",
3247 .user = OCP_USER_MPU | OCP_USER_SDMA,
3250 /* dma_system -> l3_main_2 */
3251 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3252 .master = &omap44xx_dma_system_hwmod,
3253 .slave = &omap44xx_l3_main_2_hwmod,
3255 .user = OCP_USER_MPU | OCP_USER_SDMA,
3258 /* fdif -> l3_main_2 */
3259 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3260 .master = &omap44xx_fdif_hwmod,
3261 .slave = &omap44xx_l3_main_2_hwmod,
3263 .user = OCP_USER_MPU | OCP_USER_SDMA,
3266 /* gpu -> l3_main_2 */
3267 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3268 .master = &omap44xx_gpu_hwmod,
3269 .slave = &omap44xx_l3_main_2_hwmod,
3271 .user = OCP_USER_MPU | OCP_USER_SDMA,
3274 /* hsi -> l3_main_2 */
3275 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3276 .master = &omap44xx_hsi_hwmod,
3277 .slave = &omap44xx_l3_main_2_hwmod,
3279 .user = OCP_USER_MPU | OCP_USER_SDMA,
3282 /* ipu -> l3_main_2 */
3283 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3284 .master = &omap44xx_ipu_hwmod,
3285 .slave = &omap44xx_l3_main_2_hwmod,
3287 .user = OCP_USER_MPU | OCP_USER_SDMA,
3290 /* iss -> l3_main_2 */
3291 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3292 .master = &omap44xx_iss_hwmod,
3293 .slave = &omap44xx_l3_main_2_hwmod,
3295 .user = OCP_USER_MPU | OCP_USER_SDMA,
3298 /* iva -> l3_main_2 */
3299 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3300 .master = &omap44xx_iva_hwmod,
3301 .slave = &omap44xx_l3_main_2_hwmod,
3303 .user = OCP_USER_MPU | OCP_USER_SDMA,
3306 /* l3_main_1 -> l3_main_2 */
3307 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3308 .master = &omap44xx_l3_main_1_hwmod,
3309 .slave = &omap44xx_l3_main_2_hwmod,
3311 .user = OCP_USER_MPU,
3314 /* l4_cfg -> l3_main_2 */
3315 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3316 .master = &omap44xx_l4_cfg_hwmod,
3317 .slave = &omap44xx_l3_main_2_hwmod,
3319 .user = OCP_USER_MPU | OCP_USER_SDMA,
3322 /* usb_host_fs -> l3_main_2 */
3323 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3324 .master = &omap44xx_usb_host_fs_hwmod,
3325 .slave = &omap44xx_l3_main_2_hwmod,
3327 .user = OCP_USER_MPU | OCP_USER_SDMA,
3330 /* usb_host_hs -> l3_main_2 */
3331 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3332 .master = &omap44xx_usb_host_hs_hwmod,
3333 .slave = &omap44xx_l3_main_2_hwmod,
3335 .user = OCP_USER_MPU | OCP_USER_SDMA,
3338 /* usb_otg_hs -> l3_main_2 */
3339 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3340 .master = &omap44xx_usb_otg_hs_hwmod,
3341 .slave = &omap44xx_l3_main_2_hwmod,
3343 .user = OCP_USER_MPU | OCP_USER_SDMA,
3346 /* l3_main_1 -> l3_main_3 */
3347 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3348 .master = &omap44xx_l3_main_1_hwmod,
3349 .slave = &omap44xx_l3_main_3_hwmod,
3351 .user = OCP_USER_MPU,
3354 /* l3_main_2 -> l3_main_3 */
3355 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3356 .master = &omap44xx_l3_main_2_hwmod,
3357 .slave = &omap44xx_l3_main_3_hwmod,
3359 .user = OCP_USER_MPU | OCP_USER_SDMA,
3362 /* l4_cfg -> l3_main_3 */
3363 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3364 .master = &omap44xx_l4_cfg_hwmod,
3365 .slave = &omap44xx_l3_main_3_hwmod,
3367 .user = OCP_USER_MPU | OCP_USER_SDMA,
3370 /* aess -> l4_abe */
3371 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3372 .master = &omap44xx_aess_hwmod,
3373 .slave = &omap44xx_l4_abe_hwmod,
3374 .clk = "ocp_abe_iclk",
3375 .user = OCP_USER_MPU | OCP_USER_SDMA,
3379 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3380 .master = &omap44xx_dsp_hwmod,
3381 .slave = &omap44xx_l4_abe_hwmod,
3382 .clk = "ocp_abe_iclk",
3383 .user = OCP_USER_MPU | OCP_USER_SDMA,
3386 /* l3_main_1 -> l4_abe */
3387 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3388 .master = &omap44xx_l3_main_1_hwmod,
3389 .slave = &omap44xx_l4_abe_hwmod,
3391 .user = OCP_USER_MPU | OCP_USER_SDMA,
3395 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3396 .master = &omap44xx_mpu_hwmod,
3397 .slave = &omap44xx_l4_abe_hwmod,
3398 .clk = "ocp_abe_iclk",
3399 .user = OCP_USER_MPU | OCP_USER_SDMA,
3402 /* l3_main_1 -> l4_cfg */
3403 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3404 .master = &omap44xx_l3_main_1_hwmod,
3405 .slave = &omap44xx_l4_cfg_hwmod,
3407 .user = OCP_USER_MPU | OCP_USER_SDMA,
3410 /* l3_main_2 -> l4_per */
3411 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3412 .master = &omap44xx_l3_main_2_hwmod,
3413 .slave = &omap44xx_l4_per_hwmod,
3415 .user = OCP_USER_MPU | OCP_USER_SDMA,
3418 /* l4_cfg -> l4_wkup */
3419 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3420 .master = &omap44xx_l4_cfg_hwmod,
3421 .slave = &omap44xx_l4_wkup_hwmod,
3423 .user = OCP_USER_MPU | OCP_USER_SDMA,
3426 /* mpu -> mpu_private */
3427 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3428 .master = &omap44xx_mpu_hwmod,
3429 .slave = &omap44xx_mpu_private_hwmod,
3431 .user = OCP_USER_MPU | OCP_USER_SDMA,
3434 /* l4_cfg -> ocp_wp_noc */
3435 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3436 .master = &omap44xx_l4_cfg_hwmod,
3437 .slave = &omap44xx_ocp_wp_noc_hwmod,
3439 .user = OCP_USER_MPU | OCP_USER_SDMA,
3442 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3445 .pa_start = 0x40180000,
3446 .pa_end = 0x4018ffff
3450 .pa_start = 0x401a0000,
3451 .pa_end = 0x401a1fff
3455 .pa_start = 0x401c0000,
3456 .pa_end = 0x401c5fff
3460 .pa_start = 0x401e0000,
3461 .pa_end = 0x401e1fff
3465 .pa_start = 0x401f1000,
3466 .pa_end = 0x401f13ff,
3467 .flags = ADDR_TYPE_RT
3472 /* l4_abe -> aess */
3473 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3474 .master = &omap44xx_l4_abe_hwmod,
3475 .slave = &omap44xx_aess_hwmod,
3476 .clk = "ocp_abe_iclk",
3477 .addr = omap44xx_aess_addrs,
3478 .user = OCP_USER_MPU,
3481 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3484 .pa_start = 0x49080000,
3485 .pa_end = 0x4908ffff
3489 .pa_start = 0x490a0000,
3490 .pa_end = 0x490a1fff
3494 .pa_start = 0x490c0000,
3495 .pa_end = 0x490c5fff
3499 .pa_start = 0x490e0000,
3500 .pa_end = 0x490e1fff
3504 .pa_start = 0x490f1000,
3505 .pa_end = 0x490f13ff,
3506 .flags = ADDR_TYPE_RT
3511 /* l4_abe -> aess (dma) */
3512 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3513 .master = &omap44xx_l4_abe_hwmod,
3514 .slave = &omap44xx_aess_hwmod,
3515 .clk = "ocp_abe_iclk",
3516 .addr = omap44xx_aess_dma_addrs,
3517 .user = OCP_USER_SDMA,
3520 /* l3_main_2 -> c2c */
3521 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3522 .master = &omap44xx_l3_main_2_hwmod,
3523 .slave = &omap44xx_c2c_hwmod,
3525 .user = OCP_USER_MPU | OCP_USER_SDMA,
3528 /* l4_wkup -> counter_32k */
3529 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3530 .master = &omap44xx_l4_wkup_hwmod,
3531 .slave = &omap44xx_counter_32k_hwmod,
3532 .clk = "l4_wkup_clk_mux_ck",
3533 .user = OCP_USER_MPU | OCP_USER_SDMA,
3536 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3538 .pa_start = 0x4a002000,
3539 .pa_end = 0x4a0027ff,
3540 .flags = ADDR_TYPE_RT
3545 /* l4_cfg -> ctrl_module_core */
3546 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3547 .master = &omap44xx_l4_cfg_hwmod,
3548 .slave = &omap44xx_ctrl_module_core_hwmod,
3550 .addr = omap44xx_ctrl_module_core_addrs,
3551 .user = OCP_USER_MPU | OCP_USER_SDMA,
3554 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3556 .pa_start = 0x4a100000,
3557 .pa_end = 0x4a1007ff,
3558 .flags = ADDR_TYPE_RT
3563 /* l4_cfg -> ctrl_module_pad_core */
3564 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3565 .master = &omap44xx_l4_cfg_hwmod,
3566 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
3568 .addr = omap44xx_ctrl_module_pad_core_addrs,
3569 .user = OCP_USER_MPU | OCP_USER_SDMA,
3572 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3574 .pa_start = 0x4a30c000,
3575 .pa_end = 0x4a30c7ff,
3576 .flags = ADDR_TYPE_RT
3581 /* l4_wkup -> ctrl_module_wkup */
3582 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3583 .master = &omap44xx_l4_wkup_hwmod,
3584 .slave = &omap44xx_ctrl_module_wkup_hwmod,
3585 .clk = "l4_wkup_clk_mux_ck",
3586 .addr = omap44xx_ctrl_module_wkup_addrs,
3587 .user = OCP_USER_MPU | OCP_USER_SDMA,
3590 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3592 .pa_start = 0x4a31e000,
3593 .pa_end = 0x4a31e7ff,
3594 .flags = ADDR_TYPE_RT
3599 /* l4_wkup -> ctrl_module_pad_wkup */
3600 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3601 .master = &omap44xx_l4_wkup_hwmod,
3602 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
3603 .clk = "l4_wkup_clk_mux_ck",
3604 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
3605 .user = OCP_USER_MPU | OCP_USER_SDMA,
3608 /* l3_instr -> debugss */
3609 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3610 .master = &omap44xx_l3_instr_hwmod,
3611 .slave = &omap44xx_debugss_hwmod,
3613 .user = OCP_USER_MPU | OCP_USER_SDMA,
3616 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3618 .pa_start = 0x4a056000,
3619 .pa_end = 0x4a056fff,
3620 .flags = ADDR_TYPE_RT
3625 /* l4_cfg -> dma_system */
3626 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3627 .master = &omap44xx_l4_cfg_hwmod,
3628 .slave = &omap44xx_dma_system_hwmod,
3630 .addr = omap44xx_dma_system_addrs,
3631 .user = OCP_USER_MPU | OCP_USER_SDMA,
3634 /* l4_abe -> dmic */
3635 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3636 .master = &omap44xx_l4_abe_hwmod,
3637 .slave = &omap44xx_dmic_hwmod,
3638 .clk = "ocp_abe_iclk",
3639 .user = OCP_USER_MPU,
3642 /* l4_abe -> dmic (dma) */
3643 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
3644 .master = &omap44xx_l4_abe_hwmod,
3645 .slave = &omap44xx_dmic_hwmod,
3646 .clk = "ocp_abe_iclk",
3647 .user = OCP_USER_SDMA,
3651 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3652 .master = &omap44xx_dsp_hwmod,
3653 .slave = &omap44xx_iva_hwmod,
3654 .clk = "dpll_iva_m5x2_ck",
3655 .user = OCP_USER_DSP,
3659 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3660 .master = &omap44xx_dsp_hwmod,
3661 .slave = &omap44xx_sl2if_hwmod,
3662 .clk = "dpll_iva_m5x2_ck",
3663 .user = OCP_USER_DSP,
3667 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3668 .master = &omap44xx_l4_cfg_hwmod,
3669 .slave = &omap44xx_dsp_hwmod,
3671 .user = OCP_USER_MPU | OCP_USER_SDMA,
3674 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3676 .pa_start = 0x58000000,
3677 .pa_end = 0x5800007f,
3678 .flags = ADDR_TYPE_RT
3683 /* l3_main_2 -> dss */
3684 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3685 .master = &omap44xx_l3_main_2_hwmod,
3686 .slave = &omap44xx_dss_hwmod,
3688 .addr = omap44xx_dss_dma_addrs,
3689 .user = OCP_USER_SDMA,
3692 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3694 .pa_start = 0x48040000,
3695 .pa_end = 0x4804007f,
3696 .flags = ADDR_TYPE_RT
3702 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3703 .master = &omap44xx_l4_per_hwmod,
3704 .slave = &omap44xx_dss_hwmod,
3706 .addr = omap44xx_dss_addrs,
3707 .user = OCP_USER_MPU,
3710 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3712 .pa_start = 0x58001000,
3713 .pa_end = 0x58001fff,
3714 .flags = ADDR_TYPE_RT
3719 /* l3_main_2 -> dss_dispc */
3720 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3721 .master = &omap44xx_l3_main_2_hwmod,
3722 .slave = &omap44xx_dss_dispc_hwmod,
3724 .addr = omap44xx_dss_dispc_dma_addrs,
3725 .user = OCP_USER_SDMA,
3728 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3730 .pa_start = 0x48041000,
3731 .pa_end = 0x48041fff,
3732 .flags = ADDR_TYPE_RT
3737 /* l4_per -> dss_dispc */
3738 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3739 .master = &omap44xx_l4_per_hwmod,
3740 .slave = &omap44xx_dss_dispc_hwmod,
3742 .addr = omap44xx_dss_dispc_addrs,
3743 .user = OCP_USER_MPU,
3746 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3748 .pa_start = 0x58004000,
3749 .pa_end = 0x580041ff,
3750 .flags = ADDR_TYPE_RT
3755 /* l3_main_2 -> dss_dsi1 */
3756 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3757 .master = &omap44xx_l3_main_2_hwmod,
3758 .slave = &omap44xx_dss_dsi1_hwmod,
3760 .addr = omap44xx_dss_dsi1_dma_addrs,
3761 .user = OCP_USER_SDMA,
3764 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3766 .pa_start = 0x48044000,
3767 .pa_end = 0x480441ff,
3768 .flags = ADDR_TYPE_RT
3773 /* l4_per -> dss_dsi1 */
3774 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3775 .master = &omap44xx_l4_per_hwmod,
3776 .slave = &omap44xx_dss_dsi1_hwmod,
3778 .addr = omap44xx_dss_dsi1_addrs,
3779 .user = OCP_USER_MPU,
3782 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3784 .pa_start = 0x58005000,
3785 .pa_end = 0x580051ff,
3786 .flags = ADDR_TYPE_RT
3791 /* l3_main_2 -> dss_dsi2 */
3792 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3793 .master = &omap44xx_l3_main_2_hwmod,
3794 .slave = &omap44xx_dss_dsi2_hwmod,
3796 .addr = omap44xx_dss_dsi2_dma_addrs,
3797 .user = OCP_USER_SDMA,
3800 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3802 .pa_start = 0x48045000,
3803 .pa_end = 0x480451ff,
3804 .flags = ADDR_TYPE_RT
3809 /* l4_per -> dss_dsi2 */
3810 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3811 .master = &omap44xx_l4_per_hwmod,
3812 .slave = &omap44xx_dss_dsi2_hwmod,
3814 .addr = omap44xx_dss_dsi2_addrs,
3815 .user = OCP_USER_MPU,
3818 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3820 .pa_start = 0x58006000,
3821 .pa_end = 0x58006fff,
3822 .flags = ADDR_TYPE_RT
3827 /* l3_main_2 -> dss_hdmi */
3828 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3829 .master = &omap44xx_l3_main_2_hwmod,
3830 .slave = &omap44xx_dss_hdmi_hwmod,
3832 .addr = omap44xx_dss_hdmi_dma_addrs,
3833 .user = OCP_USER_SDMA,
3836 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3838 .pa_start = 0x48046000,
3839 .pa_end = 0x48046fff,
3840 .flags = ADDR_TYPE_RT
3845 /* l4_per -> dss_hdmi */
3846 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3847 .master = &omap44xx_l4_per_hwmod,
3848 .slave = &omap44xx_dss_hdmi_hwmod,
3850 .addr = omap44xx_dss_hdmi_addrs,
3851 .user = OCP_USER_MPU,
3854 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3856 .pa_start = 0x58002000,
3857 .pa_end = 0x580020ff,
3858 .flags = ADDR_TYPE_RT
3863 /* l3_main_2 -> dss_rfbi */
3864 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3865 .master = &omap44xx_l3_main_2_hwmod,
3866 .slave = &omap44xx_dss_rfbi_hwmod,
3868 .addr = omap44xx_dss_rfbi_dma_addrs,
3869 .user = OCP_USER_SDMA,
3872 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3874 .pa_start = 0x48042000,
3875 .pa_end = 0x480420ff,
3876 .flags = ADDR_TYPE_RT
3881 /* l4_per -> dss_rfbi */
3882 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3883 .master = &omap44xx_l4_per_hwmod,
3884 .slave = &omap44xx_dss_rfbi_hwmod,
3886 .addr = omap44xx_dss_rfbi_addrs,
3887 .user = OCP_USER_MPU,
3890 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3892 .pa_start = 0x58003000,
3893 .pa_end = 0x580030ff,
3894 .flags = ADDR_TYPE_RT
3899 /* l3_main_2 -> dss_venc */
3900 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3901 .master = &omap44xx_l3_main_2_hwmod,
3902 .slave = &omap44xx_dss_venc_hwmod,
3904 .addr = omap44xx_dss_venc_dma_addrs,
3905 .user = OCP_USER_SDMA,
3908 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3910 .pa_start = 0x48043000,
3911 .pa_end = 0x480430ff,
3912 .flags = ADDR_TYPE_RT
3917 /* l4_per -> dss_venc */
3918 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3919 .master = &omap44xx_l4_per_hwmod,
3920 .slave = &omap44xx_dss_venc_hwmod,
3922 .addr = omap44xx_dss_venc_addrs,
3923 .user = OCP_USER_MPU,
3926 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
3928 .pa_start = 0x48078000,
3929 .pa_end = 0x48078fff,
3930 .flags = ADDR_TYPE_RT
3936 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3937 .master = &omap44xx_l4_per_hwmod,
3938 .slave = &omap44xx_elm_hwmod,
3940 .addr = omap44xx_elm_addrs,
3941 .user = OCP_USER_MPU | OCP_USER_SDMA,
3944 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3946 .pa_start = 0x4a10a000,
3947 .pa_end = 0x4a10a1ff,
3948 .flags = ADDR_TYPE_RT
3953 /* l4_cfg -> fdif */
3954 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3955 .master = &omap44xx_l4_cfg_hwmod,
3956 .slave = &omap44xx_fdif_hwmod,
3958 .addr = omap44xx_fdif_addrs,
3959 .user = OCP_USER_MPU | OCP_USER_SDMA,
3962 /* l4_wkup -> gpio1 */
3963 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3964 .master = &omap44xx_l4_wkup_hwmod,
3965 .slave = &omap44xx_gpio1_hwmod,
3966 .clk = "l4_wkup_clk_mux_ck",
3967 .user = OCP_USER_MPU | OCP_USER_SDMA,
3970 /* l4_per -> gpio2 */
3971 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3972 .master = &omap44xx_l4_per_hwmod,
3973 .slave = &omap44xx_gpio2_hwmod,
3975 .user = OCP_USER_MPU | OCP_USER_SDMA,
3978 /* l4_per -> gpio3 */
3979 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3980 .master = &omap44xx_l4_per_hwmod,
3981 .slave = &omap44xx_gpio3_hwmod,
3983 .user = OCP_USER_MPU | OCP_USER_SDMA,
3986 /* l4_per -> gpio4 */
3987 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3988 .master = &omap44xx_l4_per_hwmod,
3989 .slave = &omap44xx_gpio4_hwmod,
3991 .user = OCP_USER_MPU | OCP_USER_SDMA,
3994 /* l4_per -> gpio5 */
3995 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3996 .master = &omap44xx_l4_per_hwmod,
3997 .slave = &omap44xx_gpio5_hwmod,
3999 .user = OCP_USER_MPU | OCP_USER_SDMA,
4002 /* l4_per -> gpio6 */
4003 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4004 .master = &omap44xx_l4_per_hwmod,
4005 .slave = &omap44xx_gpio6_hwmod,
4007 .user = OCP_USER_MPU | OCP_USER_SDMA,
4010 /* l3_main_2 -> gpmc */
4011 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4012 .master = &omap44xx_l3_main_2_hwmod,
4013 .slave = &omap44xx_gpmc_hwmod,
4015 .user = OCP_USER_MPU | OCP_USER_SDMA,
4018 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4020 .pa_start = 0x56000000,
4021 .pa_end = 0x5600ffff,
4022 .flags = ADDR_TYPE_RT
4027 /* l3_main_2 -> gpu */
4028 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4029 .master = &omap44xx_l3_main_2_hwmod,
4030 .slave = &omap44xx_gpu_hwmod,
4032 .addr = omap44xx_gpu_addrs,
4033 .user = OCP_USER_MPU | OCP_USER_SDMA,
4036 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4038 .pa_start = 0x480b2000,
4039 .pa_end = 0x480b201f,
4040 .flags = ADDR_TYPE_RT
4045 /* l4_per -> hdq1w */
4046 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4047 .master = &omap44xx_l4_per_hwmod,
4048 .slave = &omap44xx_hdq1w_hwmod,
4050 .addr = omap44xx_hdq1w_addrs,
4051 .user = OCP_USER_MPU | OCP_USER_SDMA,
4054 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4056 .pa_start = 0x4a058000,
4057 .pa_end = 0x4a05bfff,
4058 .flags = ADDR_TYPE_RT
4064 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4065 .master = &omap44xx_l4_cfg_hwmod,
4066 .slave = &omap44xx_hsi_hwmod,
4068 .addr = omap44xx_hsi_addrs,
4069 .user = OCP_USER_MPU | OCP_USER_SDMA,
4072 /* l4_per -> i2c1 */
4073 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4074 .master = &omap44xx_l4_per_hwmod,
4075 .slave = &omap44xx_i2c1_hwmod,
4077 .user = OCP_USER_MPU | OCP_USER_SDMA,
4080 /* l4_per -> i2c2 */
4081 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4082 .master = &omap44xx_l4_per_hwmod,
4083 .slave = &omap44xx_i2c2_hwmod,
4085 .user = OCP_USER_MPU | OCP_USER_SDMA,
4088 /* l4_per -> i2c3 */
4089 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4090 .master = &omap44xx_l4_per_hwmod,
4091 .slave = &omap44xx_i2c3_hwmod,
4093 .user = OCP_USER_MPU | OCP_USER_SDMA,
4096 /* l4_per -> i2c4 */
4097 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4098 .master = &omap44xx_l4_per_hwmod,
4099 .slave = &omap44xx_i2c4_hwmod,
4101 .user = OCP_USER_MPU | OCP_USER_SDMA,
4104 /* l3_main_2 -> ipu */
4105 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4106 .master = &omap44xx_l3_main_2_hwmod,
4107 .slave = &omap44xx_ipu_hwmod,
4109 .user = OCP_USER_MPU | OCP_USER_SDMA,
4112 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4114 .pa_start = 0x52000000,
4115 .pa_end = 0x520000ff,
4116 .flags = ADDR_TYPE_RT
4121 /* l3_main_2 -> iss */
4122 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4123 .master = &omap44xx_l3_main_2_hwmod,
4124 .slave = &omap44xx_iss_hwmod,
4126 .addr = omap44xx_iss_addrs,
4127 .user = OCP_USER_MPU | OCP_USER_SDMA,
4131 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4132 .master = &omap44xx_iva_hwmod,
4133 .slave = &omap44xx_sl2if_hwmod,
4134 .clk = "dpll_iva_m5x2_ck",
4135 .user = OCP_USER_IVA,
4138 /* l3_main_2 -> iva */
4139 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4140 .master = &omap44xx_l3_main_2_hwmod,
4141 .slave = &omap44xx_iva_hwmod,
4143 .user = OCP_USER_MPU,
4146 /* l4_wkup -> kbd */
4147 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4148 .master = &omap44xx_l4_wkup_hwmod,
4149 .slave = &omap44xx_kbd_hwmod,
4150 .clk = "l4_wkup_clk_mux_ck",
4151 .user = OCP_USER_MPU | OCP_USER_SDMA,
4154 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4156 .pa_start = 0x4a0f4000,
4157 .pa_end = 0x4a0f41ff,
4158 .flags = ADDR_TYPE_RT
4163 /* l4_cfg -> mailbox */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4165 .master = &omap44xx_l4_cfg_hwmod,
4166 .slave = &omap44xx_mailbox_hwmod,
4168 .addr = omap44xx_mailbox_addrs,
4169 .user = OCP_USER_MPU | OCP_USER_SDMA,
4172 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4174 .pa_start = 0x40128000,
4175 .pa_end = 0x401283ff,
4176 .flags = ADDR_TYPE_RT
4181 /* l4_abe -> mcasp */
4182 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4183 .master = &omap44xx_l4_abe_hwmod,
4184 .slave = &omap44xx_mcasp_hwmod,
4185 .clk = "ocp_abe_iclk",
4186 .addr = omap44xx_mcasp_addrs,
4187 .user = OCP_USER_MPU,
4190 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4192 .pa_start = 0x49028000,
4193 .pa_end = 0x490283ff,
4194 .flags = ADDR_TYPE_RT
4199 /* l4_abe -> mcasp (dma) */
4200 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4201 .master = &omap44xx_l4_abe_hwmod,
4202 .slave = &omap44xx_mcasp_hwmod,
4203 .clk = "ocp_abe_iclk",
4204 .addr = omap44xx_mcasp_dma_addrs,
4205 .user = OCP_USER_SDMA,
4208 /* l4_abe -> mcbsp1 */
4209 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4210 .master = &omap44xx_l4_abe_hwmod,
4211 .slave = &omap44xx_mcbsp1_hwmod,
4212 .clk = "ocp_abe_iclk",
4213 .user = OCP_USER_MPU,
4216 /* l4_abe -> mcbsp1 (dma) */
4217 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4218 .master = &omap44xx_l4_abe_hwmod,
4219 .slave = &omap44xx_mcbsp1_hwmod,
4220 .clk = "ocp_abe_iclk",
4221 .user = OCP_USER_SDMA,
4224 /* l4_abe -> mcbsp2 */
4225 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4226 .master = &omap44xx_l4_abe_hwmod,
4227 .slave = &omap44xx_mcbsp2_hwmod,
4228 .clk = "ocp_abe_iclk",
4229 .user = OCP_USER_MPU,
4232 /* l4_abe -> mcbsp2 (dma) */
4233 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
4234 .master = &omap44xx_l4_abe_hwmod,
4235 .slave = &omap44xx_mcbsp2_hwmod,
4236 .clk = "ocp_abe_iclk",
4237 .user = OCP_USER_SDMA,
4240 /* l4_abe -> mcbsp3 */
4241 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4242 .master = &omap44xx_l4_abe_hwmod,
4243 .slave = &omap44xx_mcbsp3_hwmod,
4244 .clk = "ocp_abe_iclk",
4245 .user = OCP_USER_MPU,
4248 /* l4_abe -> mcbsp3 (dma) */
4249 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
4250 .master = &omap44xx_l4_abe_hwmod,
4251 .slave = &omap44xx_mcbsp3_hwmod,
4252 .clk = "ocp_abe_iclk",
4253 .user = OCP_USER_SDMA,
4256 /* l4_per -> mcbsp4 */
4257 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4258 .master = &omap44xx_l4_per_hwmod,
4259 .slave = &omap44xx_mcbsp4_hwmod,
4261 .user = OCP_USER_MPU | OCP_USER_SDMA,
4264 /* l4_abe -> mcpdm */
4265 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4266 .master = &omap44xx_l4_abe_hwmod,
4267 .slave = &omap44xx_mcpdm_hwmod,
4268 .clk = "ocp_abe_iclk",
4269 .user = OCP_USER_MPU,
4272 /* l4_abe -> mcpdm (dma) */
4273 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
4274 .master = &omap44xx_l4_abe_hwmod,
4275 .slave = &omap44xx_mcpdm_hwmod,
4276 .clk = "ocp_abe_iclk",
4277 .user = OCP_USER_SDMA,
4280 /* l4_per -> mcspi1 */
4281 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4282 .master = &omap44xx_l4_per_hwmod,
4283 .slave = &omap44xx_mcspi1_hwmod,
4285 .user = OCP_USER_MPU | OCP_USER_SDMA,
4288 /* l4_per -> mcspi2 */
4289 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4290 .master = &omap44xx_l4_per_hwmod,
4291 .slave = &omap44xx_mcspi2_hwmod,
4293 .user = OCP_USER_MPU | OCP_USER_SDMA,
4296 /* l4_per -> mcspi3 */
4297 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4298 .master = &omap44xx_l4_per_hwmod,
4299 .slave = &omap44xx_mcspi3_hwmod,
4301 .user = OCP_USER_MPU | OCP_USER_SDMA,
4304 /* l4_per -> mcspi4 */
4305 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4306 .master = &omap44xx_l4_per_hwmod,
4307 .slave = &omap44xx_mcspi4_hwmod,
4309 .user = OCP_USER_MPU | OCP_USER_SDMA,
4312 /* l4_per -> mmc1 */
4313 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4314 .master = &omap44xx_l4_per_hwmod,
4315 .slave = &omap44xx_mmc1_hwmod,
4317 .user = OCP_USER_MPU | OCP_USER_SDMA,
4320 /* l4_per -> mmc2 */
4321 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4322 .master = &omap44xx_l4_per_hwmod,
4323 .slave = &omap44xx_mmc2_hwmod,
4325 .user = OCP_USER_MPU | OCP_USER_SDMA,
4328 /* l4_per -> mmc3 */
4329 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4330 .master = &omap44xx_l4_per_hwmod,
4331 .slave = &omap44xx_mmc3_hwmod,
4333 .user = OCP_USER_MPU | OCP_USER_SDMA,
4336 /* l4_per -> mmc4 */
4337 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4338 .master = &omap44xx_l4_per_hwmod,
4339 .slave = &omap44xx_mmc4_hwmod,
4341 .user = OCP_USER_MPU | OCP_USER_SDMA,
4344 /* l4_per -> mmc5 */
4345 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4346 .master = &omap44xx_l4_per_hwmod,
4347 .slave = &omap44xx_mmc5_hwmod,
4349 .user = OCP_USER_MPU | OCP_USER_SDMA,
4352 /* l3_main_2 -> ocmc_ram */
4353 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4354 .master = &omap44xx_l3_main_2_hwmod,
4355 .slave = &omap44xx_ocmc_ram_hwmod,
4357 .user = OCP_USER_MPU | OCP_USER_SDMA,
4360 /* l4_cfg -> ocp2scp_usb_phy */
4361 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4362 .master = &omap44xx_l4_cfg_hwmod,
4363 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
4365 .user = OCP_USER_MPU | OCP_USER_SDMA,
4368 /* mpu_private -> prcm_mpu */
4369 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4370 .master = &omap44xx_mpu_private_hwmod,
4371 .slave = &omap44xx_prcm_mpu_hwmod,
4373 .user = OCP_USER_MPU | OCP_USER_SDMA,
4376 /* l4_wkup -> cm_core_aon */
4377 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4378 .master = &omap44xx_l4_wkup_hwmod,
4379 .slave = &omap44xx_cm_core_aon_hwmod,
4380 .clk = "l4_wkup_clk_mux_ck",
4381 .user = OCP_USER_MPU | OCP_USER_SDMA,
4384 /* l4_cfg -> cm_core */
4385 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4386 .master = &omap44xx_l4_cfg_hwmod,
4387 .slave = &omap44xx_cm_core_hwmod,
4389 .user = OCP_USER_MPU | OCP_USER_SDMA,
4392 /* l4_wkup -> prm */
4393 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4394 .master = &omap44xx_l4_wkup_hwmod,
4395 .slave = &omap44xx_prm_hwmod,
4396 .clk = "l4_wkup_clk_mux_ck",
4397 .user = OCP_USER_MPU | OCP_USER_SDMA,
4400 /* l4_wkup -> scrm */
4401 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4402 .master = &omap44xx_l4_wkup_hwmod,
4403 .slave = &omap44xx_scrm_hwmod,
4404 .clk = "l4_wkup_clk_mux_ck",
4405 .user = OCP_USER_MPU | OCP_USER_SDMA,
4408 /* l3_main_2 -> sl2if */
4409 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4410 .master = &omap44xx_l3_main_2_hwmod,
4411 .slave = &omap44xx_sl2if_hwmod,
4413 .user = OCP_USER_MPU | OCP_USER_SDMA,
4416 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4418 .pa_start = 0x4012c000,
4419 .pa_end = 0x4012c3ff,
4420 .flags = ADDR_TYPE_RT
4425 /* l4_abe -> slimbus1 */
4426 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4427 .master = &omap44xx_l4_abe_hwmod,
4428 .slave = &omap44xx_slimbus1_hwmod,
4429 .clk = "ocp_abe_iclk",
4430 .addr = omap44xx_slimbus1_addrs,
4431 .user = OCP_USER_MPU,
4434 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4436 .pa_start = 0x4902c000,
4437 .pa_end = 0x4902c3ff,
4438 .flags = ADDR_TYPE_RT
4443 /* l4_abe -> slimbus1 (dma) */
4444 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4445 .master = &omap44xx_l4_abe_hwmod,
4446 .slave = &omap44xx_slimbus1_hwmod,
4447 .clk = "ocp_abe_iclk",
4448 .addr = omap44xx_slimbus1_dma_addrs,
4449 .user = OCP_USER_SDMA,
4452 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4454 .pa_start = 0x48076000,
4455 .pa_end = 0x480763ff,
4456 .flags = ADDR_TYPE_RT
4461 /* l4_per -> slimbus2 */
4462 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4463 .master = &omap44xx_l4_per_hwmod,
4464 .slave = &omap44xx_slimbus2_hwmod,
4466 .addr = omap44xx_slimbus2_addrs,
4467 .user = OCP_USER_MPU | OCP_USER_SDMA,
4470 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4472 .pa_start = 0x4a0dd000,
4473 .pa_end = 0x4a0dd03f,
4474 .flags = ADDR_TYPE_RT
4479 /* l4_cfg -> smartreflex_core */
4480 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4481 .master = &omap44xx_l4_cfg_hwmod,
4482 .slave = &omap44xx_smartreflex_core_hwmod,
4484 .addr = omap44xx_smartreflex_core_addrs,
4485 .user = OCP_USER_MPU | OCP_USER_SDMA,
4488 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4490 .pa_start = 0x4a0db000,
4491 .pa_end = 0x4a0db03f,
4492 .flags = ADDR_TYPE_RT
4497 /* l4_cfg -> smartreflex_iva */
4498 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4499 .master = &omap44xx_l4_cfg_hwmod,
4500 .slave = &omap44xx_smartreflex_iva_hwmod,
4502 .addr = omap44xx_smartreflex_iva_addrs,
4503 .user = OCP_USER_MPU | OCP_USER_SDMA,
4506 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4508 .pa_start = 0x4a0d9000,
4509 .pa_end = 0x4a0d903f,
4510 .flags = ADDR_TYPE_RT
4515 /* l4_cfg -> smartreflex_mpu */
4516 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4517 .master = &omap44xx_l4_cfg_hwmod,
4518 .slave = &omap44xx_smartreflex_mpu_hwmod,
4520 .addr = omap44xx_smartreflex_mpu_addrs,
4521 .user = OCP_USER_MPU | OCP_USER_SDMA,
4524 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4526 .pa_start = 0x4a0f6000,
4527 .pa_end = 0x4a0f6fff,
4528 .flags = ADDR_TYPE_RT
4533 /* l4_cfg -> spinlock */
4534 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4535 .master = &omap44xx_l4_cfg_hwmod,
4536 .slave = &omap44xx_spinlock_hwmod,
4538 .addr = omap44xx_spinlock_addrs,
4539 .user = OCP_USER_MPU | OCP_USER_SDMA,
4542 /* l4_wkup -> timer1 */
4543 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4544 .master = &omap44xx_l4_wkup_hwmod,
4545 .slave = &omap44xx_timer1_hwmod,
4546 .clk = "l4_wkup_clk_mux_ck",
4547 .user = OCP_USER_MPU | OCP_USER_SDMA,
4550 /* l4_per -> timer2 */
4551 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4552 .master = &omap44xx_l4_per_hwmod,
4553 .slave = &omap44xx_timer2_hwmod,
4555 .user = OCP_USER_MPU | OCP_USER_SDMA,
4558 /* l4_per -> timer3 */
4559 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4560 .master = &omap44xx_l4_per_hwmod,
4561 .slave = &omap44xx_timer3_hwmod,
4563 .user = OCP_USER_MPU | OCP_USER_SDMA,
4566 /* l4_per -> timer4 */
4567 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4568 .master = &omap44xx_l4_per_hwmod,
4569 .slave = &omap44xx_timer4_hwmod,
4571 .user = OCP_USER_MPU | OCP_USER_SDMA,
4574 /* l4_abe -> timer5 */
4575 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4576 .master = &omap44xx_l4_abe_hwmod,
4577 .slave = &omap44xx_timer5_hwmod,
4578 .clk = "ocp_abe_iclk",
4579 .user = OCP_USER_MPU,
4582 /* l4_abe -> timer5 (dma) */
4583 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4584 .master = &omap44xx_l4_abe_hwmod,
4585 .slave = &omap44xx_timer5_hwmod,
4586 .clk = "ocp_abe_iclk",
4587 .user = OCP_USER_SDMA,
4590 /* l4_abe -> timer6 */
4591 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4592 .master = &omap44xx_l4_abe_hwmod,
4593 .slave = &omap44xx_timer6_hwmod,
4594 .clk = "ocp_abe_iclk",
4595 .user = OCP_USER_MPU,
4598 /* l4_abe -> timer6 (dma) */
4599 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4600 .master = &omap44xx_l4_abe_hwmod,
4601 .slave = &omap44xx_timer6_hwmod,
4602 .clk = "ocp_abe_iclk",
4603 .user = OCP_USER_SDMA,
4606 /* l4_abe -> timer7 */
4607 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4608 .master = &omap44xx_l4_abe_hwmod,
4609 .slave = &omap44xx_timer7_hwmod,
4610 .clk = "ocp_abe_iclk",
4611 .user = OCP_USER_MPU,
4614 /* l4_abe -> timer7 (dma) */
4615 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4616 .master = &omap44xx_l4_abe_hwmod,
4617 .slave = &omap44xx_timer7_hwmod,
4618 .clk = "ocp_abe_iclk",
4619 .user = OCP_USER_SDMA,
4622 /* l4_abe -> timer8 */
4623 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4624 .master = &omap44xx_l4_abe_hwmod,
4625 .slave = &omap44xx_timer8_hwmod,
4626 .clk = "ocp_abe_iclk",
4627 .user = OCP_USER_MPU,
4630 /* l4_abe -> timer8 (dma) */
4631 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4632 .master = &omap44xx_l4_abe_hwmod,
4633 .slave = &omap44xx_timer8_hwmod,
4634 .clk = "ocp_abe_iclk",
4635 .user = OCP_USER_SDMA,
4638 /* l4_per -> timer9 */
4639 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4640 .master = &omap44xx_l4_per_hwmod,
4641 .slave = &omap44xx_timer9_hwmod,
4643 .user = OCP_USER_MPU | OCP_USER_SDMA,
4646 /* l4_per -> timer10 */
4647 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4648 .master = &omap44xx_l4_per_hwmod,
4649 .slave = &omap44xx_timer10_hwmod,
4651 .user = OCP_USER_MPU | OCP_USER_SDMA,
4654 /* l4_per -> timer11 */
4655 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4656 .master = &omap44xx_l4_per_hwmod,
4657 .slave = &omap44xx_timer11_hwmod,
4659 .user = OCP_USER_MPU | OCP_USER_SDMA,
4662 /* l4_per -> uart1 */
4663 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4664 .master = &omap44xx_l4_per_hwmod,
4665 .slave = &omap44xx_uart1_hwmod,
4667 .user = OCP_USER_MPU | OCP_USER_SDMA,
4670 /* l4_per -> uart2 */
4671 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4672 .master = &omap44xx_l4_per_hwmod,
4673 .slave = &omap44xx_uart2_hwmod,
4675 .user = OCP_USER_MPU | OCP_USER_SDMA,
4678 /* l4_per -> uart3 */
4679 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4680 .master = &omap44xx_l4_per_hwmod,
4681 .slave = &omap44xx_uart3_hwmod,
4683 .user = OCP_USER_MPU | OCP_USER_SDMA,
4686 /* l4_per -> uart4 */
4687 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4688 .master = &omap44xx_l4_per_hwmod,
4689 .slave = &omap44xx_uart4_hwmod,
4691 .user = OCP_USER_MPU | OCP_USER_SDMA,
4694 /* l4_cfg -> usb_host_fs */
4695 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4696 .master = &omap44xx_l4_cfg_hwmod,
4697 .slave = &omap44xx_usb_host_fs_hwmod,
4699 .user = OCP_USER_MPU | OCP_USER_SDMA,
4702 /* l4_cfg -> usb_host_hs */
4703 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4704 .master = &omap44xx_l4_cfg_hwmod,
4705 .slave = &omap44xx_usb_host_hs_hwmod,
4707 .user = OCP_USER_MPU | OCP_USER_SDMA,
4710 /* l4_cfg -> usb_otg_hs */
4711 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4712 .master = &omap44xx_l4_cfg_hwmod,
4713 .slave = &omap44xx_usb_otg_hs_hwmod,
4715 .user = OCP_USER_MPU | OCP_USER_SDMA,
4718 /* l4_cfg -> usb_tll_hs */
4719 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4720 .master = &omap44xx_l4_cfg_hwmod,
4721 .slave = &omap44xx_usb_tll_hs_hwmod,
4723 .user = OCP_USER_MPU | OCP_USER_SDMA,
4726 /* l4_wkup -> wd_timer2 */
4727 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4728 .master = &omap44xx_l4_wkup_hwmod,
4729 .slave = &omap44xx_wd_timer2_hwmod,
4730 .clk = "l4_wkup_clk_mux_ck",
4731 .user = OCP_USER_MPU | OCP_USER_SDMA,
4734 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4736 .pa_start = 0x40130000,
4737 .pa_end = 0x4013007f,
4738 .flags = ADDR_TYPE_RT
4743 /* l4_abe -> wd_timer3 */
4744 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4745 .master = &omap44xx_l4_abe_hwmod,
4746 .slave = &omap44xx_wd_timer3_hwmod,
4747 .clk = "ocp_abe_iclk",
4748 .addr = omap44xx_wd_timer3_addrs,
4749 .user = OCP_USER_MPU,
4752 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4754 .pa_start = 0x49030000,
4755 .pa_end = 0x4903007f,
4756 .flags = ADDR_TYPE_RT
4761 /* l4_abe -> wd_timer3 (dma) */
4762 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4763 .master = &omap44xx_l4_abe_hwmod,
4764 .slave = &omap44xx_wd_timer3_hwmod,
4765 .clk = "ocp_abe_iclk",
4766 .addr = omap44xx_wd_timer3_dma_addrs,
4767 .user = OCP_USER_SDMA,
4771 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4772 .master = &omap44xx_mpu_hwmod,
4773 .slave = &omap44xx_emif1_hwmod,
4775 .user = OCP_USER_MPU | OCP_USER_SDMA,
4779 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4780 .master = &omap44xx_mpu_hwmod,
4781 .slave = &omap44xx_emif2_hwmod,
4783 .user = OCP_USER_MPU | OCP_USER_SDMA,
4786 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4787 &omap44xx_l3_main_1__dmm,
4789 &omap44xx_iva__l3_instr,
4790 &omap44xx_l3_main_3__l3_instr,
4791 &omap44xx_ocp_wp_noc__l3_instr,
4792 &omap44xx_dsp__l3_main_1,
4793 &omap44xx_dss__l3_main_1,
4794 &omap44xx_l3_main_2__l3_main_1,
4795 &omap44xx_l4_cfg__l3_main_1,
4796 &omap44xx_mmc1__l3_main_1,
4797 &omap44xx_mmc2__l3_main_1,
4798 &omap44xx_mpu__l3_main_1,
4799 &omap44xx_debugss__l3_main_2,
4800 &omap44xx_dma_system__l3_main_2,
4801 &omap44xx_fdif__l3_main_2,
4802 &omap44xx_gpu__l3_main_2,
4803 &omap44xx_hsi__l3_main_2,
4804 &omap44xx_ipu__l3_main_2,
4805 &omap44xx_iss__l3_main_2,
4806 &omap44xx_iva__l3_main_2,
4807 &omap44xx_l3_main_1__l3_main_2,
4808 &omap44xx_l4_cfg__l3_main_2,
4809 /* &omap44xx_usb_host_fs__l3_main_2, */
4810 &omap44xx_usb_host_hs__l3_main_2,
4811 &omap44xx_usb_otg_hs__l3_main_2,
4812 &omap44xx_l3_main_1__l3_main_3,
4813 &omap44xx_l3_main_2__l3_main_3,
4814 &omap44xx_l4_cfg__l3_main_3,
4815 &omap44xx_aess__l4_abe,
4816 &omap44xx_dsp__l4_abe,
4817 &omap44xx_l3_main_1__l4_abe,
4818 &omap44xx_mpu__l4_abe,
4819 &omap44xx_l3_main_1__l4_cfg,
4820 &omap44xx_l3_main_2__l4_per,
4821 &omap44xx_l4_cfg__l4_wkup,
4822 &omap44xx_mpu__mpu_private,
4823 &omap44xx_l4_cfg__ocp_wp_noc,
4824 &omap44xx_l4_abe__aess,
4825 &omap44xx_l4_abe__aess_dma,
4826 &omap44xx_l3_main_2__c2c,
4827 &omap44xx_l4_wkup__counter_32k,
4828 &omap44xx_l4_cfg__ctrl_module_core,
4829 &omap44xx_l4_cfg__ctrl_module_pad_core,
4830 &omap44xx_l4_wkup__ctrl_module_wkup,
4831 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4832 &omap44xx_l3_instr__debugss,
4833 &omap44xx_l4_cfg__dma_system,
4834 &omap44xx_l4_abe__dmic,
4835 &omap44xx_l4_abe__dmic_dma,
4837 /* &omap44xx_dsp__sl2if, */
4838 &omap44xx_l4_cfg__dsp,
4839 &omap44xx_l3_main_2__dss,
4840 &omap44xx_l4_per__dss,
4841 &omap44xx_l3_main_2__dss_dispc,
4842 &omap44xx_l4_per__dss_dispc,
4843 &omap44xx_l3_main_2__dss_dsi1,
4844 &omap44xx_l4_per__dss_dsi1,
4845 &omap44xx_l3_main_2__dss_dsi2,
4846 &omap44xx_l4_per__dss_dsi2,
4847 &omap44xx_l3_main_2__dss_hdmi,
4848 &omap44xx_l4_per__dss_hdmi,
4849 &omap44xx_l3_main_2__dss_rfbi,
4850 &omap44xx_l4_per__dss_rfbi,
4851 &omap44xx_l3_main_2__dss_venc,
4852 &omap44xx_l4_per__dss_venc,
4853 &omap44xx_l4_per__elm,
4854 &omap44xx_l4_cfg__fdif,
4855 &omap44xx_l4_wkup__gpio1,
4856 &omap44xx_l4_per__gpio2,
4857 &omap44xx_l4_per__gpio3,
4858 &omap44xx_l4_per__gpio4,
4859 &omap44xx_l4_per__gpio5,
4860 &omap44xx_l4_per__gpio6,
4861 &omap44xx_l3_main_2__gpmc,
4862 &omap44xx_l3_main_2__gpu,
4863 &omap44xx_l4_per__hdq1w,
4864 &omap44xx_l4_cfg__hsi,
4865 &omap44xx_l4_per__i2c1,
4866 &omap44xx_l4_per__i2c2,
4867 &omap44xx_l4_per__i2c3,
4868 &omap44xx_l4_per__i2c4,
4869 &omap44xx_l3_main_2__ipu,
4870 &omap44xx_l3_main_2__iss,
4871 /* &omap44xx_iva__sl2if, */
4872 &omap44xx_l3_main_2__iva,
4873 &omap44xx_l4_wkup__kbd,
4874 &omap44xx_l4_cfg__mailbox,
4875 &omap44xx_l4_abe__mcasp,
4876 &omap44xx_l4_abe__mcasp_dma,
4877 &omap44xx_l4_abe__mcbsp1,
4878 &omap44xx_l4_abe__mcbsp1_dma,
4879 &omap44xx_l4_abe__mcbsp2,
4880 &omap44xx_l4_abe__mcbsp2_dma,
4881 &omap44xx_l4_abe__mcbsp3,
4882 &omap44xx_l4_abe__mcbsp3_dma,
4883 &omap44xx_l4_per__mcbsp4,
4884 &omap44xx_l4_abe__mcpdm,
4885 &omap44xx_l4_abe__mcpdm_dma,
4886 &omap44xx_l4_per__mcspi1,
4887 &omap44xx_l4_per__mcspi2,
4888 &omap44xx_l4_per__mcspi3,
4889 &omap44xx_l4_per__mcspi4,
4890 &omap44xx_l4_per__mmc1,
4891 &omap44xx_l4_per__mmc2,
4892 &omap44xx_l4_per__mmc3,
4893 &omap44xx_l4_per__mmc4,
4894 &omap44xx_l4_per__mmc5,
4895 &omap44xx_l3_main_2__mmu_ipu,
4896 &omap44xx_l4_cfg__mmu_dsp,
4897 &omap44xx_l3_main_2__ocmc_ram,
4898 &omap44xx_l4_cfg__ocp2scp_usb_phy,
4899 &omap44xx_mpu_private__prcm_mpu,
4900 &omap44xx_l4_wkup__cm_core_aon,
4901 &omap44xx_l4_cfg__cm_core,
4902 &omap44xx_l4_wkup__prm,
4903 &omap44xx_l4_wkup__scrm,
4904 /* &omap44xx_l3_main_2__sl2if, */
4905 &omap44xx_l4_abe__slimbus1,
4906 &omap44xx_l4_abe__slimbus1_dma,
4907 &omap44xx_l4_per__slimbus2,
4908 &omap44xx_l4_cfg__smartreflex_core,
4909 &omap44xx_l4_cfg__smartreflex_iva,
4910 &omap44xx_l4_cfg__smartreflex_mpu,
4911 &omap44xx_l4_cfg__spinlock,
4912 &omap44xx_l4_wkup__timer1,
4913 &omap44xx_l4_per__timer2,
4914 &omap44xx_l4_per__timer3,
4915 &omap44xx_l4_per__timer4,
4916 &omap44xx_l4_abe__timer5,
4917 &omap44xx_l4_abe__timer5_dma,
4918 &omap44xx_l4_abe__timer6,
4919 &omap44xx_l4_abe__timer6_dma,
4920 &omap44xx_l4_abe__timer7,
4921 &omap44xx_l4_abe__timer7_dma,
4922 &omap44xx_l4_abe__timer8,
4923 &omap44xx_l4_abe__timer8_dma,
4924 &omap44xx_l4_per__timer9,
4925 &omap44xx_l4_per__timer10,
4926 &omap44xx_l4_per__timer11,
4927 &omap44xx_l4_per__uart1,
4928 &omap44xx_l4_per__uart2,
4929 &omap44xx_l4_per__uart3,
4930 &omap44xx_l4_per__uart4,
4931 /* &omap44xx_l4_cfg__usb_host_fs, */
4932 &omap44xx_l4_cfg__usb_host_hs,
4933 &omap44xx_l4_cfg__usb_otg_hs,
4934 &omap44xx_l4_cfg__usb_tll_hs,
4935 &omap44xx_l4_wkup__wd_timer2,
4936 &omap44xx_l4_abe__wd_timer3,
4937 &omap44xx_l4_abe__wd_timer3_dma,
4938 &omap44xx_mpu__emif1,
4939 &omap44xx_mpu__emif2,
4943 int __init omap44xx_hwmod_init(void)
4946 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);